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  • ea638eb2d3
         Merge pull request #25 from open-sdr/dot11zynq master Jinghao Shi 2023-01-28 21:08:45 -0800
  • 19acdbe82f
         Merge pull request #6 from ytakeuch/dot11zynq #25 Jiao Xianjun 2023-01-28 12:00:50 +0100
  • 583753829d
         Merge pull request #7 from open-sdr/pre-release Jiao Xianjun 2023-01-28 11:56:19 +0100
  • 36c6b0f59a Add neptunesdr to related files Xianjun Jiao 2023-01-16 13:40:22 +0100
  • 7e8b44439a fix unsigned signals to signed signals Yoji Takeuchi 2023-01-16 12:56:24 +0900
  • 3f645e30f4 Add antsdr/e200 and sdrpi Xianjun Jiao 2023-01-09 16:00:47 +0100
  • 8aa784707a Change the phase control value to the most safe one Xianjun Jiao 2023-01-09 15:57:28 +0100
  • b2e08ff46e Add precise sample_in_strobe phase control into dot11_tb.v for debugging the back luck FPGA loopback issue Xianjun Jiao 2023-01-09 15:56:17 +0100
  • db87c8d8a9 Fix the ofdm_symbol_eq_out_pulse according to the new euqalizer states Xianjun Jiao 2023-01-09 15:55:10 +0100
  • b7ba58b60a Add centralized DBG switch Xianjun Jiao 2023-01-09 15:54:20 +0100
  • ec2a5e8105 Update script for vivado 2021.1 Xianjun Jiao 2023-01-09 15:50:30 +0100
  • f59c9418a7 Add DEBUG but not enabled Xianjun Jiao 2023-01-09 15:49:23 +0100
  • ad5a5206d3 Remove floating connections Xianjun Jiao 2023-01-09 15:48:23 +0100
  • 95e93cadfd LVPE correction before estimation - Add state in equalizer and rename others - Add new dumper files in testbench to check with MATLAB thavinga 2023-01-09 15:45:05 +0100
  • b0df85040f Add FFT window shift register thavinga 2023-01-09 15:40:42 +0100
  • 1b0354f85d Avoid phy_len_calculation out of the watchdog reset scope to have stable value before the next long_preamble_detected Xianjun Jiao 2023-01-09 15:33:57 +0100
  • e83599a85e Enable threshold scale for receiver and disable power trigger for watchdog by default Xianjun Jiao 2023-01-09 15:32:48 +0100
  • 1043429762 signal watchdog only work while rssi above threshold: power_trigger valid Xianjun Jiao 2023-01-09 15:31:52 +0100
  • 54bdff7348 Make minimum pkt length configurable for signal_watchdog Xianjun Jiao 2023-01-09 15:30:20 +0100
  • 75979e165a Add fake random +/-1 input while input are 0s: to avoid receiver reset during self-rx-muting (packet sending) Xianjun Jiao 2023-01-09 15:29:33 +0100
  • 73475306b7 Add phy len indication for decoding latency prediciton: Add n_ofdm_sym, n_bit_in_last_sym and phy_len_valid to openofdm_rx ip Xianjun Jiao 2023-01-09 15:28:25 +0100
  • 4359e4f96d Add phy len log into dot11_tb Xianjun Jiao 2023-01-09 15:25:29 +0100
  • 8ce830c262 Shrink the bits of num_bits_to_decode and deinter_out_count: and adapt the verilog/ofdm_decoder.v accordingly Xianjun Jiao 2023-01-09 15:24:42 +0100
  • efa844bf0c Adapt CPE/LVPE calculation thavinga 2023-01-09 15:20:16 +0100
  • 27392f217f Adapt the test bench to align with ... Xianjun Jiao 2023-01-09 14:51:55 +0100
  • e978f30de6 Resolve the cpe/lvpe overflow issue Xianjun Jiao 2023-01-09 14:51:06 +0100
  • f455472288 Feed data to ofdm decoder earlier in case a data is missed (arrive too early for ofdm decoder) Xianjun Jiao 2023-01-09 14:50:22 +0100
  • 71c9b42d78 Reset internally equalizer after it is disabled to prepare for next round enable Xianjun Jiao 2023-01-09 14:49:31 +0100
  • 8e59685c65 Let sync short restart earlier before the end of current packet decoding, so that the next packet can come earlier (smaller inter packet gap is achieved) Xianjun Jiao 2023-01-09 14:48:34 +0100
  • e65ee43101 Make some basic block simpler and its delay more deterministic Xianjun Jiao 2023-01-09 14:47:34 +0100
  • a1e1e0090b Add threshold_scale and enable it by default: sync short works at low SNR and the receiver sensitivity is better Xianjun Jiao 2023-01-09 14:43:34 +0100
  • 6a8818fe5f extend the status_code to more formated style Xianjun Jiao 2023-01-09 14:40:46 +0100
  • 2747d431f9 fix viterbi decoder logging issue Wei Liu 2023-01-05 16:47:07 +0100
  • fe93170efc log all header bits, also when error occors Wei Liu 2023-01-05 16:45:43 +0100
  • c9f3d280a3 clean up log file, prolong simulation at the end by 300 sp Wei Liu 2023-01-05 16:38:51 +0100
  • f3bf82a05b add support for antsdr e200 black_pigeon 2022-10-22 00:58:18 +0800
  • 3d0a40958c Add neptunesdr Xianjun Jiao 2022-10-16 22:09:17 +0200
  • 0c2c2d7f76
         Merge pull request #24 from redfast00/fix-reserved-ht-header Jinghao Shi 2022-08-17 23:47:32 -0700
  • a77a1abd01
         Fix reserved bit in SIG-HT header #24 redfast00 2022-08-18 08:13:56 +0200
  • 76986e99d3 Update parse_board_name.tcl HexSDR 2022-08-05 23:49:49 +0800
  • 8a74580ad1 Update create_vivado_proj.sh HexSDR 2022-08-05 23:49:05 +0800
  • 707cb99a90 Remove the huge logging thing in dot11_tb.v Xianjun Jiao 2022-07-15 12:10:03 +0200
  • 864096ac05
         Merge pull request #21 from jhshi/dependabot/pip/numpy-1.22.0 Jinghao Shi 2022-06-21 17:34:43 -0700
  • f6679c7f18
         Bump numpy from 1.11.2 to 1.22.0 #21 dependabot[bot] 2022-06-21 21:12:55 +0000
  • cd8eb01a35
         Bump numpy from 1.11.2 to 1.21.0 #20 dependabot[bot] 2022-06-17 21:11:03 +0000
  • 064bbe4250 Auto stop the simulation at the end of iq sample file Xianjun Jiao 2022-05-16 09:53:07 +0200
  • f6fd0a2a85 Minor cleaning Xianjun Jiao 2022-05-16 09:52:24 +0200
  • 7622d7aaa0 Disable signal watch dog for normal simulation in the tb Xianjun Jiao 2022-05-16 09:51:30 +0200
  • 55f77bb16b Connect pkt_len from dot11 to signal watch dog in the tb Xianjun Jiao 2022-05-16 09:51:01 +0200
  • cb6b566d5f Move all signal logging to dot11_tb.v thavinga 2022-05-16 09:33:19 +0200
  • 1659c01ac7 Add conditional compiling framework Xianjun Jiao 2022-05-13 13:24:41 +0200
  • a7b95b492c Workaround to supress the error message when the 1st time run simulation Xianjun Jiao 2022-05-13 13:21:19 +0200
  • ac1a75e55a
         Change the device/board to 7020 for low-end device friendly (Avoid the license issue in the default case) Jiao Xianjun 2022-05-11 10:30:18 +0200
  • 0ab83ce223
         Merge pull request #19 from open-sdr/dot11zynq Jinghao Shi 2022-04-01 15:48:52 -0700
  • 5d4e72f66e
         Merge pull request #1 from open-sdr/pre-release #19 Jiao Xianjun 2022-04-01 11:07:17 +0200
  • 4168aa8c7a Add slv_reg1[4] for option of disabling all smoothing Xianjun Jiao 2022-03-29 12:50:31 +0200
  • 39911461ef Fix the issue of adrv9364z7020: demod_is_ongoing always high. dot11 stuck at state 3 Seems new viter decoder IP core does not need this complicated CE signal vit_ce in ofdm_decoder.v Setting the vit-ce to always 1 fixed the issue Xianjun Jiao 2022-03-23 14:26:41 +0100
  • 44c8846072 Add more test vectors into testing_inputs/simulated Xianjun Jiao 2022-03-16 15:07:48 +0100
  • f08c76ca3d Add signal_watchdog module to prevent fake demod in early phase: 1. If strong DC or low frequency sing wave like signal (suspect it is generated by ad9361 during some self-calibration like operation), put the receiver into reset 2. If the signal/header is valid, but the packet length is abnormal (signal_len<14 || signal_len>max_signal_len_th), reset the receiver Xianjun Jiao 2022-03-15 16:03:40 +0100
  • e77f1ba70b Add git rev tracking to reg 31 Xianjun Jiao 2022-03-15 15:57:57 +0100
  • 954bae4e77 Add a test vector fake-demod-0.txt that could cause fake demodulation Xianjun Jiao 2022-03-15 15:53:36 +0100
  • 40b3e59958 remove unnecessary atan_lut files Xianjun Jiao 2022-03-15 15:52:05 +0100
  • 4ad09c44c3
         Merge pull request #18 from open-sdr/dot11zynq Jinghao Shi 2022-01-28 11:11:57 -0800
  • 566e82f43e Add more clock cases into dot11_tb.v #18 Xianjun Jiao 2022-01-28 12:17:16 +0100
  • 030cdb34ca Add force ht smoothing option: > 1. Leave the module always enabled, so the slv_reg1 is free > 2. Use the slv_reg1 to force ht smoothing > 3. By default, the smoothing option of the receiver is still controlled by the received ht packet Xianjun Jiao 2022-01-28 12:15:49 +0100
  • 23e61e6a29 Avoid equalizer module processing HT_STF symbol mmehari 2022-01-04 22:45:47 +0100
  • 0c75a8e8f2 bug fix: remaining packet length calculation mmehari 2022-01-04 22:44:31 +0100
  • 8730912d6f feature update: sampling frequency offset (SFO) compensation mmehari 2022-01-04 22:26:57 +0100
  • b40c221e67 Advance phase correction value by guard interval size mmehari 2022-01-04 22:25:38 +0100
  • 85b1adbec7 bug fix: increase phase calculation delay by 1 CLK mmehari 2022-01-04 22:22:00 +0100
  • e257d3373b storage update: A-MPDU decoding mmehari 2022-01-04 22:20:44 +0100
  • af855d8c10 Save channel gain information of HT-LTF mmehari 2022-01-04 22:19:40 +0100
  • 48aade0190 provide demod_soft_bits and demod_soft_bits_pos signals out mmehari 2022-01-04 22:18:23 +0100
  • 84039d7368 Don't catagorize IQ modulation as Q-BPSK or BPSK when I and Q components have the same magnitude mmehari 2022-01-04 22:17:12 +0100
  • d2d5494f57 LTF cross-correlation window update: 16->32 complex samples mmehari 2022-01-04 22:16:18 +0100
  • 36c738fe98 phase estimation update: quadrant quantization from 256 slices -> 512 slices mmehari 2022-01-04 22:15:16 +0100
  • 53679a107f integer division rounding fix during phase offset calculation mmehari 2022-01-04 22:12:45 +0100
  • 82d2d456e5 keep significant bits while performing division during phase calculation mmehari 2022-01-04 22:11:50 +0100
  • d9649eb614 phase register size reduction: 32bit -> 16bit mmehari 2022-01-04 22:10:36 +0100
  • f3e95eaa92 long preamble detection method update: cross-correlation inter-peak gap distance -> 1st peak detection mmehari 2022-01-04 22:07:54 +0100
  • aaa8ef3ce5 HT/non_HT detection requires at most 9 clocks mmehari 2022-01-04 22:05:38 +0100
  • 8bc2d7f0a4 channel smoothing update based on HT-SIG field mmehari 2022-01-04 22:03:03 +0100
  • 171ef8b27a A-MPDU decoding support mmehari 2022-01-04 22:01:58 +0100
  • 1a9246fd24 Provide ht_aggregation signal out mmehari 2022-01-04 22:00:55 +0100
  • c3035cf985
         Merge pull request #15 from open-sdr/dot11zynq Jinghao Shi 2021-01-08 10:37:24 -0800
  • f83d179cbe Provide ht_sgi signal out #15 mmehari 2020-11-06 13:20:15 +0100
  • d0f271bdc8
         Merge pull request #14 from open-sdr/dot11zynq Jinghao Shi 2020-10-19 02:01:39 -0700
  • d331e66a31 add necessary port as trigger for iq capture feature in openwifi #14 Xianjun Jiao 2020-10-19 09:22:54 +0200
  • 2c57c0a096
         Merge pull request #13 from f380cedric/patch-1 Jinghao Shi 2020-10-12 10:34:43 -0700
  • a7efc6cb97
         Typo #13 f380cedric 2020-10-12 15:52:18 +0200
  • fb5fa6a744
         Merge pull request #12 from open-sdr/dot11zynq Jinghao Shi 2020-10-08 02:17:22 -0700
  • 8714c30857 output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux #12 Xianjun Jiao 2020-10-08 10:06:03 +0200
  • 229da948ae
         Merge pull request #11 from open-sdr/dot11zynq Jinghao Shi 2020-09-03 23:49:55 -0700
  • 539133f453 make the code more testbench friendly #11 Xianjun Jiao 2020-09-02 21:59:37 +0200
  • 2b3a043e8c turn on soft_decoding in dot11_tb.v Xianjun Jiao 2020-09-02 17:15:11 +0200
  • 6d60fceed2 fix the project_name and script_file in openofdm_rx_ultra_scale.tcl Xianjun Jiao 2020-09-02 17:05:18 +0200
  • bf043af712 change the latency of divider from automatic 60 clocks to the original 36 clock Xianjun Jiao 2020-09-02 16:49:59 +0200
  • b86951097c 802.11n rx performance fix when used different clock rates (i.e. 100MHz vs 200MHz) mmehari 2020-08-30 15:23:07 +0200
  • d7f5806790 fix the atan_addr overflow issue (phase.v) Xianjun Jiao 2020-08-29 14:48:38 +0200
  • 8c59d3a8dd channel estimation update: frequency domain averaging mmehari 2020-08-29 11:41:32 +0200