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fix unsigned signals to signed signals

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This commit is contained in:
Yoji Takeuchi 2023-01-16 12:56:24 +09:00
parent f3bf82a05b
commit 7e8b44439a
1 changed files with 2 additions and 2 deletions
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4
verilog/dot11.v
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@ -12,11 +12,11 @@ module dot11 (
//input [31:0] set_data,
// add ports for register based inputs
input [10:0] power_thres,
input signed [10:0] power_thres,
input [31:0] min_plateau,
// INPUT: RSSI
input [10:0] rssi_half_db,
input signed [10:0] rssi_half_db,
// INPUT: I/Q sample
input [31:0] sample_in,
input sample_in_strobe,