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https://github.com/jhshi/openofdm.git
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Merge pull request #14 from open-sdr/dot11zynq
add necessary port as trigger for iq capture feature in openwifi
This commit is contained in:
Jinghao Shi
GitHub
commit
d0f271bdc8
@ -183,8 +183,8 @@ set files [list \
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[file normalize "${origin_dir}/../openwifi-hw/ip/xpu/src/phy_rx_parse.v"] \
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[file normalize "${origin_dir}/../openwifi-hw/ip/side_ch/src/side_ch_control.v"] \
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[file normalize "${origin_dir}/../openwifi-hw/ip/side_ch/src/side_ch_m_axis.v"] \
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[file normalize "${origin_dir}/../openwifi-hw/ip_repo/ultra_scale/fifo64_1clk_dep4k/src/fifo64_1clk_dep4k_fifo_generator_0_0/fifo64_1clk_dep4k_fifo_generator_0_0.xci"]\
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[file normalize "${origin_dir}/../openwifi-hw/ip_repo/ultra_scale/fifo64_1clk_dep4k/src/fifo64_1clk_dep4k.v"]\
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[file normalize "${origin_dir}/../openwifi-hw/ip_repo/ultra_scale/fifo64_1clk/src/fifo64_1clk_fifo_generator_0_0/fifo64_1clk_fifo_generator_0_0.xci"]\
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[file normalize "${origin_dir}/../openwifi-hw/ip_repo/ultra_scale/fifo64_1clk/src/fifo64_1clk.v"]\
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]
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# If you want to make a copy of the file to new src folder, use following command
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# set imported_files [import_files -fileset sources_1 $files]
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@ -853,6 +853,8 @@ always @(posedge clock) begin
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end
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S_HT_LTS: begin
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pkt_header_valid <= 0;
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pkt_header_valid_strobe <= 0;
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short_gi <= ht_sgi;
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if (sync_long_out_strobe) begin
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sync_long_out_count <= sync_long_out_count + 1;
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@ -19,7 +19,7 @@ localparam integer C_S00_AXIS_TDATA_WIDTH = 64;
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localparam integer C_M00_AXIS_TDATA_WIDTH = 64;
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localparam integer WAIT_COUNT_BITS = 5;
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localparam integer MAX_NUM_DMA_SYMBOL = 4096; // the fifo depth inside m_axis
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localparam integer MAX_NUM_DMA_SYMBOL = 8192; // the fifo depth inside m_axis
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function integer clogb2 (input integer bit_depth);
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begin
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@ -49,6 +49,7 @@ wire [31:0] sync_long_metric;
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wire sync_long_metric_stb;
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wire long_preamble_detected;
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wire [31:0] phase_offset_taken;
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wire [31:0] equalizer_out;
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wire equalizer_out_strobe;
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@ -105,17 +106,24 @@ wire addr3_valid;
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wire m_axis_start_1trans;
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wire [63:0] data_to_ps;
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wire data_to_ps_valid;
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wire [12:0] m_axis_data_count;
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wire [(MAX_BIT_NUM_DMA_SYMBOL-1):0] m_axis_data_count;
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wire fulln_to_pl;
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wire M_AXIS_TVALID;
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wire M_AXIS_TLAST;
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reg slv_reg_wren_signal;
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reg [4:0] axi_awaddr_core;
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reg m_axis_start_ext_trigger;
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reg [3:0] num_eq;
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// iq capture configuration
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reg iq_capture;
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reg [3:0] iq_trigger_select;
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reg signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_th;
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reg [(GPIO_STATUS_WIDTH-2):0] gain_th;
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reg [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] pre_trigger_len;
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reg [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] iq_len_target;
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reg set_stb;
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reg [7:0] set_addr;
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reg [31:0] set_data;
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@ -147,6 +155,11 @@ integer file_i, file_q, file_rssi_half_db, iq_sample_file;
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`define SPEED_100M // remove this to use 200M
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localparam integer IQ_CAPTURE = 1; //0 -- CSI; 1 -- IQ
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localparam integer IQ_TRIGGER_SELECT = 6;
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localparam integer PRE_TRIGGER_LEN = 3;
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localparam integer IQ_LEN_TARGET = 7;
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//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_ht_unsupport_openwifi.txt"
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//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_ht_sig_openwifi.txt"
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//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_sig_openwifi.txt"
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@ -171,7 +184,13 @@ initial begin
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slv_reg_wren_signal = 0;
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axi_awaddr_core = 0;
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m_axis_start_ext_trigger = 0;
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iq_capture = IQ_CAPTURE;
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iq_trigger_select = IQ_TRIGGER_SELECT;
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rssi_th = 0;
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gain_th = 0;
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pre_trigger_len = PRE_TRIGGER_LEN;
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iq_len_target = IQ_LEN_TARGET;
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clock = 0;
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reset = 1;
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@ -357,7 +376,8 @@ end
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side_ch_control # (
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.TSF_TIMER_WIDTH(TSF_TIMER_WIDTH), // according to 802.11 standard
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.GPIO_STATUS_WIDTH(GPIO_STATUS_WIDTH),
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.RSSI_HALF_DB_WIDTH(RSSI_HALF_DB_WIDTH),
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.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
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.IQ_DATA_WIDTH(IQ_DATA_WIDTH),
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.C_S_AXIS_TDATA_WIDTH(C_S00_AXIS_TDATA_WIDTH),
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@ -368,14 +388,21 @@ side_ch_control # (
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.rstn(~reset),
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// from pl
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.gpio_status(34),
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.rssi_half_db(54),
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.tsf_runtime_val(64'd123456),
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.iq(sample_in),
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.iq_strobe(sample_in_strobe),
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.demod_is_ongoing(demod_is_ongoing),
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.ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse),
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.long_preamble_detected(long_preamble_detected),
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.short_preamble_detected(short_preamble_detected),
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.ht_unsupport(ht_unsupport),
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.pkt_rate(pkt_rate),
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.pkt_len(pkt_len),
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.csi(csi),
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.csi_valid(csi_valid),
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.phase_offset_taken(phase_offset_taken),
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.equalizer(equalizer_out),
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.equalizer_valid(equalizer_out_strobe),
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@ -398,11 +425,19 @@ side_ch_control # (
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// from arm
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.slv_reg_wren_signal(slv_reg_wren_signal), // to capture m axis num dma symbol write, so that auto trigger start
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.axi_awaddr_core(axi_awaddr_core),
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.iq_capture(iq_capture),
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.iq_trigger_select(iq_trigger_select),
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.rssi_th(rssi_th),
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.gain_th(gain_th),
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.pre_trigger_len(pre_trigger_len),
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.iq_len_target(iq_len_target),
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.FC_target(16'd3243),
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.addr1_target(32'd23343),
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.match_cfg(1),
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.addr2_target(32'd98765),
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.match_cfg(0),
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.num_eq({1'd0, num_eq[2:0]}),
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.m_axis_start_mode(1),
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.m_axis_start_ext_trigger(m_axis_start_ext_trigger),
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.m_axis_start_ext_trigger(),
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// s_axis
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.data_to_pl(),
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@ -525,6 +560,7 @@ dot11 dot11_inst (
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.long_preamble_detected(long_preamble_detected),
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.sync_long_out(sync_long_out),
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.sync_long_out_strobe(sync_long_out_strobe),
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.phase_offset_taken(phase_offset_taken),
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.sync_long_state(sync_long_state),
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.equalizer_out(equalizer_out),
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@ -18,6 +18,8 @@
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output wire demod_is_ongoing, // this needs to be corrected further to indicate actual RF on going regardless the latency
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// output wire pkt_ht,
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output wire short_preamble_detected,
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output wire long_preamble_detected,
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output wire pkt_header_valid,
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output wire pkt_header_valid_strobe,
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output wire ht_unsupport,
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@ -144,13 +146,13 @@
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.power_trigger(),
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// sync short
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.short_preamble_detected(),
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.short_preamble_detected(short_preamble_detected),
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.phase_offset(),
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// sync long
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.sync_long_metric(),
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.sync_long_metric_stb(),
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.long_preamble_detected(),
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.long_preamble_detected(long_preamble_detected),
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.sync_long_out(),
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.sync_long_out_strobe(),
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.phase_offset_taken(phase_offset_taken),
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