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Fix the ofdm_symbol_eq_out_pulse according to the new euqalizer states

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Xianjun Jiao 2023-01-09 15:55:10 +01:00
parent b7ba58b60a
commit db87c8d8a9
1 changed files with 1 additions and 1 deletions
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verilog/dot11.v
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@ -141,7 +141,7 @@ assign n_bit_in_last_sym = n_bit_in_last_sym_tmp[9:0];
////////////////////////////////////////////////////////////////////////////////
`DEBUG_PREFIX reg [3:0] equalizer_state_reg;
assign ofdm_symbol_eq_out_pulse = (equalizer_state==4 && equalizer_state_reg==7);
assign ofdm_symbol_eq_out_pulse = (equalizer_state==4 && equalizer_state_reg==8);
always @(posedge clock) begin
if (reset==1) begin