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Move all signal logging to dot11_tb.v

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This commit is contained in:
thavinga 2022-05-16 09:33:19 +02:00
parent 1659c01ac7
commit cb6b566d5f
4 changed files with 195 additions and 296 deletions
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305
verilog/dot11_tb.v
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@ -14,43 +14,8 @@ reg[31:0] sample_in;
reg sample_in_strobe;
reg [15:0] clk_count;
wire [31:0] sync_short_metric;
wire short_preamble_detected;
wire power_trigger;
wire [31:0] sync_long_out;
wire sync_long_out_strobe;
wire [31:0] sync_long_metric;
wire sync_long_metric_stb;
wire long_preamble_detected;
wire [31:0] equalizer_out;
wire equalizer_out_strobe;
wire [5:0] demod_out;
wire [5:0] demod_soft_bits;
wire [3:0] demod_soft_bits_pos;
wire demod_out_strobe;
wire [7:0] deinterleave_erase_out;
wire deinterleave_erase_out_strobe;
wire conv_decoder_out;
wire conv_decoder_out_stb;
wire descramble_out;
wire descramble_out_strobe;
wire [3:0] legacy_rate;
wire legacy_sig_rsvd;
wire [11:0] legacy_len;
wire legacy_sig_parity;
wire [5:0] legacy_sig_tail;
wire legacy_sig_stb;
reg signal_done;
wire [3:0] dot11_state;
wire pkt_header_valid;
wire pkt_header_valid_strobe;
wire [7:0] byte_out;
@ -74,6 +39,9 @@ wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
integer addr;
// file descriptors
integer sample_file_name_fd;
integer bb_sample_fd;
integer power_trigger_fd;
integer short_preamble_detected_fd;
@ -82,8 +50,6 @@ integer long_preamble_detected_fd;
integer sync_long_metric_fd;
integer sync_long_out_fd;
integer equalizer_out_fd;
integer demod_out_fd;
integer demod_soft_bits_fd;
integer demod_soft_bits_pos_fd;
@ -95,7 +61,36 @@ integer signal_fd;
integer byte_out_fd;
integer file_i, file_q, file_rssi_half_db, iq_sample_file;
// sync_short
integer mag_sq_fd;
integer mag_sq_avg_fd;
integer prod_fd;
integer prod_avg_fd;
integer phase_in_fd;
integer phase_out_fd;
integer delay_prod_avg_mag_fd;
// sync_long
integer sum_fd;
integer metric_fd;
integer phase_correction_fd;
integer next_phase_correction_fd;
integer fft_in_fd;
integer fft_out_fd;
// equalizer
integer new_lts_fd;
integer phase_offset_pilot_input_fd;
integer phase_offset_lts_input_fd;
integer phase_offset_pilot_fd;
integer phase_offset_pilot_sum_fd;
integer phase_offset_phase_out_fd;
integer rot_in_fd;
integer rot_out_fd;
integer equalizer_prod_fd;
integer equalizer_prod_scaled_fd;
integer equalizer_mag_sq_fd;
integer equalizer_out_fd;
// ONLY allow 100(low FPGA), 200(high FPGA), 240(ultra_scal FPGA) and 400(test)
// do NOT turn on more than one of them
@ -142,9 +137,15 @@ integer file_i, file_q, file_rssi_half_db, iq_sample_file;
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/openofdm_tx/PL_100Bytes/54Mbps.txt"
//`define NUM_SAMPLE 2048
integer file_i, file_q, file_rssi_half_db, iq_sample_file;
initial begin
$dumpfile("dot11.vcd");
$dumpvars;
sample_file_name_fd = $fopen("./sample_file_name.txt", "w");
$fwrite(sample_file_name_fd, "%s", `SAMPLE_FILE);
$fflush(sample_file_name_fd);
$fclose(sample_file_name_fd);
clock = 0;
reset = 1;
@ -178,8 +179,6 @@ always @(posedge clock) begin
long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
demod_out_fd = $fopen("./demod_out.txt", "w");
demod_soft_bits_fd = $fopen("./demod_soft_bits.txt", "w");
demod_soft_bits_pos_fd = $fopen("./demod_soft_bits_pos.txt", "w");
@ -190,6 +189,38 @@ always @(posedge clock) begin
signal_fd = $fopen("./signal_out.txt", "w");
byte_out_fd = $fopen("./byte_out.txt", "w");
// sync_short
mag_sq_fd = $fopen("./mag_sq.txt", "w");
mag_sq_avg_fd = $fopen("./mag_sq_avg.txt", "w");
prod_fd = $fopen("./prod.txt", "w");
prod_avg_fd = $fopen("./prod_avg.txt", "w");
phase_in_fd = $fopen("./phase_in.txt", "w");
phase_out_fd = $fopen("./phase_out.txt", "w");
delay_prod_avg_mag_fd = $fopen("./delay_prod_avg_mag.txt", "w");
// sync_long
sum_fd = $fopen("./sum.txt", "w");
metric_fd = $fopen("./metric.txt", "w");
phase_correction_fd = $fopen("./phase_correction.txt", "w");
next_phase_correction_fd = $fopen("./next_phase_correction.txt", "w");
fft_in_fd = $fopen("./fft_in.txt", "w");
fft_out_fd = $fopen("./fft_out.txt", "w");
// equalizer
new_lts_fd = $fopen("./new_lts.txt", "w");
phase_offset_pilot_input_fd = $fopen("./phase_offset_pilot_input.txt", "w");
phase_offset_lts_input_fd = $fopen("./phase_offset_lts_input.txt", "w");
phase_offset_pilot_fd = $fopen("./phase_offset_pilot.txt", "w");
phase_offset_pilot_sum_fd = $fopen("./phase_offset_pilot_sum.txt", "w");
phase_offset_phase_out_fd = $fopen("./phase_offset_phase_out.txt", "w");
rot_in_fd = $fopen("./rot_in.txt", "w");
rot_out_fd = $fopen("./rot_out.txt", "w");
equalizer_prod_fd = $fopen("./equalizer_prod.txt", "w");
equalizer_prod_scaled_fd = $fopen("./equalizer_prod_scaled.txt", "w");
equalizer_mag_sq_fd = $fopen("./equalizer_mag_sq.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
end
end
@ -235,16 +266,16 @@ always @(posedge clock) begin
clk_count <= clk_count + 1;
end
if (legacy_sig_stb) begin
if (dot11_inst.legacy_sig_stb) begin
end
//if (sample_in_strobe && power_trigger) begin
if (sample_in_strobe) begin
$fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0]));
$fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger);
$fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected);
$fwrite(power_trigger_fd, "%d %d\n", $time/2, dot11_inst.power_trigger);
$fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, dot11_inst.short_preamble_detected);
$fwrite(long_preamble_detected_fd, "%d %d\n", $time/2, long_preamble_detected);
$fwrite(long_preamble_detected_fd, "%d %d\n", $time/2, dot11_inst.long_preamble_detected);
$fflush(bb_sample_fd);
$fflush(power_trigger_fd);
@ -283,56 +314,154 @@ always @(posedge clock) begin
end
end
if (sync_long_metric_stb) begin
$fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric);
if (dot11_inst.sync_long_inst.metric_stb) begin
$fwrite(sync_long_metric_fd, "%d %d\n", $time/2, dot11_inst.sync_long_inst.metric);
$fflush(sync_long_metric_fd);
end
if (sync_long_out_strobe) begin
$fwrite(sync_long_out_fd, "%d %d\n", $signed(sync_long_out[31:16]), $signed(sync_long_out[15:0]));
if (dot11_inst.sync_long_inst.sample_out_strobe) begin
$fwrite(sync_long_out_fd, "%d %d\n", $signed(dot11_inst.sync_long_inst.sample_out[31:16]), $signed(dot11_inst.sync_long_inst.sample_out[15:0]));
$fflush(sync_long_out_fd);
end
if (equalizer_out_strobe) begin
$fwrite(equalizer_out_fd, "%d %d\n", $signed(equalizer_out[31:16]), $signed(equalizer_out[15:0]));
$fflush(equalizer_out_fd);
end
// if (dot11_inst.equalizer_inst.sample_out_strobe) begin
// $fwrite(equalizer_out_fd, "%d %d\n", $signed(dot11_inst.equalizer_inst.sample_out[31:16]), $signed(dot11_inst.equalizer_inst.sample_out[15:0]));
// $fflush(equalizer_out_fd);
// end
if (legacy_sig_stb) begin
if (dot11_inst.legacy_sig_stb) begin
signal_done <= 1;
$fwrite(signal_fd, "%04b %b %012b %b %06b", legacy_rate, legacy_sig_rsvd, legacy_len, legacy_sig_parity, legacy_sig_tail);
$fwrite(signal_fd, "%04b %b %012b %b %06b", dot11_inst.legacy_rate, dot11_inst.legacy_sig_rsvd, dot11_inst.legacy_len, dot11_inst.legacy_sig_parity, dot11_inst.legacy_sig_tail);
$fflush(signal_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && demod_out_strobe) begin
$fwrite(demod_out_fd, "%b %b %b %b %b %b\n",demod_out[0],demod_out[1],demod_out[2],demod_out[3],demod_out[4],demod_out[5]);
$fwrite(demod_soft_bits_fd, "%b %b %b %b %b %b\n",demod_soft_bits[0],demod_soft_bits[1],demod_soft_bits[2],demod_soft_bits[3],demod_soft_bits[4],demod_soft_bits[5]);
$fwrite(demod_soft_bits_pos_fd, "%b %b %b %b\n",demod_soft_bits_pos[0],demod_soft_bits_pos[1],demod_soft_bits_pos[2],demod_soft_bits_pos[3]);
if ((dot11_inst.state == S_MPDU_DELIM || dot11_inst.state == S_DECODE_DATA || dot11_inst.state == S_MPDU_PAD) && dot11_inst.ofdm_decoder_inst.demod_out_strobe) begin
$fwrite(demod_out_fd, "%b %b %b %b %b %b\n",dot11_inst.ofdm_decoder_inst.demod_out[0],dot11_inst.ofdm_decoder_inst.demod_out[1],dot11_inst.ofdm_decoder_inst.demod_out[2],dot11_inst.ofdm_decoder_inst.demod_out[3],dot11_inst.ofdm_decoder_inst.demod_out[4],dot11_inst.ofdm_decoder_inst.demod_out[5]);
$fwrite(demod_soft_bits_fd, "%b %b %b %b %b %b\n",dot11_inst.ofdm_decoder_inst.demod_soft_bits[0],dot11_inst.ofdm_decoder_inst.demod_soft_bits[1],dot11_inst.ofdm_decoder_inst.demod_soft_bits[2],dot11_inst.ofdm_decoder_inst.demod_soft_bits[3],dot11_inst.ofdm_decoder_inst.demod_soft_bits[4],dot11_inst.ofdm_decoder_inst.demod_soft_bits[5]);
$fwrite(demod_soft_bits_pos_fd, "%b %b %b %b\n",dot11_inst.ofdm_decoder_inst.demod_soft_bits_pos[0],dot11_inst.ofdm_decoder_inst.demod_soft_bits_pos[1],dot11_inst.ofdm_decoder_inst.demod_soft_bits_pos[2],dot11_inst.ofdm_decoder_inst.demod_soft_bits_pos[3]);
$fflush(demod_out_fd);
$fflush(demod_soft_bits_fd);
$fflush(demod_soft_bits_pos_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && deinterleave_erase_out_strobe) begin
$fwrite(deinterleave_erase_out_fd, "%b %b %b %b %b %b %b %b\n", deinterleave_erase_out[0], deinterleave_erase_out[1], deinterleave_erase_out[2], deinterleave_erase_out[3], deinterleave_erase_out[4], deinterleave_erase_out[5], deinterleave_erase_out[6], deinterleave_erase_out[7]);
if ((dot11_inst.state == S_MPDU_DELIM || dot11_inst.state == S_DECODE_DATA || dot11_inst.state == S_MPDU_PAD) && dot11_inst.deinterleave_erase_out_strobe) begin
$fwrite(deinterleave_erase_out_fd, "%b %b %b %b %b %b %b %b\n", dot11_inst.deinterleave_erase_out[0], dot11_inst.deinterleave_erase_out[1], dot11_inst.deinterleave_erase_out[2], dot11_inst.deinterleave_erase_out[3], dot11_inst.deinterleave_erase_out[4], dot11_inst.deinterleave_erase_out[5], dot11_inst.deinterleave_erase_out[6], dot11_inst.deinterleave_erase_out[7]);
$fflush(deinterleave_erase_out_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && conv_decoder_out_stb) begin
$fwrite(conv_out_fd, "%b\n", conv_decoder_out);
if ((dot11_inst.state == S_MPDU_DELIM || dot11_inst.state == S_DECODE_DATA || dot11_inst.state == S_MPDU_PAD) && dot11_inst.conv_decoder_out_stb) begin
$fwrite(conv_out_fd, "%b\n", dot11_inst.conv_decoder_out);
$fflush(conv_out_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && descramble_out_strobe) begin
$fwrite(descramble_out_fd, "%b\n", descramble_out);
if ((dot11_inst.state == S_MPDU_DELIM || dot11_inst.state == S_DECODE_DATA || dot11_inst.state == S_MPDU_PAD) && dot11_inst.descramble_out_strobe) begin
$fwrite(descramble_out_fd, "%b\n", dot11_inst.descramble_out);
$fflush(descramble_out_fd);
end
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && byte_out_strobe) begin
$fwrite(byte_out_fd, "%02x\n", byte_out);
if ((dot11_inst.state == S_MPDU_DELIM || dot11_inst.state == S_DECODE_DATA || dot11_inst.state == S_MPDU_PAD) && dot11_inst.byte_out_strobe) begin
$fwrite(byte_out_fd, "%02x\n", dot11_inst.byte_out);
$fflush(byte_out_fd);
end
// sync_short
if (dot11_inst.sync_short_inst.mag_sq_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(mag_sq_fd, "%d\n", dot11_inst.sync_short_inst.mag_sq);
$fflush(mag_sq_fd);
end
if (dot11_inst.sync_short_inst.mag_sq_avg_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(mag_sq_avg_fd, "%d\n", dot11_inst.sync_short_inst.mag_sq_avg);
$fflush(mag_sq_avg_fd);
end
if (dot11_inst.sync_short_inst.prod_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(prod_fd, "%d %d\n", dot11_inst.sync_short_inst.prod[63:32], dot11_inst.sync_short_inst.prod[31:0]);
$fflush(prod_fd);
end
if (dot11_inst.sync_short_inst.prod_avg_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(prod_avg_fd, "%d %d\n", dot11_inst.sync_short_inst.prod_avg[63:32], dot11_inst.sync_short_inst.prod_avg[31:0]);
$fflush(prod_avg_fd);
end
if (dot11_inst.sync_short_inst.phase_in_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(phase_in_fd, "%d %d\n", dot11_inst.sync_short_inst.phase_in_i, dot11_inst.sync_short_inst.phase_in_q);
$fflush(phase_in_fd);
end
if (dot11_inst.sync_short_inst.phase_out_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(phase_out_fd, "%d\n", $signed(dot11_inst.sync_short_inst.phase_out));
$fflush(phase_out_fd);
end
if (dot11_inst.sync_short_inst.delay_prod_avg_mag_stb && dot11_inst.sync_short_inst.enable && ~dot11_inst.sync_short_inst.reset) begin
$fwrite(delay_prod_avg_mag_fd, "%d\n", dot11_inst.sync_short_inst.delay_prod_avg_mag);
$fflush(delay_prod_avg_mag_fd);
end
// sync_long
if (dot11_inst.sync_long_inst.sum_stb && dot11_inst.sync_long_inst.enable && ~dot11_inst.sync_long_inst.reset) begin
$fwrite(sum_fd, "%d %d\n", dot11_inst.sync_long_inst.sum_i, dot11_inst.sync_long_inst.sum_q);
$fflush(sum_fd);
end
if (dot11_inst.sync_long_inst.metric_stb && dot11_inst.sync_long_inst.enable && ~dot11_inst.sync_long_inst.reset) begin
$fwrite(metric_fd, "%d\n", dot11_inst.sync_long_inst.metric);
$fflush(metric_fd);
end
if (dot11_inst.sync_long_inst.raw_stb && dot11_inst.sync_long_inst.enable && ~dot11_inst.sync_long_inst.reset) begin
$fwrite(phase_correction_fd, "%d\n", dot11_inst.sync_long_inst.phase_correction);
$fflush(phase_correction_fd);
$fwrite(next_phase_correction_fd, "%d\n", dot11_inst.sync_long_inst.next_phase_correction);
$fflush(next_phase_correction_fd);
end
if (dot11_inst.sync_long_inst.fft_in_stb && dot11_inst.sync_long_inst.enable && ~dot11_inst.sync_long_inst.reset) begin
$fwrite(fft_in_fd, "%d %d\n", dot11_inst.sync_long_inst.fft_in_re, dot11_inst.sync_long_inst.fft_in_im);
$fflush(fft_in_fd);
end
if (dot11_inst.sync_long_inst.fft_valid && dot11_inst.sync_long_inst.enable && ~dot11_inst.sync_long_inst.reset) begin
$fwrite(fft_out_fd, "%d %d\n", $signed(dot11_inst.sync_long_inst.fft_out_re[22:7]), $signed(dot11_inst.sync_long_inst.fft_out_im[22:7]));
$fflush(fft_out_fd);
end
// equalizer
if ((dot11_inst.equalizer_inst.num_ofdm_sym == 1 || (dot11_inst.equalizer_inst.pkt_ht==1 && dot11_inst.equalizer_inst.num_ofdm_sym==5)) && dot11_inst.equalizer_inst.state == dot11_inst.equalizer_inst.S_CALC_FREQ_OFFSET && dot11_inst.equalizer_inst.sample_in_strobe_dly == 1 && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
$fwrite(new_lts_fd, "%d %d\n", dot11_inst.equalizer_inst.lts_i_out, dot11_inst.equalizer_inst.lts_q_out);
$fflush(new_lts_fd);
end
if (dot11_inst.equalizer_inst.pilot_in_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
$fwrite(phase_offset_pilot_input_fd, "%d %d\n", dot11_inst.equalizer_inst.input_i, dot11_inst.equalizer_inst.input_q);
$fflush(phase_offset_pilot_input_fd);
$fwrite(phase_offset_lts_input_fd, "%d %d\n", dot11_inst.equalizer_inst.lts_i_out, dot11_inst.equalizer_inst.lts_q_out);
$fflush(phase_offset_lts_input_fd);
end
if (dot11_inst.equalizer_inst.pilot_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
$fwrite(phase_offset_pilot_fd, "%d %d\n", dot11_inst.equalizer_inst.pilot_i, dot11_inst.equalizer_inst.pilot_q);
$fflush(phase_offset_pilot_fd);
end
if (dot11_inst.equalizer_inst.phase_in_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
$fwrite(phase_offset_pilot_sum_fd, "%d %d\n", dot11_inst.equalizer_inst.pilot_sum_i, dot11_inst.equalizer_inst.pilot_sum_q);
$fflush(phase_offset_pilot_sum_fd);
end
if (dot11_inst.equalizer_inst.phase_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
$fwrite(phase_offset_phase_out_fd, "%d\n", $signed(dot11_inst.equalizer_inst.phase_out));
$fflush(phase_offset_phase_out_fd);
end
if (dot11_inst.equalizer_inst.rot_in_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
$fwrite(rot_in_fd, "%d %d %d\n", $signed(dot11_inst.equalizer_inst.buf_i_out), $signed(dot11_inst.equalizer_inst.buf_q_out), $signed(dot11_inst.equalizer_inst.sym_phase));
$fflush(rot_in_fd);
end
if (dot11_inst.equalizer_inst.rot_out_stb && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
$fwrite(rot_out_fd, "%d %d\n", dot11_inst.equalizer_inst.rot_i, dot11_inst.equalizer_inst.rot_q);
$fflush(rot_out_fd);
end
if (dot11_inst.equalizer_inst.prod_out_strobe && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
$fwrite(equalizer_prod_fd, "%d %d\n", $signed(dot11_inst.equalizer_inst.prod_i), $signed(dot11_inst.equalizer_inst.prod_q));
$fflush(equalizer_prod_fd);
$fwrite(equalizer_prod_scaled_fd, "%d %d\n", $signed(dot11_inst.equalizer_inst.prod_i_scaled), $signed(dot11_inst.equalizer_inst.prod_q_scaled));
$fflush(equalizer_prod_scaled_fd);
$fwrite(equalizer_mag_sq_fd, "%d\n", dot11_inst.equalizer_inst.mag_sq);
$fflush(equalizer_mag_sq_fd);
end
if (dot11_inst.equalizer_inst.sample_out_strobe && dot11_inst.equalizer_inst.enable && ~dot11_inst.equalizer_inst.reset) begin
$fwrite(equalizer_out_fd, "%d %d\n", $signed(dot11_inst.equalizer_inst.sample_out[31:16]), $signed(dot11_inst.equalizer_inst.sample_out[15:0]));
$fflush(equalizer_out_fd);
end
end
end
@ -374,50 +503,6 @@ dot11 dot11_inst (
.demod_is_ongoing(demod_is_ongoing),
.pkt_header_valid(pkt_header_valid),
.pkt_header_valid_strobe(pkt_header_valid_strobe),
.pkt_len(pkt_len),
.pkt_len_total(pkt_len_total),
.byte_out_strobe(byte_out_strobe),
.byte_out(byte_out),
.byte_count_total(byte_count_total),
.byte_count(byte_count),
.fcs_out_strobe(fcs_out_strobe),
.fcs_ok(fcs_ok),
.state(dot11_state),
.power_trigger(power_trigger),
.short_preamble_detected(short_preamble_detected),
.sync_long_metric(sync_long_metric),
.sync_long_metric_stb(sync_long_metric_stb),
.long_preamble_detected(long_preamble_detected),
.sync_long_out(sync_long_out),
.sync_long_out_strobe(sync_long_out_strobe),
.equalizer_out(equalizer_out),
.equalizer_out_strobe(equalizer_out_strobe),
.legacy_sig_stb(legacy_sig_stb),
.legacy_rate(legacy_rate),
.legacy_sig_rsvd(legacy_sig_rsvd),
.legacy_len(legacy_len),
.legacy_sig_parity(legacy_sig_parity),
.legacy_sig_tail(legacy_sig_tail),
.demod_out(demod_out),
.demod_soft_bits(demod_soft_bits),
.demod_soft_bits_pos(demod_soft_bits_pos),
.demod_out_strobe(demod_out_strobe),
.deinterleave_erase_out(deinterleave_erase_out),
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
.conv_decoder_out(conv_decoder_out),
.conv_decoder_out_stb(conv_decoder_out_stb),
.descramble_out(descramble_out),
.descramble_out_strobe(descramble_out_strobe)
);
/*

81
verilog/equalizer.v
View File

@ -199,87 +199,6 @@ reg sample_in_strobe_dly;
assign csi = {lts_i_out, lts_q_out};
assign csi_valid = ( (num_ofdm_sym == 1 || (pkt_ht==1 && num_ofdm_sym==5)) && state == S_CALC_FREQ_OFFSET && sample_in_strobe_dly == 1 && enable && (~reset) );
/*
// =============save signal to file for matlab bit-true comparison===========
integer file_open_trigger = 0;
integer new_lts_fd, phase_offset_pilot_input_fd, phase_offset_lts_input_fd, phase_offset_pilot_fd, phase_offset_pilot_sum_fd, phase_offset_phase_out_fd, rot_out_fd, equalizer_prod_fd, equalizer_prod_scaled_fd, equalizer_mag_sq_fd, equalizer_out_fd;
wire signed [15:0] norm_i_signed, norm_q_signed;
assign norm_i_signed = sample_out[31:16];
assign norm_q_signed = sample_out[15:0];
wire signed [31:0] prod_i_signed, prod_q_signed, prod_i_scaled_signed, prod_q_scaled_signed;
wire signed [15:0] phase_out_signed;
assign prod_i_signed = prod_i;
assign prod_q_signed = prod_q;
assign prod_i_scaled_signed = prod_i_scaled;
assign prod_q_scaled_signed = prod_q_scaled;
assign phase_out_signed = phase_out;
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
new_lts_fd = $fopen("./new_lts.txt", "w");
phase_offset_pilot_input_fd = $fopen("./phase_offset_pilot_input.txt", "w");
phase_offset_lts_input_fd = $fopen("./phase_offset_lts_input.txt", "w");
phase_offset_pilot_fd = $fopen("./phase_offset_pilot.txt", "w");
phase_offset_pilot_sum_fd = $fopen("./phase_offset_pilot_sum.txt", "w");
phase_offset_phase_out_fd = $fopen("./phase_offset_phase_out.txt", "w");
rot_out_fd = $fopen("./rot_out.txt", "w");
equalizer_prod_fd = $fopen("./equalizer_prod.txt", "w");
equalizer_prod_scaled_fd = $fopen("./equalizer_prod_scaled.txt", "w");
equalizer_mag_sq_fd = $fopen("./equalizer_mag_sq.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
end
if ((num_ofdm_sym == 1 || (pkt_ht==1 && num_ofdm_sym==5)) && state == S_CALC_FREQ_OFFSET && sample_in_strobe_dly == 1 && enable && (~reset) ) begin
$fwrite(new_lts_fd, "%d %d\n", lts_i_out, lts_q_out);
$fflush(new_lts_fd);
end
if (pilot_in_stb && enable && (~reset) ) begin
$fwrite(phase_offset_pilot_input_fd, "%d %d\n", input_i, input_q);
$fflush(phase_offset_pilot_input_fd);
$fwrite(phase_offset_lts_input_fd, "%d %d\n", lts_i_out, lts_q_out);
$fflush(phase_offset_lts_input_fd);
end
if (pilot_out_stb && enable && (~reset) ) begin
$fwrite(phase_offset_pilot_fd, "%d %d\n", pilot_i, pilot_q);
$fflush(phase_offset_pilot_fd);
end
if (phase_in_stb && enable && (~reset) ) begin
$fwrite(phase_offset_pilot_sum_fd, "%d %d\n", pilot_sum_i, pilot_sum_q);
$fflush(phase_offset_pilot_sum_fd);
end
if (phase_out_stb && enable && (~reset) ) begin
$fwrite(phase_offset_phase_out_fd, "%d\n", phase_out_signed);
$fflush(phase_offset_phase_out_fd);
end
if (rot_out_stb && enable && (~reset) ) begin
$fwrite(rot_out_fd, "%d %d\n", rot_i, rot_q);
$fflush(rot_out_fd);
end
if (prod_out_strobe && enable && (~reset) ) begin
$fwrite(equalizer_prod_fd, "%d %d\n", prod_i_signed, prod_q_signed);
$fflush(equalizer_prod_fd);
$fwrite(equalizer_prod_scaled_fd, "%d %d\n", prod_i_scaled_signed, prod_q_scaled_signed);
$fflush(equalizer_prod_scaled_fd);
$fwrite(equalizer_mag_sq_fd, "%d\n", mag_sq);
$fflush(equalizer_mag_sq_fd);
end
if (sample_out_strobe && enable && (~reset) ) begin
$fwrite(equalizer_out_fd, "%d %d\n", norm_i_signed, norm_q_signed);
$fflush(equalizer_out_fd);
end
end
// ==========end of save signal to file for matlab bit-true comparison===========
*/
ram_2port #(.DWIDTH(32), .AWIDTH(6)) lts_inst (
.clka(clock),

47
verilog/sync_long.v
View File

@ -55,53 +55,6 @@ reg signed [31:0] next_phase_correction;
reg reset_delay ; // add reset signal for fft, somehow all kinds of event flag raises when feeding real rf signal, maybe reset will help
wire fft_resetn ;
/*
// =============save signal to file for matlab bit-true comparison===========
integer file_open_trigger = 0;
integer sum_fd, metric_fd, phase_correction_fd, next_phase_correction_fd, fft_in_fd, fft_out_fd;
wire signed [15:0] fft_out_re_signed, fft_out_im_signed;
// wire signed [31:0] prod_i, prod_q, prod_avg_i, prod_avg_q, phase_in_i_signed, phase_in_q_signed, phase_out_signed;
// assign prod_i = prod[63:32];
assign fft_out_re_signed = fft_out_re[22:7];
assign fft_out_im_signed = fft_out_im[22:7];
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
sum_fd = $fopen("./sum.txt", "w");
metric_fd = $fopen("./metric.txt", "w");
phase_correction_fd = $fopen("./phase_correction.txt", "w");
next_phase_correction_fd = $fopen("./next_phase_correction.txt", "w");
fft_in_fd = $fopen("./fft_in.txt", "w");
fft_out_fd = $fopen("./fft_out.txt", "w");
end
if (sum_stb && enable && (~reset) ) begin
$fwrite(sum_fd, "%d %d\n", sum_i, sum_q);
$fflush(sum_fd);
end
if (metric_stb && enable && (~reset) ) begin
$fwrite(metric_fd, "%d\n", metric);
$fflush(metric_fd);
end
if (raw_stb && enable && (~reset) ) begin
$fwrite(phase_correction_fd, "%d\n", phase_correction);
$fflush(phase_correction_fd);
$fwrite(next_phase_correction_fd, "%d\n", next_phase_correction);
$fflush(next_phase_correction_fd);
end
if (fft_in_stb && enable && (~reset) ) begin
$fwrite(fft_in_fd, "%d %d\n", fft_in_re, fft_in_im);
$fflush(fft_in_fd);
end
if (fft_valid && enable && (~reset) ) begin
$fwrite(fft_out_fd, "%d %d\n", fft_out_re_signed, fft_out_im_signed);
$fflush(fft_out_fd);
end
end
// ==========end of save signal to file for matlab bit-true comparison===========
*/
always @(posedge clock) begin
reset_delay = reset ;
end

58
verilog/sync_short.v
View File

@ -78,64 +78,6 @@ reg has_neg;
.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(min_plateau), .changed());*/
/*
// =============save signal to file for matlab bit-true comparison===========
integer file_open_trigger = 0;
integer mag_sq_fd, mag_sq_avg_fd, prod_fd, prod_avg_fd, phase_in_fd, phase_out_fd, delay_prod_avg_mag_fd;
wire signed [31:0] prod_i, prod_q, prod_avg_i, prod_avg_q, phase_in_i_signed, phase_in_q_signed;
wire signed [15:0] phase_out_signed;
assign prod_i = prod[63:32];
assign prod_q = prod[31:0];
assign prod_avg_i = prod_avg[63:32];
assign prod_avg_q = prod_avg[31:0];
assign phase_in_i_signed = phase_in_i;
assign phase_in_q_signed = phase_in_q;
assign phase_out_signed = phase_out;
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
mag_sq_fd = $fopen("./mag_sq.txt", "w");
mag_sq_avg_fd = $fopen("./mag_sq_avg.txt", "w");
prod_fd = $fopen("./prod.txt", "w");
prod_avg_fd = $fopen("./prod_avg.txt", "w");
phase_in_fd = $fopen("./phase_in.txt", "w");
phase_out_fd = $fopen("./phase_out.txt", "w");
delay_prod_avg_mag_fd = $fopen("./delay_prod_avg_mag.txt", "w");
end
if (mag_sq_stb && enable && (~reset) ) begin
$fwrite(mag_sq_fd, "%d\n", mag_sq);
$fflush(mag_sq_fd);
end
if (mag_sq_avg_stb && enable && (~reset) ) begin
$fwrite(mag_sq_avg_fd, "%d\n", mag_sq_avg);
$fflush(mag_sq_avg_fd);
end
if (prod_stb && enable && (~reset) ) begin
$fwrite(prod_fd, "%d %d\n", prod_i, prod_q);
$fflush(prod_fd);
end
if (prod_avg_stb && enable && (~reset) ) begin
$fwrite(prod_avg_fd, "%d %d\n", prod_avg_i, prod_avg_q);
$fflush(prod_avg_fd);
end
if (phase_in_stb && enable && (~reset) ) begin
$fwrite(phase_in_fd, "%d %d\n", phase_in_i_signed, phase_in_q_signed);
$fflush(phase_in_fd);
end
if (phase_out_stb && enable && (~reset) ) begin
$fwrite(phase_out_fd, "%d\n", phase_out_signed);
$fflush(phase_out_fd);
end
if (delay_prod_avg_mag_stb && enable && (~reset) ) begin
$fwrite(delay_prod_avg_mag_fd, "%d\n", delay_prod_avg_mag);
$fflush(delay_prod_avg_mag_fd);
end
end
// ==========end of save signal to file for matlab bit-true comparison===========
*/
complex_to_mag_sq mag_sq_inst (
.clock(clock),
.enable(enable),