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make the code more testbench friendly

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This commit is contained in:
Xianjun Jiao 2020-09-02 21:59:37 +02:00
parent 2b3a043e8c
commit 539133f453
6 changed files with 230 additions and 28 deletions
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1
openofdm_rx.tcl
View File

@ -177,7 +177,6 @@ set files [list \
"[file normalize "$origin_dir/verilog/Xilinx/zynq/deinter_lut/deinter_lut.coe"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/atan_lut/atan_lut.coe"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/rot_lut/rot_lut.coe"]"\
"[file normalize "$origin_dir/../rx_intf/src/byte_to_word_fcs_sn_insert.v"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/viterbi/viterbi_v7_0.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynq/deinter_lut/deinter_lut.xci"]"\
"[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynq/src/div_gen_div_gen_0_0/div_gen_div_gen_0_0.xci"]"\

1
openofdm_rx_ultra_scale.tcl
View File

@ -177,7 +177,6 @@ set files [list \
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/deinter_lut/deinter_lut.coe"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/atan_lut/atan_lut.coe"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/rot_lut/rot_lut.coe"]"\
"[file normalize "$origin_dir/../rx_intf/src/byte_to_word_fcs_sn_insert.v"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/viterbi/viterbi_v7_0.xci"]"\
"[file normalize "$origin_dir/verilog/Xilinx/zynquplus/deinter_lut/deinter_lut.xci"]"\
"[file normalize "$origin_dir/verilog/coregen/div_gen_new_ip_core_zynquplus/src/div_gen_div_gen_0_0/div_gen_div_gen_0_0.xci"]"\

66
verilog/dot11_tb.v
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@ -55,8 +55,8 @@ wire [15:0] byte_count_total;
wire [15:0] byte_count;
wire [15:0] pkt_len_total;
wire [15:0] pkt_len;
wire [63:0] word_out;
wire word_out_strobe;
// wire [63:0] word_out;
// wire word_out_strobe;
reg set_stb;
reg [7:0] set_addr;
@ -92,6 +92,7 @@ integer file_i, file_q, file_rssi_half_db, iq_sample_file;
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_65mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi.txt"
//`define NUM_SAMPLE 4560
`define SAMPLE_FILE "../../../../../testing_inputs/simulated/openofdm_tx/PL_100Bytes/54Mbps.txt"
`define NUM_SAMPLE 2048
@ -115,33 +116,44 @@ initial begin
set_data = 0;
# 20 set_stb = 0;
iq_sample_file = $fopen(`SAMPLE_FILE, "r");
bb_sample_fd = $fopen("./sample_in.txt", "w");
power_trigger_fd = $fopen("./power_trigger.txt", "w");
short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w");
sync_long_metric_fd = $fopen("./sync_long_metric.txt", "w");
long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
demod_out_fd = $fopen("./demod_out.txt", "w");
deinterleave_erase_out_fd = $fopen("./deinterleave_erase_out.txt", "w");
conv_out_fd = $fopen("./conv_out.txt", "w");
descramble_out_fd = $fopen("./descramble_out.txt", "w");
signal_fd = $fopen("./signal_out.txt", "w");
byte_out_fd = $fopen("./byte_out.txt", "w");
end
integer file_open_trigger = 0;
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
iq_sample_file = $fopen(`SAMPLE_FILE, "r");
bb_sample_fd = $fopen("./sample_in.txt", "w");
power_trigger_fd = $fopen("./power_trigger.txt", "w");
short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w");
sync_long_metric_fd = $fopen("./sync_long_metric.txt", "w");
long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
demod_out_fd = $fopen("./demod_out.txt", "w");
deinterleave_erase_out_fd = $fopen("./deinterleave_erase_out.txt", "w");
conv_out_fd = $fopen("./conv_out.txt", "w");
descramble_out_fd = $fopen("./descramble_out.txt", "w");
signal_fd = $fopen("./signal_out.txt", "w");
byte_out_fd = $fopen("./byte_out.txt", "w");
end
end
always begin //100MHz
#5 clock = !clock;
end
/*
always begin //200MHz
#2.5 clock = !clock;
end
*/
always @(posedge clock) begin
if (reset) begin
@ -150,7 +162,8 @@ always @(posedge clock) begin
sample_in_strobe <= 0;
addr <= 0;
end else if (enable) begin
if (clk_count == 9) begin
if (clk_count == 4) begin // for 100M; 100/20 = 5
// if (clk_count == 9) begin // for 200M; 200/20 = 10
sample_in_strobe <= 1;
//$fscanf(iq_sample_file, "%d %d %d", file_i, file_q, file_rssi_half_db);
$fscanf(iq_sample_file, "%d %d", file_i, file_q);
@ -271,11 +284,11 @@ dot11 dot11_inst (
.power_thres(11'd0),
.min_plateau(32'd100),
.soft_decoding(1'b1),
.rssi_half_db(rssi_half_db),
.sample_in(sample_in),
.sample_in_strobe(sample_in_strobe),
.soft_decoding(1'b1),
.state(dot11_state),
@ -322,6 +335,7 @@ dot11 dot11_inst (
.legacy_sig_stb(legacy_sig_stb)
);
/*
byte_to_word_fcs_sn_insert byte_to_word_fcs_sn_insert_inst (
.clk(clock),
.rstn((~reset)&(~pkt_header_valid_strobe)),
@ -337,4 +351,6 @@ byte_to_word_fcs_sn_insert byte_to_word_fcs_sn_insert_inst (
.word_out(word_out),
.word_out_strobe(word_out_strobe)
);
*/
endmodule

87
verilog/equalizer.v
View File

@ -64,7 +64,7 @@ localparam IN_BUF_LEN_SHIFT = 6;
reg ht;
reg [5:0] num_data_carrier;
reg [7:0] num_ofdm_sym;
// bit masks
reg [63:0] lts_ref;
@ -168,6 +168,89 @@ wire lts_div_out_stb = div_out_stb;
reg prod_in_strobe;
wire prod_out_strobe;
/*
// =============save signal to file for matlab bit-true comparison===========
integer file_open_trigger = 0;
integer new_lts_fd, phase_offset_pilot_input_fd, phase_offset_lts_input_fd, phase_offset_pilot_fd, phase_offset_pilot_sum_fd, phase_offset_phase_out_fd, rot_out_fd, equalizer_prod_fd, equalizer_prod_scaled_fd, equalizer_mag_sq_fd, equalizer_out_fd;
reg sample_in_strobe_dly;
wire signed [15:0] norm_i_signed, norm_q_signed;
assign norm_i_signed = sample_out[31:16];
assign norm_q_signed = sample_out[15:0];
wire signed [31:0] prod_i_signed, prod_q_signed, prod_i_scaled_signed, prod_q_scaled_signed, phase_out_signed;
assign prod_i_signed = prod_i;
assign prod_q_signed = prod_q;
assign prod_i_scaled_signed = prod_i_scaled;
assign prod_q_scaled_signed = prod_q_scaled;
assign phase_out_signed = phase_out;
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
new_lts_fd = $fopen("./new_lts.txt", "w");
phase_offset_pilot_input_fd = $fopen("./phase_offset_pilot_input.txt", "w");
phase_offset_lts_input_fd = $fopen("./phase_offset_lts_input.txt", "w");
phase_offset_pilot_fd = $fopen("./phase_offset_pilot.txt", "w");
phase_offset_pilot_sum_fd = $fopen("./phase_offset_pilot_sum.txt", "w");
phase_offset_phase_out_fd = $fopen("./phase_offset_phase_out.txt", "w");
rot_out_fd = $fopen("./rot_out.txt", "w");
equalizer_prod_fd = $fopen("./equalizer_prod.txt", "w");
equalizer_prod_scaled_fd = $fopen("./equalizer_prod_scaled.txt", "w");
equalizer_mag_sq_fd = $fopen("./equalizer_mag_sq.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
end
sample_in_strobe_dly <= sample_in_strobe;
if (num_ofdm_sym == 1 && state == S_CALC_FREQ_OFFSET && sample_in_strobe_dly == 1 && enable && (~reset) ) begin
$fwrite(new_lts_fd, "%d %d\n", lts_i_out, lts_q_out);
$fflush(new_lts_fd);
end
if (pilot_in_stb && enable && (~reset) ) begin
$fwrite(phase_offset_pilot_input_fd, "%d %d\n", input_i, input_q);
$fflush(phase_offset_pilot_input_fd);
$fwrite(phase_offset_lts_input_fd, "%d %d\n", lts_i_out, lts_q_out);
$fflush(phase_offset_lts_input_fd);
end
if (pilot_out_stb && enable && (~reset) ) begin
$fwrite(phase_offset_pilot_fd, "%d %d\n", pilot_i, pilot_q);
$fflush(phase_offset_pilot_fd);
end
if (phase_in_stb && enable && (~reset) ) begin
$fwrite(phase_offset_pilot_sum_fd, "%d %d\n", pilot_sum_i, pilot_sum_q);
$fflush(phase_offset_pilot_sum_fd);
end
if (phase_out_stb && enable && (~reset) ) begin
$fwrite(phase_offset_phase_out_fd, "%d\n", phase_out_signed);
$fflush(phase_offset_phase_out_fd);
end
if (rot_out_stb && enable && (~reset) ) begin
$fwrite(rot_out_fd, "%d %d\n", rot_i, rot_q);
$fflush(rot_out_fd);
end
if (prod_out_strobe && enable && (~reset) ) begin
$fwrite(equalizer_prod_fd, "%d %d\n", prod_i_signed, prod_q_signed);
$fflush(equalizer_prod_fd);
$fwrite(equalizer_prod_scaled_fd, "%d %d\n", prod_i_scaled_signed, prod_q_scaled_signed);
$fflush(equalizer_prod_scaled_fd);
$fwrite(equalizer_mag_sq_fd, "%d\n", mag_sq);
$fflush(equalizer_mag_sq_fd);
end
if (sample_out_strobe && enable && (~reset) ) begin
$fwrite(equalizer_out_fd, "%d %d\n", norm_i_signed, norm_q_signed);
$fflush(equalizer_out_fd);
end
end
// ==========end of save signal to file for matlab bit-true comparison===========
*/
ram_2port #(.DWIDTH(32), .AWIDTH(6)) lts_inst (
.clka(clock),
.ena(1),
@ -330,6 +413,7 @@ always @(posedge clock) begin
ht <= 0;
num_data_carrier <= 48;
num_ofdm_sym <= 0;
subcarrier_mask <= SUBCARRIER_MASK;
data_subcarrier_mask <= DATA_SUBCARRIER_MASK;
@ -522,6 +606,7 @@ always @(posedge clock) begin
input_i <= 0;
input_q <= 0;
lts_raddr <= 0;
num_ofdm_sym <= num_ofdm_sym + 1;
state <= S_CALC_FREQ_OFFSET;
end

47
verilog/sync_long.v
View File

@ -54,6 +54,53 @@ reg signed [31:0] next_phase_correction;
reg reset_delay ; // add reset signal for fft, somehow all kinds of event flag raises when feeding real rf signal, maybe reset will help
wire fft_resetn ;
/*
// =============save signal to file for matlab bit-true comparison===========
integer file_open_trigger = 0;
integer sum_fd, metric_fd, phase_correction_fd, next_phase_correction_fd, fft_in_fd, fft_out_fd;
wire signed [15:0] fft_out_re_signed, fft_out_im_signed;
// wire signed [31:0] prod_i, prod_q, prod_avg_i, prod_avg_q, phase_in_i_signed, phase_in_q_signed, phase_out_signed;
// assign prod_i = prod[63:32];
assign fft_out_re_signed = fft_out_re[22:7];
assign fft_out_im_signed = fft_out_im[22:7];
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
sum_fd = $fopen("./sum.txt", "w");
metric_fd = $fopen("./metric.txt", "w");
phase_correction_fd = $fopen("./phase_correction.txt", "w");
next_phase_correction_fd = $fopen("./next_phase_correction.txt", "w");
fft_in_fd = $fopen("./fft_in.txt", "w");
fft_out_fd = $fopen("./fft_out.txt", "w");
end
if (sum_stb && enable && (~reset) ) begin
$fwrite(sum_fd, "%d %d\n", sum_i, sum_q);
$fflush(sum_fd);
end
if (metric_stb && enable && (~reset) ) begin
$fwrite(metric_fd, "%d\n", metric);
$fflush(metric_fd);
end
if (raw_stb && enable && (~reset) ) begin
$fwrite(phase_correction_fd, "%d\n", phase_correction);
$fflush(phase_correction_fd);
$fwrite(next_phase_correction_fd, "%d\n", next_phase_correction);
$fflush(next_phase_correction_fd);
end
if (fft_in_stb && enable && (~reset) ) begin
$fwrite(fft_in_fd, "%d %d\n", fft_in_re, fft_in_im);
$fflush(fft_in_fd);
end
if (fft_valid && enable && (~reset) ) begin
$fwrite(fft_out_fd, "%d %d\n", fft_out_re_signed, fft_out_im_signed);
$fflush(fft_out_fd);
end
end
// ==========end of save signal to file for matlab bit-true comparison===========
*/
always @(posedge clock) begin
reset_delay = reset ;
end

56
verilog/sync_short.v
View File

@ -77,6 +77,62 @@ reg has_neg;
.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(min_plateau), .changed());*/
/*
// =============save signal to file for matlab bit-true comparison===========
integer file_open_trigger = 0;
integer mag_sq_fd, mag_sq_avg_fd, prod_fd, prod_avg_fd, phase_in_fd, phase_out_fd, delay_prod_avg_mag_fd;
wire signed [31:0] prod_i, prod_q, prod_avg_i, prod_avg_q, phase_in_i_signed, phase_in_q_signed, phase_out_signed;
assign prod_i = prod[63:32];
assign prod_q = prod[31:0];
assign prod_avg_i = prod_avg[63:32];
assign prod_avg_q = prod_avg[31:0];
assign phase_in_i_signed = phase_in_i;
assign phase_in_q_signed = phase_in_q;
assign phase_out_signed = phase_out;
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
mag_sq_fd = $fopen("./mag_sq.txt", "w");
mag_sq_avg_fd = $fopen("./mag_sq_avg.txt", "w");
prod_fd = $fopen("./prod.txt", "w");
prod_avg_fd = $fopen("./prod_avg.txt", "w");
phase_in_fd = $fopen("./phase_in.txt", "w");
phase_out_fd = $fopen("./phase_out.txt", "w");
delay_prod_avg_mag_fd = $fopen("./delay_prod_avg_mag.txt", "w");
end
if (mag_sq_stb && enable && (~reset) ) begin
$fwrite(mag_sq_fd, "%d\n", mag_sq);
$fflush(mag_sq_fd);
end
if (mag_sq_avg_stb && enable && (~reset) ) begin
$fwrite(mag_sq_avg_fd, "%d\n", mag_sq_avg);
$fflush(mag_sq_avg_fd);
end
if (prod_stb && enable && (~reset) ) begin
$fwrite(prod_fd, "%d %d\n", prod_i, prod_q);
$fflush(prod_fd);
end
if (prod_avg_stb && enable && (~reset) ) begin
$fwrite(prod_avg_fd, "%d %d\n", prod_avg_i, prod_avg_q);
$fflush(prod_avg_fd);
end
if (phase_in_stb && enable && (~reset) ) begin
$fwrite(phase_in_fd, "%d %d\n", phase_in_i_signed, phase_in_q_signed);
$fflush(phase_in_fd);
end
if (phase_out_stb && enable && (~reset) ) begin
$fwrite(phase_out_fd, "%d\n", phase_out_signed);
$fflush(phase_out_fd);
end
if (delay_prod_avg_mag_stb && enable && (~reset) ) begin
$fwrite(delay_prod_avg_mag_fd, "%d\n", delay_prod_avg_mag);
$fflush(delay_prod_avg_mag_fd);
end
end
// ==========end of save signal to file for matlab bit-true comparison===========
*/
complex_to_mag_sq mag_sq_inst (
.clock(clock),