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Add slv_reg1[4] for option of disabling all smoothing
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@ -21,6 +21,7 @@ module dot11 (
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input sample_in_strobe,
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input soft_decoding,
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input wire force_ht_smoothing,
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input wire disable_all_smoothing,
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// OUTPUT: bytes and FCS status
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output reg demod_is_ongoing,
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@ -376,6 +377,7 @@ equalizer equalizer_inst (
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.ht_next(ht_next),
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.pkt_ht(pkt_ht),
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.ht_smoothing(ht_smoothing|force_ht_smoothing),
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.disable_all_smoothing(disable_all_smoothing),
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.phase_in_i(eq_phase_in_i),
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.phase_in_q(eq_phase_in_q),
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@ -11,6 +11,7 @@ module equalizer
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input ht_next,
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input pkt_ht,
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input ht_smoothing,
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input wire disable_all_smoothing,
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output [31:0] phase_in_i,
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output [31:0] phase_in_q,
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@ -548,8 +549,7 @@ always @(posedge clock) begin
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lts_raddr <= 62;
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lts_in_stb <= 0;
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lts_div_in_stb <= 0;
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// Always smooth legacy channel
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state <= S_SMOOTH_CH_DC;
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state <= (disable_all_smoothing?S_GET_POLARITY:S_SMOOTH_CH_DC);
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end else begin
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lts_waddr <= lts_waddr + 1;
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end
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@ -848,7 +848,7 @@ always @(posedge clock) begin
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lts_in_stb <= 0;
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lts_div_in_stb <= 0;
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// Depending on smoothing bit in HT-SIG, smooth the channel
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if(ht_smoothing) begin
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if(ht_smoothing==1 && disable_all_smoothing==0) begin
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state <= S_SMOOTH_CH_DC;
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end else begin
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state <= S_GET_POLARITY;
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@ -145,6 +145,7 @@
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.sample_in_strobe(sample_in_strobe),
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.soft_decoding(slv_reg4[0]),
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.force_ht_smoothing(slv_reg1[0]),
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.disable_all_smoothing(slv_reg1[4]),
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// OUTPUT: bytes and FCS status
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.demod_is_ongoing(demod_is_ongoing),
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