Add slv_reg1[4] for option of disabling all smoothing

This commit is contained in:
Xianjun Jiao 2022-03-29 12:50:31 +02:00
parent 39911461ef
commit 4168aa8c7a
3 changed files with 6 additions and 3 deletions

View File

@ -21,6 +21,7 @@ module dot11 (
input sample_in_strobe,
input soft_decoding,
input wire force_ht_smoothing,
input wire disable_all_smoothing,
// OUTPUT: bytes and FCS status
output reg demod_is_ongoing,
@ -376,6 +377,7 @@ equalizer equalizer_inst (
.ht_next(ht_next),
.pkt_ht(pkt_ht),
.ht_smoothing(ht_smoothing|force_ht_smoothing),
.disable_all_smoothing(disable_all_smoothing),
.phase_in_i(eq_phase_in_i),
.phase_in_q(eq_phase_in_q),

View File

@ -11,6 +11,7 @@ module equalizer
input ht_next,
input pkt_ht,
input ht_smoothing,
input wire disable_all_smoothing,
output [31:0] phase_in_i,
output [31:0] phase_in_q,
@ -548,8 +549,7 @@ always @(posedge clock) begin
lts_raddr <= 62;
lts_in_stb <= 0;
lts_div_in_stb <= 0;
// Always smooth legacy channel
state <= S_SMOOTH_CH_DC;
state <= (disable_all_smoothing?S_GET_POLARITY:S_SMOOTH_CH_DC);
end else begin
lts_waddr <= lts_waddr + 1;
end
@ -848,7 +848,7 @@ always @(posedge clock) begin
lts_in_stb <= 0;
lts_div_in_stb <= 0;
// Depending on smoothing bit in HT-SIG, smooth the channel
if(ht_smoothing) begin
if(ht_smoothing==1 && disable_all_smoothing==0) begin
state <= S_SMOOTH_CH_DC;
end else begin
state <= S_GET_POLARITY;

View File

@ -145,6 +145,7 @@
.sample_in_strobe(sample_in_strobe),
.soft_decoding(slv_reg4[0]),
.force_ht_smoothing(slv_reg1[0]),
.disable_all_smoothing(slv_reg1[4]),
// OUTPUT: bytes and FCS status
.demod_is_ongoing(demod_is_ongoing),