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Add signal_watchdog module to prevent fake demod in early phase:

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1. If strong DC or low frequency sing wave like signal (suspect it is generated by ad9361 during some self-calibration like operation), put the receiver into reset
2. If the signal/header is valid, but the packet length is abnormal (signal_len<14 || signal_len>max_signal_len_th), reset the receiver
This commit is contained in:
Xianjun Jiao 2022-03-15 16:03:40 +01:00
parent e77f1ba70b
commit f08c76ca3d
7 changed files with 1870 additions and 1538 deletions
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1549
openofdm_rx.tcl
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1543
openofdm_rx_ultra_scale.tcl
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27
verilog/dot11_tb.v
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@ -49,6 +49,7 @@ reg signal_done;
wire [3:0] dot11_state;
wire pkt_header_valid;
wire pkt_header_valid_strobe;
wire [7:0] byte_out;
wire byte_out_strobe;
@ -64,6 +65,10 @@ reg [7:0] set_addr;
reg [31:0] set_data;
wire fcs_out_strobe, fcs_ok;
wire demod_is_ongoing;
wire receiver_rst;
wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
integer addr;
@ -309,10 +314,28 @@ always @(posedge clock) begin
end
end
signal_watchdog signal_watchdog_inst (
.clk(clock),
.rstn(~reset),
.enable(~demod_is_ongoing),
.i_data(sample_in[31:16]),
.q_data(sample_in[15:0]),
.iq_valid(sample_in_strobe),
.signal_len(pkt_len),
.sig_valid(sig_valid),
.max_signal_len_th(137),
.dc_running_sum_th(62),
.receiver_rst(receiver_rst)
);
dot11 dot11_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.reset(reset|receiver_rst),
//.set_stb(set_stb),
//.set_addr(set_addr),
@ -326,6 +349,8 @@ dot11 dot11_inst (
.sample_in_strobe(sample_in_strobe),
.soft_decoding(1'b1),
.demod_is_ongoing(demod_is_ongoing),
.pkt_header_valid(pkt_header_valid),
.pkt_header_valid_strobe(pkt_header_valid_strobe),
.pkt_len(pkt_len),
.pkt_len_total(pkt_len_total),

25
verilog/openofdm_rx.v
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@ -108,12 +108,33 @@
assign slv_reg31 = `OPENOFDM_RX_GIT_REV;
wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
wire receiver_rst;
signal_watchdog signal_watchdog_inst (
.clk(s00_axi_aclk),
.rstn(s00_axi_aresetn),
.enable(~demod_is_ongoing),
.i_data(sample_in[31:16]),
.q_data(sample_in[15:0]),
.iq_valid(sample_in_strobe),
.signal_len(pkt_len),
.sig_valid(sig_valid),
.max_signal_len_th(slv_reg4[31:16]),
.dc_running_sum_th(slv_reg2[23:16]),
.receiver_rst(receiver_rst)
);
dot11 # (
) dot11_i (
.clock(s00_axi_aclk),
.enable( 1 ),
//.reset ( (~s00_axi_aresetn)|slv_reg0[0]|openofdm_core_rst ),
.reset ( (~s00_axi_aresetn)|slv_reg0[0] ),
.reset ( (~s00_axi_aresetn)|slv_reg0[0]|receiver_rst ),
.power_thres(slv_reg2[10:0]),
.min_plateau(slv_reg3),
@ -262,7 +283,7 @@
.SLV_REG17(slv_reg17),
.SLV_REG18(slv_reg18),
.SLV_REG19(slv_reg19),*/
.SLV_REG20(slv_reg20)/*
.SLV_REG20(slv_reg20),/*
.SLV_REG21(slv_reg21),
.SLV_REG22(slv_reg22),
.SLV_REG23(slv_reg23),

93
verilog/running_sum.v Normal file
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@ -0,0 +1,93 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
module running_sum
#(
parameter DATA_WIDTH = 16,
parameter LOG2_SUM_LEN = 6
)
(
input clk,
input rstn,
input signed [DATA_WIDTH-1:0] data_in,
input data_in_valid,
output reg signed [(DATA_WIDTH + LOG2_SUM_LEN-1):0] running_sum_result,
output reg data_out_valid
);
localparam FIFO_SIZE = 1<<LOG2_SUM_LEN;
localparam TOTAL_WIDTH = DATA_WIDTH + LOG2_SUM_LEN;
wire signed [DATA_WIDTH-1:0] data_in_old;
wire signed [TOTAL_WIDTH-1:0] ext_data_in_old = {{LOG2_SUM_LEN{data_in_old[DATA_WIDTH-1]}}, data_in_old};
wire signed [TOTAL_WIDTH-1:0] ext_data_in = {{LOG2_SUM_LEN{data_in[DATA_WIDTH-1]}}, data_in };
reg data_in_valid_reg;
reg rd_en, rd_en_start;
wire [LOG2_SUM_LEN:0] wr_data_count;
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"), // String
.ECC_MODE("no_ecc"), // String
.FIFO_MEMORY_TYPE("auto"), // String
.FIFO_READ_LATENCY(0), // DECIMAL
.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(10), // DECIMAL
.PROG_FULL_THRESH(10), // DECIMAL
.RD_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1), // DECIMAL
.READ_DATA_WIDTH(DATA_WIDTH), // DECIMAL
.READ_MODE("fwft"), // String
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
.WAKEUP_TIME(0), // DECIMAL
.WRITE_DATA_WIDTH(DATA_WIDTH), // DECIMAL
.WR_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1) // DECIMAL
) fifo_1clk_for_mv_avg_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout(data_in_old),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din(data_in),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(~rstn),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (~rstn) begin
data_in_valid_reg <= 0;
running_sum_result <= 0;
data_out_valid <= 0;
rd_en <= 0;
rd_en_start <= 0;
end else begin
data_in_valid_reg <= data_in_valid;
data_out_valid <= data_in_valid_reg;
rd_en_start <= ((wr_data_count == FIFO_SIZE)?1:rd_en_start);
rd_en <= (rd_en_start?data_in_valid:rd_en);
if (data_in_valid) begin
running_sum_result <= running_sum_result + ext_data_in - (rd_en_start?ext_data_in_old:0);
end
end
end
endmodule

103
verilog/running_sum_dual_ch.v Normal file
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@ -0,0 +1,103 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
module running_sum_dual_ch
#(
parameter DATA_WIDTH0 = 16,
parameter DATA_WIDTH1 = 16,
parameter LOG2_SUM_LEN = 6
)
(
input clk,
input rstn,
input signed [DATA_WIDTH0-1:0] data_in0,
input signed [DATA_WIDTH1-1:0] data_in1,
input data_in_valid,
output reg signed [(DATA_WIDTH0 + LOG2_SUM_LEN-1):0] running_sum_result0,
output reg signed [(DATA_WIDTH1 + LOG2_SUM_LEN-1):0] running_sum_result1,
output reg data_out_valid
);
localparam FIFO_SIZE = 1<<LOG2_SUM_LEN;
localparam TOTAL_WIDTH0 = DATA_WIDTH0 + LOG2_SUM_LEN;
localparam TOTAL_WIDTH1 = DATA_WIDTH1 + LOG2_SUM_LEN;
wire signed [DATA_WIDTH0-1:0] data_in_old0;
wire signed [DATA_WIDTH1-1:0] data_in_old1;
wire signed [TOTAL_WIDTH0-1:0] ext_data_in_old0 = {{LOG2_SUM_LEN{data_in_old0[DATA_WIDTH0-1]}}, data_in_old0};
wire signed [TOTAL_WIDTH0-1:0] ext_data_in0 = {{LOG2_SUM_LEN{data_in0[DATA_WIDTH0-1]}}, data_in0 };
wire signed [TOTAL_WIDTH1-1:0] ext_data_in_old1 = {{LOG2_SUM_LEN{data_in_old1[DATA_WIDTH1-1]}}, data_in_old1};
wire signed [TOTAL_WIDTH1-1:0] ext_data_in1 = {{LOG2_SUM_LEN{data_in1[DATA_WIDTH1-1]}}, data_in1 };
reg data_in_valid_reg;
reg rd_en, rd_en_start;
wire [LOG2_SUM_LEN:0] wr_data_count;
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"), // String
.ECC_MODE("no_ecc"), // String
.FIFO_MEMORY_TYPE("auto"), // String
.FIFO_READ_LATENCY(0), // DECIMAL
.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(10), // DECIMAL
.PROG_FULL_THRESH(10), // DECIMAL
.RD_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1), // DECIMAL
.READ_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL
.READ_MODE("fwft"), // String
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
.WAKEUP_TIME(0), // DECIMAL
.WRITE_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL
.WR_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1) // DECIMAL
) fifo_1clk_for_running_sum_dual_ch_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout({data_in_old1, data_in_old0}),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din({data_in1, data_in0}),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(~rstn),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (~rstn) begin
data_in_valid_reg <= 0;
running_sum_result0 <= 0;
running_sum_result1 <= 0;
data_out_valid <= 0;
rd_en <= 0;
rd_en_start <= 0;
end else begin
data_in_valid_reg <= data_in_valid;
data_out_valid <= data_in_valid_reg;
rd_en_start <= ((wr_data_count == FIFO_SIZE)?1:rd_en_start);
rd_en <= (rd_en_start?data_in_valid:rd_en);
if (data_in_valid) begin
running_sum_result0 <= running_sum_result0 + ext_data_in0 - (rd_en_start?ext_data_in_old0:0);
running_sum_result1 <= running_sum_result1 + ext_data_in1 - (rd_en_start?ext_data_in_old1:0);
end
end
end
endmodule

68
verilog/signal_watchdog.v Normal file
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@ -0,0 +1,68 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
module signal_watchdog
#(
parameter integer IQ_DATA_WIDTH = 16,
parameter LOG2_SUM_LEN = 6
)
(
input clk,
input rstn,
input enable,
input signed [(IQ_DATA_WIDTH-1):0] i_data,
input signed [(IQ_DATA_WIDTH-1):0] q_data,
input iq_valid,
input [15:0] signal_len,
input sig_valid,
input [15:0] max_signal_len_th,
input signed [(LOG2_SUM_LEN+2-1):0] dc_running_sum_th,
output receiver_rst
);
wire signed [1:0] i_sign;
wire signed [1:0] q_sign;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i_abs;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q_abs;
wire receiver_rst_internal;
reg receiver_rst_reg;
wire receiver_rst_pulse;
assign i_sign = (i_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
assign q_sign = (q_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
assign running_sum_result_i_abs = (running_sum_result_i[LOG2_SUM_LEN+2-1]?(-running_sum_result_i):running_sum_result_i);
assign running_sum_result_q_abs = (running_sum_result_q[LOG2_SUM_LEN+2-1]?(-running_sum_result_q):running_sum_result_q);
assign receiver_rst_internal = (enable&(running_sum_result_i_abs>=dc_running_sum_th || running_sum_result_q_abs>=dc_running_sum_th));
assign receiver_rst_pulse = (receiver_rst_internal&&(~receiver_rst_reg));
assign receiver_rst = ( receiver_rst_reg | (sig_valid && (signal_len<14 || signal_len>max_signal_len_th)) );
always @(posedge clk) begin
if (~rstn) begin
receiver_rst_reg <= 0;
end else begin
receiver_rst_reg <= receiver_rst_internal;
end
end
running_sum_dual_ch #(.DATA_WIDTH0(2), .DATA_WIDTH1(2), .LOG2_SUM_LEN(LOG2_SUM_LEN)) signal_watchdog_running_sum_inst (
.clk(clk),
.rstn(rstn),
.data_in0(i_sign),
.data_in1(q_sign),
.data_in_valid(iq_valid),
.running_sum_result0(running_sum_result_i),
.running_sum_result1(running_sum_result_q),
.data_out_valid()
);
endmodule