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Disable signal watch dog for normal simulation in the tb

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This commit is contained in:
Xianjun Jiao 2022-05-16 09:51:30 +02:00
parent 55f77bb16b
commit 7622d7aaa0
1 changed files with 2 additions and 2 deletions
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4
verilog/dot11_tb.v
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@ -477,8 +477,8 @@ signal_watchdog signal_watchdog_inst (
.signal_len(pkt_len),
.sig_valid(sig_valid),
.max_signal_len_th(4095),
.dc_running_sum_th(64),
.max_signal_len_th(16'hFFFF),
.dc_running_sum_th(65),
.receiver_rst(receiver_rst)
);