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Mono Color

• 257f2c2f59 Merge pull request #10 from redfast00/master Jinghao Shi 2020-08-27 00:36:39 -07:00
• b4fa037864 Correct typo redfast00 2020-08-26 00:56:51 +02:00
• 15aae0a205 Merge pull request #9 from open-sdr/dot11zynq Jinghao Shi 2020-06-18 01:02:00 -07:00
• 702b0c084f fix the simulation input file format of dot11_tb.v Xianjun Jiao 2020-06-17 16:06:49 +02:00
• 0dc741237c Merge pull request #8 from open-sdr/dot11zynq Jinghao Shi 2020-06-15 23:57:20 -07:00
• 6a0073ee58 remove debug Xianjun Jiao 2020-06-12 10:24:59 +02:00
• abbe9ecde9 extend support to zcu102/Zynq MPSoC ultra_scale Xianjun Jiao 2020-04-27 15:46:16 +02:00
• 03b2591cef revert to original index Jiao Xianjun 2020-04-17 17:10:23 +02:00
• 60677384b9 change the long preamble correlator first 4 sample indexes from 1 2 3 4 to 0 1 2 3 Xianjun Jiao 2020-03-28 21:18:33 +01:00
• f7a74ac848 Merge pull request #5 from open-sdr/dot11zynq Jinghao Shi 2019-12-15 22:47:18 +08:00
• 66aef6310f xjiao update: add soft decoding register switch mmehari 2019-12-10 13:48:38 +01:00
• 1f8bb83587 soft decoding support for BPSK, QPSK, 16-QAM and 64-QAM mmehari 2019-12-10 13:45:43 +01:00
• 2643844f2f necessary bug fixes and improvements for openwifi Xianjun Jiao 2019-12-10 13:31:16 +01:00
• 10ff8da3d7 port dot11 to zynq weiliu 2019-12-10 14:09:31 +01:00
• 2f0e0ba953 faq Jinghao Shi 2017-12-09 19:05:26 -05:00
• 549a7de059 readme Jinghao Shi 2017-04-26 14:49:53 -04:00
• 31d35e91e8 license Jinghao Shi 2017-04-26 14:47:59 -04:00
• ae5246395b doc url Jinghao Shi 2017-04-26 14:36:17 -04:00
• 126c1037f5 readme Jinghao Shi 2017-04-25 15:24:48 -04:00
• cceefb6c77 usrp Jinghao Shi 2017-04-25 15:19:32 -04:00
• 39b6115360 docs Jinghao Shi 2017-04-21 13:42:20 -04:00
• 079744bec1 fix dot11 port pinout Jinghao Shi 2017-04-21 13:42:09 -04:00
• b7361b2feb fix port pinout Jinghao Shi 2017-04-21 13:41:49 -04:00
• c0ad55abb6 remve unused variable in descramble.v Jinghao Shi 2017-04-21 13:41:28 -04:00
• 436aa53ea1 rewrite test.py Jinghao Shi 2017-04-21 13:41:03 -04:00
• 2315d0fc74 fix window size Jinghao Shi 2017-04-21 13:40:46 -04:00
• cc5effe283 ht-sig Jinghao Shi 2017-04-17 15:55:36 -04:00
• 25c5d67904 descrabmle Jinghao Shi 2017-04-17 12:53:44 -04:00
• 556794ae2e add coregen files Jinghao Shi 2017-04-14 16:29:33 -04:00
• a827623ab5 doc Jinghao Shi 2017-04-14 16:29:19 -04:00
• e5d4dc7cfc enlarge num_sample Jinghao Shi 2017-04-14 11:01:18 -04:00
• bcee4f66a1 fix packet detection Jinghao Shi 2017-04-14 11:01:05 -04:00
• 701cbb70c9 variable name Jinghao Shi 2017-04-14 11:00:46 -04:00
• 0b0723899a rotate Jinghao Shi 2017-04-14 11:00:33 -04:00
• 47577f7099 fix comment Jinghao Shi 2017-04-14 11:00:12 -04:00
• 191b197d5e fix polarity pattern Jinghao Shi 2017-04-14 11:00:01 -04:00
• 4f313f3ef9 doc Jinghao Shi 2017-04-14 10:59:40 -04:00
• 4e3c57c5f3 working on eq Jinghao Shi 2017-04-12 15:49:17 -04:00
• 297162af13 working Jinghao Shi 2017-04-07 16:51:06 -04:00
• c4c81b2766 fix lts index Jinghao Shi 2017-04-07 16:50:16 -04:00
• 20279b42a4 fix long preamble sample beginning index Jinghao Shi 2017-04-07 16:49:41 -04:00
• 652c8c1bb7 working on sync_long Jinghao Shi 2017-04-07 16:48:34 -04:00
• df46bc5309 phase lut Jinghao Shi 2017-04-07 11:37:11 -04:00
• 779b3651a4 remove unused verilog files Jinghao Shi 2017-04-07 11:36:51 -04:00
• 8375779a03 refactor name Jinghao Shi 2017-04-07 11:36:41 -04:00
• 4dd053ebf8 use delayT Jinghao Shi 2017-04-07 11:36:21 -04:00
• 28c57fc17f doc Jinghao Shi 2017-04-05 16:06:23 -04:00
• 63dd5a42f2 working Jinghao Shi 2017-04-03 15:48:37 -04:00
• cf42e1b7ae working Jinghao Shi 2017-04-03 15:48:25 -04:00
• 506472dec3 add sim_out dir Jinghao Shi 2017-04-03 15:25:48 -04:00
• 23e1c270e0 requirements.txt Jinghao Shi 2017-04-03 14:42:56 -04:00
• 8b4df2fcfe doc init Jinghao Shi 2017-04-03 14:42:37 -04:00
• 1ad9302fc3 readme Jinghao Shi 2017-04-03 14:31:25 -04:00
• d3ff9e7ce8 makefile Jinghao Shi 2017-04-03 14:05:07 -04:00
• bf4701fb39 makefile Jinghao Shi 2017-04-03 12:59:32 -04:00
• cf69020661 init Jinghao Shi 2017-04-03 12:52:37 -04:00
• 379f20e652 testing inputs init Jinghao Shi 2017-04-03 12:52:31 -04:00
• 20a33eb560 scripts init Jinghao Shi 2017-04-03 12:52:21 -04:00
• 9edf1899bd verilog init Jinghao Shi 2017-04-03 12:52:03 -04:00