fix comment

2024-12-19 05:38:10 +00:00 · 2017-04-14 11:00:12 -04:00 · 2017-04-14 11:00:12 -04:00 · 47577f7099
commit 47577f7099
parent 191b197d5e
1 changed files with 1 additions and 1 deletions
--- a/verilog/phase.v
+++ b/verilog/phase.v
@ -13,7 +13,7 @@ module phase
    input signed [DATA_WIDTH-1:0] in_q,
    input input_strobe,

-    // [-pi, pi) scaled up by 2048
+    // [-pi, pi) scaled up by 512
    output reg signed [31:0] phase,
    output output_strobe
 );