From 47577f7099037784d6c57ab37c45830978023ed5 Mon Sep 17 00:00:00 2001 From: Jinghao Shi Date: Fri, 14 Apr 2017 11:00:12 -0400 Subject: [PATCH] fix comment --- verilog/phase.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/phase.v b/verilog/phase.v index 701718f..5b2a9fb 100644 --- a/verilog/phase.v +++ b/verilog/phase.v @@ -13,7 +13,7 @@ module phase input signed [DATA_WIDTH-1:0] in_q, input input_strobe, - // [-pi, pi) scaled up by 2048 + // [-pi, pi) scaled up by 512 output reg signed [31:0] phase, output output_strobe );