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add sim_out dir

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This commit is contained in:
Jinghao Shi 2017-04-03 15:25:48 -04:00
parent 23e1c270e0
commit 506472dec3
1 changed files with 4 additions and 0 deletions
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verilog/sim_out/.gitignore vendored Normal file
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@ -0,0 +1,4 @@
# Ignore everything in this directory
*
# # Except this file
!.gitignore