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remove unused verilog files

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This commit is contained in:
Jinghao Shi 2017-04-07 11:36:51 -04:00
parent 8375779a03
commit 779b3651a4
3 changed files with 0 additions and 62 deletions
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21
verilog/atan_lut.v
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@ -1,21 +0,0 @@
`include "common_defs.v"
/*
* Output: atan(addr/1024.0)*2048
* Delay: 1 cycle
*/
module atan_lut (
input clka,
input [`ATAN_LUT_LEN_SHIFT-1:0] addra,
output reg [`ATAN_LUT_SCALE_SHIFT-1:0] douta
);
reg [`ATAN_LUT_SCALE_SHIFT-1:0] ram [0:(1<<`ATAN_LUT_LEN_SHIFT)-1];
initial begin
$readmemb("./atan_lut.mif", ram);
end
always @(posedge clka) begin
douta <= ram[addra];
end
endmodule

24
verilog/deinter_lut.v
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@ -1,24 +0,0 @@
module deinter_lut
#(
parameter DWIDTH = 22,
parameter AWIDTH = 11
)
(
input clka,
input [AWIDTH-1:0] addra,
output reg [DWIDTH-1:0] douta
);
reg [DWIDTH-1:0] ram [0:(1<<AWIDTH)-1];
initial begin
$readmemb("./deinter_lut.mif", ram);
end
always @(posedge clka) begin
if (ena) begin
douta <= ram[addra];
end
end
endmodule

17
verilog/rot_lut.v
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@ -1,17 +0,0 @@
`include "common_defs.v"
module rot_lut (
input clka,
input [`ROTATE_LUT_LEN_SHIFT-1:0] addra,
output reg [31:0] douta
);
reg [31:0] ram [0:(1<<`ROTATE_LUT_LEN_SHIFT)-1];
initial begin
$readmemb("./rot_lut.mif", ram);
end
always @(posedge clka) begin
douta <= ram[addra];
end
endmodule