From 779b3651a4f3523249cffec7309960a2963786bb Mon Sep 17 00:00:00 2001
From: Jinghao Shi <jinghaos@buffalo.edu>
Date: Fri, 7 Apr 2017 11:36:51 -0400
Subject: [PATCH] remove unused verilog files

---
 verilog/atan_lut.v    | 21 ---------------------
 verilog/deinter_lut.v | 24 ------------------------
 verilog/rot_lut.v     | 17 -----------------
 3 files changed, 62 deletions(-)
 delete mode 100644 verilog/atan_lut.v
 delete mode 100644 verilog/deinter_lut.v
 delete mode 100644 verilog/rot_lut.v

diff --git a/verilog/atan_lut.v b/verilog/atan_lut.v
deleted file mode 100644
index 899f884..0000000
--- a/verilog/atan_lut.v
+++ /dev/null
@@ -1,21 +0,0 @@
-`include "common_defs.v"
-
-/*
-* Output: atan(addr/1024.0)*2048
-* Delay: 1 cycle
-*/
-module atan_lut (
-    input clka,
-    input [`ATAN_LUT_LEN_SHIFT-1:0] addra,
-    output reg [`ATAN_LUT_SCALE_SHIFT-1:0] douta
-);
-
-reg [`ATAN_LUT_SCALE_SHIFT-1:0] ram [0:(1<<`ATAN_LUT_LEN_SHIFT)-1];
-initial begin
-    $readmemb("./atan_lut.mif", ram);
-end
-
-always @(posedge clka) begin
-    douta <= ram[addra];
-end
-endmodule
diff --git a/verilog/deinter_lut.v b/verilog/deinter_lut.v
deleted file mode 100644
index 7810a36..0000000
--- a/verilog/deinter_lut.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module deinter_lut
-#(
-    parameter DWIDTH = 22,
-    parameter AWIDTH = 11
-)
-(
-    input clka,
-    input [AWIDTH-1:0] addra,
-    output reg [DWIDTH-1:0] douta
-);
-
-reg [DWIDTH-1:0] ram [0:(1<<AWIDTH)-1];
-
-initial begin
-    $readmemb("./deinter_lut.mif", ram);
-end
-
-always @(posedge clka) begin
-    if (ena) begin
-        douta <= ram[addra];
-    end
-end
-
-endmodule
diff --git a/verilog/rot_lut.v b/verilog/rot_lut.v
deleted file mode 100644
index 42cf2fa..0000000
--- a/verilog/rot_lut.v
+++ /dev/null
@@ -1,17 +0,0 @@
-`include "common_defs.v"
-
-module rot_lut (
-    input clka,
-    input [`ROTATE_LUT_LEN_SHIFT-1:0] addra,
-    output reg [31:0] douta
-);
-
-reg [31:0] ram [0:(1<<`ROTATE_LUT_LEN_SHIFT)-1];
-initial begin
-    $readmemb("./rot_lut.mif", ram);
-end
-
-always @(posedge clka) begin
-    douta <= ram[addra];
-end
-endmodule