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22 lines
405 B
Verilog
22 lines
405 B
Verilog
`include "common_defs.v"
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/*
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* Output: atan(addr/1024.0)*2048
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* Delay: 1 cycle
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*/
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module atan_lut (
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input clka,
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input [`ATAN_LUT_LEN_SHIFT-1:0] addra,
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output reg [`ATAN_LUT_SCALE_SHIFT-1:0] douta
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);
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reg [`ATAN_LUT_SCALE_SHIFT-1:0] ram [0:(1<<`ATAN_LUT_LEN_SHIFT)-1];
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initial begin
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$readmemb("./atan_lut.mif", ram);
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end
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always @(posedge clka) begin
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douta <= ram[addra];
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end
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endmodule
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