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Jinghao Shi 2017-04-03 12:59:32 -04:00
parent cf69020661
commit bf4701fb39
1 changed files with 1 additions and 1 deletions
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verilog/Makefile
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@ -16,7 +16,7 @@ SRC = $(wildcard *.v) $(wildcard *.mif) $(wildcard *.coe)
MODULE_LIST = dot11_modules.list
TESTBENCH = dot11_tb.v
COMPILER_OUT = dot11.out #COMPILER OUTPUT
COMPILER_OUT = dot11.out
SIM_OUT = dot11.vcd
###############################################################################