From bf4701fb399c665b70fffcd2feb7ae961712d9cf Mon Sep 17 00:00:00 2001
From: Jinghao Shi <jinghaos@buffalo.edu>
Date: Mon, 3 Apr 2017 12:59:32 -0400
Subject: [PATCH] makefile

---
 verilog/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/verilog/Makefile b/verilog/Makefile
index 0dfd6ff..aae958b 100644
--- a/verilog/Makefile
+++ b/verilog/Makefile
@@ -16,7 +16,7 @@ SRC = $(wildcard *.v) $(wildcard *.mif) $(wildcard *.coe)
 MODULE_LIST = dot11_modules.list
 
 TESTBENCH = dot11_tb.v
-COMPILER_OUT = dot11.out			#COMPILER OUTPUT
+COMPILER_OUT = dot11.out
 SIM_OUT = dot11.vcd
 
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