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remve unused variable in descramble.v

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Jinghao Shi 2017-04-21 13:41:28 -04:00
parent 436aa53ea1
commit c0ad55abb6
1 changed files with 0 additions and 2 deletions
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verilog/descramble.v
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@ -14,7 +14,6 @@ module descramble
reg [6:0] state;
reg [4:0] bit_count;
reg [5:0] init_bits;
reg inited;
wire feedback = state[6] ^ state[3];
@ -23,7 +22,6 @@ always @(posedge clock) begin
if (reset) begin
bit_count <= 0;
state <= 0;
init_bits <= 0;
inited <= 0;
out_bit <= 0;
output_strobe <= 0;