ExternalVendorCode/openofdm
1
0
Fork 0
mirror of https://github.com/jhshi/openofdm.git synced 2025-04-20 00:31:01 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

readme

Browse Source
This commit is contained in:
Jinghao Shi 2017-04-26 14:49:53 -04:00
parent 31d35e91e8
commit 549a7de059
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Readme.rst
View File

@ -28,3 +28,9 @@ In a nutshell, the top level ``dot11`` Verilog module takes 32-bit I/Q samples
(16-bit each) as input, and output decoded bytes in 802.11 packet. The sampling
rate is 20 MSPS and the clock rate is 100 MHz. This means this module expects
one pair of I/Q sample every 5 clock ticks.
License
-------
`Apache License 2.0 <https://www.apache.org/licenses/LICENSE-2.0>`_