mirror of
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add coregen files
This commit is contained in:
Jinghao Shi
parent
a827623ab5
commit
556794ae2e
17
verilog/coregen/atan_lut.asy
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17
verilog/coregen/atan_lut.asy
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@ -0,0 +1,17 @@
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Version 4
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SymbolType BLOCK
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TEXT 32 32 LEFT 4 atan_lut
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RECTANGLE Normal 32 32 544 672
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LINE Wide 0 80 32 80
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PIN 0 80 LEFT 36
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PINATTR PinName addra[7:0]
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PINATTR Polarity IN
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LINE Normal 0 272 32 272
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PIN 0 272 LEFT 36
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PINATTR PinName clka
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PINATTR Polarity IN
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LINE Wide 576 80 544 80
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PIN 576 80 RIGHT 36
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PINATTR PinName douta[8:0]
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PINATTR Polarity OUT
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34
verilog/coregen/atan_lut.gise
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34
verilog/coregen/atan_lut.gise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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||||
<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="atan_lut.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema">
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<file xil_pn:fileType="FILE_ASY" xil_pn:name="atan_lut.asy" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="atan_lut.sym" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_VEO" xil_pn:name="atan_lut.veo" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_VHO" xil_pn:name="atan_lut.vho" xil_pn:origination="imported"/>
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<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
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</files>
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<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
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</generated_project>
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256
verilog/coregen/atan_lut.mif
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256
verilog/coregen/atan_lut.mif
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000000000
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000000010
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000000100
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000000110
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000001000
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000001010
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000001100
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000001110
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000010000
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000010100
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001000000
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100000000
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100000101
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100000110
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100001000
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100010101
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100010111
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100011011
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100011101
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100011110
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100100010
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100100100
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100100101
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100100111
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100101000
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100101001
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100101011
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100110010
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101001101
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101010001
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101010010
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101011101
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101110101
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101110111
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101111000
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101111011
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101111100
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101111101
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101111110
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101111111
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110000001
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110000010
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110000011
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110000100
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110000101
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110000110
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110000111
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110001000
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110001001
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110001010
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110001011
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110001100
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110001101
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110001110
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110001111
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110010000
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110010001
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0
verilog/coregen/atan_lut.ncf
Normal file
0
verilog/coregen/atan_lut.ncf
Normal file
3
verilog/coregen/atan_lut.ngc
Normal file
3
verilog/coregen/atan_lut.ngc
Normal file
File diff suppressed because one or more lines are too long
18
verilog/coregen/atan_lut.sym
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18
verilog/coregen/atan_lut.sym
Normal file
@ -0,0 +1,18 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<symbol version="7" name="atan_lut">
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<symboltype>BLOCK</symboltype>
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<timestamp>2016-11-8T19:48:42</timestamp>
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<pin polarity="Input" x="0" y="80" name="addra[7:0]" />
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<pin polarity="Input" x="0" y="272" name="clka" />
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<pin polarity="Output" x="576" y="80" name="douta[8:0]" />
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<graph>
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<text style="fontsize:40;fontname:Arial" x="32" y="32">atan_lut</text>
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<rect width="512" x="32" y="32" height="640" />
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<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
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<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[7:0]" />
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<line x2="32" y1="272" y2="272" x1="0" />
|
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<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
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<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
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<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[8:0]" />
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||||
</graph>
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||||
</symbol>
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45
verilog/coregen/atan_lut.veo
Normal file
45
verilog/coregen/atan_lut.veo
Normal file
@ -0,0 +1,45 @@
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||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used *
|
||||
* solely for design, simulation, implementation and creation of *
|
||||
* design files limited to Xilinx devices or technologies. Use *
|
||||
* with non-Xilinx devices or technologies is expressly prohibited *
|
||||
* and immediately terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
||||
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
||||
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
||||
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
||||
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
||||
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
||||
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
||||
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
||||
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
||||
* FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support *
|
||||
* appliances, devices, or systems. Use in such applications are *
|
||||
* expressly prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2009 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
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||||
// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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atan_lut YourInstanceName (
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.clka(clka),
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.addra(addra), // Bus [7 : 0]
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.douta(douta)); // Bus [8 : 0]
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||||
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||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file atan_lut.v when simulating
|
||||
// the core, atan_lut. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
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126
verilog/coregen/atan_lut.vhd
Normal file
126
verilog/coregen/atan_lut.vhd
Normal file
@ -0,0 +1,126 @@
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--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file atan_lut.vhd when simulating
|
||||
-- the core, atan_lut. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY atan_lut IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(7 downto 0);
|
||||
douta: OUT std_logic_VECTOR(8 downto 0));
|
||||
END atan_lut;
|
||||
|
||||
ARCHITECTURE atan_lut_a OF atan_lut IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_atan_lut
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(7 downto 0);
|
||||
douta: OUT std_logic_VECTOR(8 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_atan_lut use entity XilinxCoreLib.blk_mem_gen_v4_2(behavioral)
|
||||
generic map(
|
||||
c_has_regceb => 0,
|
||||
c_has_regcea => 0,
|
||||
c_mem_type => 3,
|
||||
c_rstram_b => 0,
|
||||
c_rstram_a => 0,
|
||||
c_has_injecterr => 0,
|
||||
c_rst_type => "SYNC",
|
||||
c_prim_type => 1,
|
||||
c_read_width_b => 9,
|
||||
c_initb_val => "0",
|
||||
c_family => "spartan3",
|
||||
c_read_width_a => 9,
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_use_softecc => 0,
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_init_file_name => "atan_lut.mif",
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_has_softecc_output_regs_b => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_load_init_file => 1,
|
||||
c_xdevicefamily => "spartan3adsp",
|
||||
c_write_depth_b => 256,
|
||||
c_write_depth_a => 256,
|
||||
c_has_rstb => 0,
|
||||
c_has_rsta => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_inita_val => "0",
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_addra_width => 8,
|
||||
c_has_softecc_input_regs_a => 0,
|
||||
c_addrb_width => 8,
|
||||
c_default_data => "0",
|
||||
c_use_ecc => 0,
|
||||
c_algorithm => 1,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_write_width_b => 9,
|
||||
c_write_width_a => 9,
|
||||
c_read_depth_b => 256,
|
||||
c_read_depth_a => 256,
|
||||
c_byte_size => 9,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_common_clk => 0,
|
||||
c_wea_width => 1,
|
||||
c_has_enb => 0,
|
||||
c_web_width => 1,
|
||||
c_has_ena => 0,
|
||||
c_use_byte_web => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_rst_priority_b => "CE",
|
||||
c_rst_priority_a => "CE",
|
||||
c_use_default_data => 0);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_atan_lut
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta);
|
||||
-- synthesis translate_on
|
||||
|
||||
END atan_lut_a;
|
||||
|
||||
60
verilog/coregen/atan_lut.vho
Normal file
60
verilog/coregen/atan_lut.vho
Normal file
@ -0,0 +1,60 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component atan_lut
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(7 downto 0);
|
||||
douta: OUT std_logic_VECTOR(8 downto 0));
|
||||
end component;
|
||||
|
||||
-- Synplicity black box declaration
|
||||
attribute syn_black_box : boolean;
|
||||
attribute syn_black_box of atan_lut: component is true;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : atan_lut
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file atan_lut.vhd when simulating
|
||||
-- the core, atan_lut. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
93
verilog/coregen/atan_lut.xco
Normal file
93
verilog/coregen/atan_lut.xco
Normal file
@ -0,0 +1,93 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 12.2
|
||||
# Date: Tue Nov 8 19:49:03 2016
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc3sd3400a
|
||||
SET devicefamily = spartan3adsp
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fg676
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -5
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator family Xilinx,_Inc. 4.2
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET additional_inputs_for_power_estimation=false
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=false
|
||||
CSET byte_size=9
|
||||
CSET coe_file=/home/jinghaos/projects/jammer/uhd/fpga-src/usrp2/custom/atan_lut.coe
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=atan_lut
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET ecctype=No_ECC
|
||||
CSET enable_a=Always_Enabled
|
||||
CSET enable_b=Always_Enabled
|
||||
CSET error_injection_type=Single_Bit_Error_Injection
|
||||
CSET fill_remaining_memory_locations=false
|
||||
CSET load_init_file=true
|
||||
CSET memory_type=Single_Port_ROM
|
||||
CSET operating_mode_a=WRITE_FIRST
|
||||
CSET operating_mode_b=WRITE_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET port_a_clock=100
|
||||
CSET port_a_enable_rate=100
|
||||
CSET port_a_write_rate=0
|
||||
CSET port_b_clock=0
|
||||
CSET port_b_enable_rate=0
|
||||
CSET port_b_write_rate=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=9
|
||||
CSET read_width_b=9
|
||||
CSET register_porta_input_of_softecc=false
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_softecc=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET reset_memory_latch_a=false
|
||||
CSET reset_memory_latch_b=false
|
||||
CSET reset_priority_a=CE
|
||||
CSET reset_priority_b=CE
|
||||
CSET reset_type=SYNC
|
||||
CSET softecc=false
|
||||
CSET use_byte_write_enable=false
|
||||
CSET use_error_injection_pins=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_rsta_pin=false
|
||||
CSET use_rstb_pin=false
|
||||
CSET write_depth_a=256
|
||||
CSET write_width_a=9
|
||||
CSET write_width_b=9
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 2731294b
|
||||
79
verilog/coregen/atan_lut.xise
Normal file
79
verilog/coregen/atan_lut.xise
Normal file
@ -0,0 +1,79 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="atan_lut.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="atan_lut.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="atan_lut.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3sd3400a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan-3A DSP" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|atan_lut|atan_lut_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="atan_lut.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/atan_lut" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fg676" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="atan_lut" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3adsp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-11-08T14:49:04" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="904347EB208A26A1448D47A682B002B7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
17
verilog/coregen/atan_lut_flist.txt
Normal file
17
verilog/coregen/atan_lut_flist.txt
Normal file
@ -0,0 +1,17 @@
|
||||
# Output products list for <atan_lut>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
atan_lut.asy
|
||||
atan_lut.gise
|
||||
atan_lut.mif
|
||||
atan_lut.ngc
|
||||
atan_lut.sym
|
||||
atan_lut.v
|
||||
atan_lut.veo
|
||||
atan_lut.vhd
|
||||
atan_lut.vho
|
||||
atan_lut.xco
|
||||
atan_lut.xise
|
||||
atan_lut_flist.txt
|
||||
atan_lut_xmdf.tcl
|
||||
blk_mem_gen_ds512.pdf
|
||||
blk_mem_gen_readme.txt
|
||||
92
verilog/coregen/atan_lut_xmdf.tcl
Normal file
92
verilog/coregen/atan_lut_xmdf.tcl
Normal file
@ -0,0 +1,92 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide atan_lut_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::atan_lut_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::atan_lut_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name atan_lut
|
||||
}
|
||||
# ::atan_lut_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::atan_lut_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path atan_lut.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path atan_lut.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path atan_lut.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path atan_lut.sym
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path atan_lut.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path atan_lut.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path atan_lut.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path atan_lut.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path atan_lut.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path atan_lut_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module atan_lut
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
33
verilog/coregen/complex_multiplier.asy
Normal file
33
verilog/coregen/complex_multiplier.asy
Normal file
@ -0,0 +1,33 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 complex_multiplier
|
||||
RECTANGLE Normal 32 32 544 640
|
||||
LINE Wide 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName ar[15:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 144 32 144
|
||||
PIN 0 144 LEFT 36
|
||||
PINATTR PinName ai[15:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 208 32 208
|
||||
PIN 0 208 LEFT 36
|
||||
PINATTR PinName br[15:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName bi[15:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 432 32 432
|
||||
PIN 0 432 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 80 544 80
|
||||
PIN 576 80 RIGHT 36
|
||||
PINATTR PinName pr[31:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 144 544 144
|
||||
PIN 576 144 RIGHT 36
|
||||
PINATTR PinName pi[31:0]
|
||||
PINATTR Polarity OUT
|
||||
|
||||
33
verilog/coregen/complex_multiplier.gise
Normal file
33
verilog/coregen/complex_multiplier.gise
Normal file
@ -0,0 +1,33 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="complex_multiplier.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="complex_multiplier.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="complex_multiplier.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="complex_multiplier.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="complex_multiplier.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
0
verilog/coregen/complex_multiplier.ncf
Normal file
0
verilog/coregen/complex_multiplier.ncf
Normal file
3
verilog/coregen/complex_multiplier.ngc
Normal file
3
verilog/coregen/complex_multiplier.ngc
Normal file
File diff suppressed because one or more lines are too long
30
verilog/coregen/complex_multiplier.sym
Normal file
30
verilog/coregen/complex_multiplier.sym
Normal file
@ -0,0 +1,30 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="complex_multiplier">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2016-8-23T18:22:59</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="ar[15:0]" />
|
||||
<pin polarity="Input" x="0" y="144" name="ai[15:0]" />
|
||||
<pin polarity="Input" x="0" y="208" name="br[15:0]" />
|
||||
<pin polarity="Input" x="0" y="272" name="bi[15:0]" />
|
||||
<pin polarity="Input" x="0" y="432" name="clk" />
|
||||
<pin polarity="Output" x="576" y="80" name="pr[31:0]" />
|
||||
<pin polarity="Output" x="576" y="144" name="pi[31:0]" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">complex_multiplier</text>
|
||||
<rect width="512" x="32" y="32" height="608" />
|
||||
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin ar[15:0]" />
|
||||
<line x2="32" y1="144" y2="144" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ai[15:0]" />
|
||||
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin br[15:0]" />
|
||||
<line x2="32" y1="272" y2="272" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin bi[15:0]" />
|
||||
<line x2="32" y1="432" y2="432" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin clk" />
|
||||
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin pr[31:0]" />
|
||||
<line x2="544" y1="144" y2="144" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="144" type="pin pi[31:0]" />
|
||||
</graph>
|
||||
</symbol>
|
||||
49
verilog/coregen/complex_multiplier.veo
Normal file
49
verilog/coregen/complex_multiplier.veo
Normal file
@ -0,0 +1,49 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used *
|
||||
* solely for design, simulation, implementation and creation of *
|
||||
* design files limited to Xilinx devices or technologies. Use *
|
||||
* with non-Xilinx devices or technologies is expressly prohibited *
|
||||
* and immediately terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
||||
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
||||
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
||||
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
||||
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
||||
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
||||
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
||||
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
||||
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
||||
* FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support *
|
||||
* appliances, devices, or systems. Use in such applications are *
|
||||
* expressly prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2009 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
complex_multiplier YourInstanceName (
|
||||
.ar(ar), // Bus [15 : 0]
|
||||
.ai(ai), // Bus [15 : 0]
|
||||
.br(br), // Bus [15 : 0]
|
||||
.bi(bi), // Bus [15 : 0]
|
||||
.clk(clk),
|
||||
.pr(pr), // Bus [31 : 0]
|
||||
.pi(pi)); // Bus [31 : 0]
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file complex_multiplier.v when simulating
|
||||
// the core, complex_multiplier. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
102
verilog/coregen/complex_multiplier.vhd
Normal file
102
verilog/coregen/complex_multiplier.vhd
Normal file
@ -0,0 +1,102 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file complex_multiplier.vhd when simulating
|
||||
-- the core, complex_multiplier. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY complex_multiplier IS
|
||||
port (
|
||||
ar: IN std_logic_VECTOR(15 downto 0);
|
||||
ai: IN std_logic_VECTOR(15 downto 0);
|
||||
br: IN std_logic_VECTOR(15 downto 0);
|
||||
bi: IN std_logic_VECTOR(15 downto 0);
|
||||
clk: IN std_logic;
|
||||
pr: OUT std_logic_VECTOR(31 downto 0);
|
||||
pi: OUT std_logic_VECTOR(31 downto 0));
|
||||
END complex_multiplier;
|
||||
|
||||
ARCHITECTURE complex_multiplier_a OF complex_multiplier IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_complex_multiplier
|
||||
port (
|
||||
ar: IN std_logic_VECTOR(15 downto 0);
|
||||
ai: IN std_logic_VECTOR(15 downto 0);
|
||||
br: IN std_logic_VECTOR(15 downto 0);
|
||||
bi: IN std_logic_VECTOR(15 downto 0);
|
||||
clk: IN std_logic;
|
||||
pr: OUT std_logic_VECTOR(31 downto 0);
|
||||
pi: OUT std_logic_VECTOR(31 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_complex_multiplier use entity XilinxCoreLib.cmpy_v3_1(behavioral)
|
||||
generic map(
|
||||
c_a_width => 16,
|
||||
c_ce_overrides_sclr => 0,
|
||||
has_negate => 0,
|
||||
c_has_sclr => 0,
|
||||
c_out_high => 31,
|
||||
c_verbosity => 0,
|
||||
c_mult_type => 1,
|
||||
c_latency => 3,
|
||||
c_xdevice => "xc3sd3400a",
|
||||
c_has_ce => 0,
|
||||
single_output => 0,
|
||||
round => 0,
|
||||
use_dsp_cascades => 1,
|
||||
c_optimize_goal => 0,
|
||||
c_xdevicefamily => "spartan3adsp",
|
||||
c_out_low => 0,
|
||||
c_b_width => 16);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_complex_multiplier
|
||||
port map (
|
||||
ar => ar,
|
||||
ai => ai,
|
||||
br => br,
|
||||
bi => bi,
|
||||
clk => clk,
|
||||
pr => pr,
|
||||
pi => pi);
|
||||
-- synthesis translate_on
|
||||
|
||||
END complex_multiplier_a;
|
||||
|
||||
68
verilog/coregen/complex_multiplier.vho
Normal file
68
verilog/coregen/complex_multiplier.vho
Normal file
@ -0,0 +1,68 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component complex_multiplier
|
||||
port (
|
||||
ar: IN std_logic_VECTOR(15 downto 0);
|
||||
ai: IN std_logic_VECTOR(15 downto 0);
|
||||
br: IN std_logic_VECTOR(15 downto 0);
|
||||
bi: IN std_logic_VECTOR(15 downto 0);
|
||||
clk: IN std_logic;
|
||||
pr: OUT std_logic_VECTOR(31 downto 0);
|
||||
pi: OUT std_logic_VECTOR(31 downto 0));
|
||||
end component;
|
||||
|
||||
-- Synplicity black box declaration
|
||||
attribute syn_black_box : boolean;
|
||||
attribute syn_black_box of complex_multiplier: component is true;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : complex_multiplier
|
||||
port map (
|
||||
ar => ar,
|
||||
ai => ai,
|
||||
br => br,
|
||||
bi => bi,
|
||||
clk => clk,
|
||||
pr => pr,
|
||||
pi => pi);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file complex_multiplier.vhd when simulating
|
||||
-- the core, complex_multiplier. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
52
verilog/coregen/complex_multiplier.xco
Normal file
52
verilog/coregen/complex_multiplier.xco
Normal file
@ -0,0 +1,52 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 12.2
|
||||
# Date: Tue Aug 23 18:23:22 2016
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc3sd3400a
|
||||
SET devicefamily = spartan3adsp
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fg676
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -5
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Complex_Multiplier family Xilinx,_Inc. 3.1
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET aportwidth=16
|
||||
CSET bportwidth=16
|
||||
CSET clockenable=false
|
||||
CSET component_name=complex_multiplier
|
||||
CSET latency=3
|
||||
CSET multtype=Use_Mults
|
||||
CSET optimizegoal=Resources
|
||||
CSET outputwidthhigh=31
|
||||
CSET outputwidthlow=0
|
||||
CSET roundmode=Truncate
|
||||
CSET sclrcepriority=SCLR_overrides_CE
|
||||
CSET syncclear=false
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 50371edc
|
||||
79
verilog/coregen/complex_multiplier.xise
Normal file
79
verilog/coregen/complex_multiplier.xise
Normal file
@ -0,0 +1,79 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="complex_multiplier.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="complex_multiplier.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="complex_multiplier.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3sd3400a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan-3A DSP" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|complex_multiplier|complex_multiplier_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="complex_multiplier.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/complex_multiplier" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fg676" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="complex_multiplier" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3adsp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-08-23T11:23:23" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1F49E394F5C62409BDE46EB42BCB2DB9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
15
verilog/coregen/complex_multiplier_flist.txt
Normal file
15
verilog/coregen/complex_multiplier_flist.txt
Normal file
@ -0,0 +1,15 @@
|
||||
# Output products list for <complex_multiplier>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
complex_multiplier.asy
|
||||
complex_multiplier.gise
|
||||
complex_multiplier.ngc
|
||||
complex_multiplier.sym
|
||||
complex_multiplier.v
|
||||
complex_multiplier.veo
|
||||
complex_multiplier.vhd
|
||||
complex_multiplier.vho
|
||||
complex_multiplier.xco
|
||||
complex_multiplier.xise
|
||||
complex_multiplier_flist.txt
|
||||
complex_multiplier_readme.txt
|
||||
complex_multiplier_xmdf.tcl
|
||||
60
verilog/coregen/complex_multiplier_readme.txt
Normal file
60
verilog/coregen/complex_multiplier_readme.txt
Normal file
@ -0,0 +1,60 @@
|
||||
The following files were generated for 'complex_multiplier' in directory
|
||||
/home/jinghaos/projects/jammer/uhd/fpga-src/usrp2/top/N2x0/build-N210R4-custom/ipcore_dir/
|
||||
|
||||
complex_multiplier.asy:
|
||||
Graphical symbol information file. Used by the ISE tools and some
|
||||
third party tools to create a symbol representing the core.
|
||||
|
||||
complex_multiplier.gise:
|
||||
ISE Project Navigator support file. This is a generated file and should
|
||||
not be edited directly.
|
||||
|
||||
complex_multiplier.ngc:
|
||||
Binary Xilinx implementation netlist file containing the information
|
||||
required to implement the module in a Xilinx (R) FPGA.
|
||||
|
||||
complex_multiplier.sym:
|
||||
Please see the core data sheet.
|
||||
|
||||
complex_multiplier.v:
|
||||
Verilog wrapper file provided to support functional simulation.
|
||||
This file contains simulation model customization data that is
|
||||
passed to a parameterized simulation model for the core.
|
||||
|
||||
complex_multiplier.veo:
|
||||
VEO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a Verilog design.
|
||||
|
||||
complex_multiplier.vhd:
|
||||
VHDL wrapper file provided to support functional simulation. This
|
||||
file contains simulation model customization data that is passed to
|
||||
a parameterized simulation model for the core.
|
||||
|
||||
complex_multiplier.vho:
|
||||
VHO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a VHDL design.
|
||||
|
||||
complex_multiplier.xco:
|
||||
CORE Generator input file containing the parameters used to
|
||||
regenerate a core.
|
||||
|
||||
complex_multiplier.xise:
|
||||
ISE Project Navigator support file. This is a generated file and should
|
||||
not be edited directly.
|
||||
|
||||
complex_multiplier_readme.txt:
|
||||
Text file indicating the files generated and how they are used.
|
||||
|
||||
complex_multiplier_xmdf.tcl:
|
||||
ISE Project Navigator interface file. ISE uses this file to determine
|
||||
how the files output by CORE Generator for the core can be integrated
|
||||
into your ISE project.
|
||||
|
||||
complex_multiplier_flist.txt:
|
||||
Text file listing all of the output files produced when a customized
|
||||
core was generated in the CORE Generator.
|
||||
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
80
verilog/coregen/complex_multiplier_xmdf.tcl
Normal file
80
verilog/coregen/complex_multiplier_xmdf.tcl
Normal file
@ -0,0 +1,80 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide complex_multiplier_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::complex_multiplier_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::complex_multiplier_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name complex_multiplier
|
||||
}
|
||||
# ::complex_multiplier_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::complex_multiplier_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path complex_multiplier.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path complex_multiplier.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path complex_multiplier.sym
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path complex_multiplier.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path complex_multiplier.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path complex_multiplier.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path complex_multiplier.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path complex_multiplier.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path complex_multiplier_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module complex_multiplier
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
17
verilog/coregen/deinter_lut.asy
Normal file
17
verilog/coregen/deinter_lut.asy
Normal file
@ -0,0 +1,17 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 deinter_lut
|
||||
RECTANGLE Normal 32 32 544 672
|
||||
LINE Wide 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName addra[10:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName clka
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 80 544 80
|
||||
PIN 576 80 RIGHT 36
|
||||
PINATTR PinName douta[21:0]
|
||||
PINATTR Polarity OUT
|
||||
|
||||
34
verilog/coregen/deinter_lut.gise
Normal file
34
verilog/coregen/deinter_lut.gise
Normal file
@ -0,0 +1,34 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="deinter_lut.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="deinter_lut.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="deinter_lut.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="deinter_lut.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="deinter_lut.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
2048
verilog/coregen/deinter_lut.mif
Normal file
2048
verilog/coregen/deinter_lut.mif
Normal file
File diff suppressed because it is too large
Load Diff
0
verilog/coregen/deinter_lut.ncf
Normal file
0
verilog/coregen/deinter_lut.ncf
Normal file
3
verilog/coregen/deinter_lut.ngc
Normal file
3
verilog/coregen/deinter_lut.ngc
Normal file
File diff suppressed because one or more lines are too long
18
verilog/coregen/deinter_lut.sym
Normal file
18
verilog/coregen/deinter_lut.sym
Normal file
@ -0,0 +1,18 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="deinter_lut">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2016-11-7T16:53:49</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="addra[10:0]" />
|
||||
<pin polarity="Input" x="0" y="272" name="clka" />
|
||||
<pin polarity="Output" x="576" y="80" name="douta[21:0]" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">deinter_lut</text>
|
||||
<rect width="512" x="32" y="32" height="640" />
|
||||
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[10:0]" />
|
||||
<line x2="32" y1="272" y2="272" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
|
||||
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[21:0]" />
|
||||
</graph>
|
||||
</symbol>
|
||||
45
verilog/coregen/deinter_lut.veo
Normal file
45
verilog/coregen/deinter_lut.veo
Normal file
@ -0,0 +1,45 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used *
|
||||
* solely for design, simulation, implementation and creation of *
|
||||
* design files limited to Xilinx devices or technologies. Use *
|
||||
* with non-Xilinx devices or technologies is expressly prohibited *
|
||||
* and immediately terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
||||
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
||||
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
||||
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
||||
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
||||
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
||||
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
||||
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
||||
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
||||
* FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support *
|
||||
* appliances, devices, or systems. Use in such applications are *
|
||||
* expressly prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2009 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
deinter_lut YourInstanceName (
|
||||
.clka(clka),
|
||||
.addra(addra), // Bus [10 : 0]
|
||||
.douta(douta)); // Bus [21 : 0]
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file deinter_lut.v when simulating
|
||||
// the core, deinter_lut. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
126
verilog/coregen/deinter_lut.vhd
Normal file
126
verilog/coregen/deinter_lut.vhd
Normal file
@ -0,0 +1,126 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file deinter_lut.vhd when simulating
|
||||
-- the core, deinter_lut. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY deinter_lut IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(21 downto 0));
|
||||
END deinter_lut;
|
||||
|
||||
ARCHITECTURE deinter_lut_a OF deinter_lut IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_deinter_lut
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(21 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_deinter_lut use entity XilinxCoreLib.blk_mem_gen_v4_2(behavioral)
|
||||
generic map(
|
||||
c_has_regceb => 0,
|
||||
c_has_regcea => 0,
|
||||
c_mem_type => 3,
|
||||
c_rstram_b => 0,
|
||||
c_rstram_a => 0,
|
||||
c_has_injecterr => 0,
|
||||
c_rst_type => "SYNC",
|
||||
c_prim_type => 1,
|
||||
c_read_width_b => 22,
|
||||
c_initb_val => "0",
|
||||
c_family => "spartan3",
|
||||
c_read_width_a => 22,
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_use_softecc => 0,
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_init_file_name => "deinter_lut.mif",
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_has_softecc_output_regs_b => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_load_init_file => 1,
|
||||
c_xdevicefamily => "spartan3adsp",
|
||||
c_write_depth_b => 2048,
|
||||
c_write_depth_a => 2048,
|
||||
c_has_rstb => 0,
|
||||
c_has_rsta => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_inita_val => "0",
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_addra_width => 11,
|
||||
c_has_softecc_input_regs_a => 0,
|
||||
c_addrb_width => 11,
|
||||
c_default_data => "0",
|
||||
c_use_ecc => 0,
|
||||
c_algorithm => 1,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_write_width_b => 22,
|
||||
c_write_width_a => 22,
|
||||
c_read_depth_b => 2048,
|
||||
c_read_depth_a => 2048,
|
||||
c_byte_size => 9,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_common_clk => 0,
|
||||
c_wea_width => 1,
|
||||
c_has_enb => 0,
|
||||
c_web_width => 1,
|
||||
c_has_ena => 0,
|
||||
c_use_byte_web => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_rst_priority_b => "CE",
|
||||
c_rst_priority_a => "CE",
|
||||
c_use_default_data => 0);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_deinter_lut
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta);
|
||||
-- synthesis translate_on
|
||||
|
||||
END deinter_lut_a;
|
||||
|
||||
60
verilog/coregen/deinter_lut.vho
Normal file
60
verilog/coregen/deinter_lut.vho
Normal file
@ -0,0 +1,60 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component deinter_lut
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(10 downto 0);
|
||||
douta: OUT std_logic_VECTOR(21 downto 0));
|
||||
end component;
|
||||
|
||||
-- Synplicity black box declaration
|
||||
attribute syn_black_box : boolean;
|
||||
attribute syn_black_box of deinter_lut: component is true;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : deinter_lut
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file deinter_lut.vhd when simulating
|
||||
-- the core, deinter_lut. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
93
verilog/coregen/deinter_lut.xco
Normal file
93
verilog/coregen/deinter_lut.xco
Normal file
@ -0,0 +1,93 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 12.2
|
||||
# Date: Mon Nov 7 16:54:10 2016
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc3sd3400a
|
||||
SET devicefamily = spartan3adsp
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fg676
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -5
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator family Xilinx,_Inc. 4.2
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET additional_inputs_for_power_estimation=false
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=false
|
||||
CSET byte_size=9
|
||||
CSET coe_file=/home/jinghaos/projects/jammer/uhd/fpga-src/usrp2/custom/deinter_lut.coe
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=deinter_lut
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET ecctype=No_ECC
|
||||
CSET enable_a=Always_Enabled
|
||||
CSET enable_b=Always_Enabled
|
||||
CSET error_injection_type=Single_Bit_Error_Injection
|
||||
CSET fill_remaining_memory_locations=false
|
||||
CSET load_init_file=true
|
||||
CSET memory_type=Single_Port_ROM
|
||||
CSET operating_mode_a=WRITE_FIRST
|
||||
CSET operating_mode_b=WRITE_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET port_a_clock=100
|
||||
CSET port_a_enable_rate=100
|
||||
CSET port_a_write_rate=0
|
||||
CSET port_b_clock=0
|
||||
CSET port_b_enable_rate=0
|
||||
CSET port_b_write_rate=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=22
|
||||
CSET read_width_b=22
|
||||
CSET register_porta_input_of_softecc=false
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_softecc=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET reset_memory_latch_a=false
|
||||
CSET reset_memory_latch_b=false
|
||||
CSET reset_priority_a=CE
|
||||
CSET reset_priority_b=CE
|
||||
CSET reset_type=SYNC
|
||||
CSET softecc=false
|
||||
CSET use_byte_write_enable=false
|
||||
CSET use_error_injection_pins=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_rsta_pin=false
|
||||
CSET use_rstb_pin=false
|
||||
CSET write_depth_a=2048
|
||||
CSET write_width_a=22
|
||||
CSET write_width_b=22
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: b978504c
|
||||
79
verilog/coregen/deinter_lut.xise
Normal file
79
verilog/coregen/deinter_lut.xise
Normal file
@ -0,0 +1,79 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="deinter_lut.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="deinter_lut.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="deinter_lut.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3sd3400a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan-3A DSP" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|deinter_lut|deinter_lut_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="deinter_lut.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/deinter_lut" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fg676" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="deinter_lut" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3adsp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-11-07T11:54:11" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3A40266961F7E507020FF3A42CC058B1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
17
verilog/coregen/deinter_lut_flist.txt
Normal file
17
verilog/coregen/deinter_lut_flist.txt
Normal file
@ -0,0 +1,17 @@
|
||||
# Output products list for <deinter_lut>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
blk_mem_gen_ds512.pdf
|
||||
blk_mem_gen_readme.txt
|
||||
deinter_lut.asy
|
||||
deinter_lut.gise
|
||||
deinter_lut.mif
|
||||
deinter_lut.ngc
|
||||
deinter_lut.sym
|
||||
deinter_lut.v
|
||||
deinter_lut.veo
|
||||
deinter_lut.vhd
|
||||
deinter_lut.vho
|
||||
deinter_lut.xco
|
||||
deinter_lut.xise
|
||||
deinter_lut_flist.txt
|
||||
deinter_lut_xmdf.tcl
|
||||
92
verilog/coregen/deinter_lut_xmdf.tcl
Normal file
92
verilog/coregen/deinter_lut_xmdf.tcl
Normal file
@ -0,0 +1,92 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide deinter_lut_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::deinter_lut_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::deinter_lut_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name deinter_lut
|
||||
}
|
||||
# ::deinter_lut_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::deinter_lut_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path deinter_lut.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path deinter_lut.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path deinter_lut.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path deinter_lut.sym
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path deinter_lut.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path deinter_lut.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path deinter_lut.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path deinter_lut.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path deinter_lut.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path deinter_lut_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module deinter_lut
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
29
verilog/coregen/div_gen_v3_0.asy
Normal file
29
verilog/coregen/div_gen_v3_0.asy
Normal file
@ -0,0 +1,29 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 div_gen_v3_0
|
||||
RECTANGLE Normal 32 32 544 384
|
||||
LINE Normal 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 208 32 208
|
||||
PIN 0 208 LEFT 36
|
||||
PINATTR PinName dividend[31:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 240 32 240
|
||||
PIN 0 240 LEFT 36
|
||||
PINATTR PinName divisor[23:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 576 80 544 80
|
||||
PIN 576 80 RIGHT 36
|
||||
PINATTR PinName rfd
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 208 544 208
|
||||
PIN 576 208 RIGHT 36
|
||||
PINATTR PinName quotient[31:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 240 544 240
|
||||
PIN 576 240 RIGHT 36
|
||||
PINATTR PinName fractional[23:0]
|
||||
PINATTR Polarity OUT
|
||||
|
||||
33
verilog/coregen/div_gen_v3_0.gise
Normal file
33
verilog/coregen/div_gen_v3_0.gise
Normal file
@ -0,0 +1,33 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="div_gen_v3_0.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="div_gen_v3_0.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="div_gen_v3_0.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="div_gen_v3_0.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="div_gen_v3_0.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
0
verilog/coregen/div_gen_v3_0.ncf
Normal file
0
verilog/coregen/div_gen_v3_0.ncf
Normal file
3
verilog/coregen/div_gen_v3_0.ngc
Normal file
3
verilog/coregen/div_gen_v3_0.ngc
Normal file
File diff suppressed because one or more lines are too long
27
verilog/coregen/div_gen_v3_0.sym
Normal file
27
verilog/coregen/div_gen_v3_0.sym
Normal file
@ -0,0 +1,27 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="div_gen_v3_0">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2016-9-15T18:35:53</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="clk" />
|
||||
<pin polarity="Input" x="0" y="208" name="dividend[31:0]" />
|
||||
<pin polarity="Input" x="0" y="240" name="divisor[23:0]" />
|
||||
<pin polarity="Output" x="576" y="80" name="rfd" />
|
||||
<pin polarity="Output" x="576" y="208" name="quotient[31:0]" />
|
||||
<pin polarity="Output" x="576" y="240" name="fractional[23:0]" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">div_gen_v3_0</text>
|
||||
<rect width="512" x="32" y="32" height="352" />
|
||||
<line x2="32" y1="80" y2="80" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk" />
|
||||
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin dividend[31:0]" />
|
||||
<line x2="32" y1="240" y2="240" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="240" type="pin divisor[23:0]" />
|
||||
<line x2="544" y1="80" y2="80" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin rfd" />
|
||||
<line x2="544" y1="208" y2="208" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="208" type="pin quotient[31:0]" />
|
||||
<line x2="544" y1="240" y2="240" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="240" type="pin fractional[23:0]" />
|
||||
</graph>
|
||||
</symbol>
|
||||
48
verilog/coregen/div_gen_v3_0.veo
Normal file
48
verilog/coregen/div_gen_v3_0.veo
Normal file
@ -0,0 +1,48 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used *
|
||||
* solely for design, simulation, implementation and creation of *
|
||||
* design files limited to Xilinx devices or technologies. Use *
|
||||
* with non-Xilinx devices or technologies is expressly prohibited *
|
||||
* and immediately terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
||||
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
||||
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
||||
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
||||
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
||||
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
||||
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
||||
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
||||
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
||||
* FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support *
|
||||
* appliances, devices, or systems. Use in such applications are *
|
||||
* expressly prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2009 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
div_gen_v3_0 YourInstanceName (
|
||||
.clk(clk),
|
||||
.rfd(rfd),
|
||||
.dividend(dividend), // Bus [31 : 0]
|
||||
.divisor(divisor), // Bus [23 : 0]
|
||||
.quotient(quotient), // Bus [31 : 0]
|
||||
.fractional(fractional)); // Bus [23 : 0]
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file div_gen_v3_0.v when simulating
|
||||
// the core, div_gen_v3_0. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
92362
verilog/coregen/div_gen_v3_0.vhd
Normal file
92362
verilog/coregen/div_gen_v3_0.vhd
Normal file
File diff suppressed because it is too large
Load Diff
66
verilog/coregen/div_gen_v3_0.vho
Normal file
66
verilog/coregen/div_gen_v3_0.vho
Normal file
@ -0,0 +1,66 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component div_gen_v3_0
|
||||
port (
|
||||
clk: IN std_logic;
|
||||
rfd: OUT std_logic;
|
||||
dividend: IN std_logic_VECTOR(31 downto 0);
|
||||
divisor: IN std_logic_VECTOR(23 downto 0);
|
||||
quotient: OUT std_logic_VECTOR(31 downto 0);
|
||||
fractional: OUT std_logic_VECTOR(23 downto 0));
|
||||
end component;
|
||||
|
||||
-- Synplicity black box declaration
|
||||
attribute syn_black_box : boolean;
|
||||
attribute syn_black_box of div_gen_v3_0: component is true;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : div_gen_v3_0
|
||||
port map (
|
||||
clk => clk,
|
||||
rfd => rfd,
|
||||
dividend => dividend,
|
||||
divisor => divisor,
|
||||
quotient => quotient,
|
||||
fractional => fractional);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file div_gen_v3_0.vhd when simulating
|
||||
-- the core, div_gen_v3_0. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
54
verilog/coregen/div_gen_v3_0.xco
Normal file
54
verilog/coregen/div_gen_v3_0.xco
Normal file
@ -0,0 +1,54 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 12.2
|
||||
# Date: Thu Sep 15 18:36:40 2016
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc3sd3400a
|
||||
SET devicefamily = spartan3adsp
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fg676
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -5
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Divider_Generator family Xilinx,_Inc. 3.0
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET algorithm_type=Radix2
|
||||
CSET ce=false
|
||||
CSET clocks_per_division=1
|
||||
CSET component_name=div_gen_v3_0
|
||||
CSET divide_by_zero_detect=false
|
||||
CSET dividend_and_quotient_width=32
|
||||
CSET divisor_width=24
|
||||
CSET fractional_width=24
|
||||
CSET latency=36
|
||||
CSET latency_configuration=Automatic
|
||||
CSET operand_sign=Signed
|
||||
CSET remainder_type=Remainder
|
||||
CSET sclr=false
|
||||
CSET sclr_ce_priority=SCLR_overrides_CE
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 9bd259e4
|
||||
79
verilog/coregen/div_gen_v3_0.xise
Normal file
79
verilog/coregen/div_gen_v3_0.xise
Normal file
@ -0,0 +1,79 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="div_gen_v3_0.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="div_gen_v3_0.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="div_gen_v3_0.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3sd3400a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan-3A DSP" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|div_gen_v3_0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="div_gen_v3_0.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/div_gen_v3_0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fg676" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="div_gen_v3_0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3adsp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-09-15T14:36:41" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AA4F572490132371B49E19E7D56CF8BA" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
15
verilog/coregen/div_gen_v3_0_flist.txt
Normal file
15
verilog/coregen/div_gen_v3_0_flist.txt
Normal file
@ -0,0 +1,15 @@
|
||||
# Output products list for <div_gen_v3_0>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
div_gen_v3_0.asy
|
||||
div_gen_v3_0.gise
|
||||
div_gen_v3_0.ngc
|
||||
div_gen_v3_0.sym
|
||||
div_gen_v3_0.v
|
||||
div_gen_v3_0.veo
|
||||
div_gen_v3_0.vhd
|
||||
div_gen_v3_0.vho
|
||||
div_gen_v3_0.xco
|
||||
div_gen_v3_0.xise
|
||||
div_gen_v3_0_flist.txt
|
||||
div_gen_v3_0_readme.txt
|
||||
div_gen_v3_0_xmdf.tcl
|
||||
60
verilog/coregen/div_gen_v3_0_readme.txt
Normal file
60
verilog/coregen/div_gen_v3_0_readme.txt
Normal file
@ -0,0 +1,60 @@
|
||||
The following files were generated for 'div_gen_v3_0' in directory
|
||||
/home/jinghaos/projects/jammer/uhd/fpga-src/usrp2/top/N2x0/build-N210R4-custom/ipcore_dir/
|
||||
|
||||
div_gen_v3_0.asy:
|
||||
Graphical symbol information file. Used by the ISE tools and some
|
||||
third party tools to create a symbol representing the core.
|
||||
|
||||
div_gen_v3_0.gise:
|
||||
ISE Project Navigator support file. This is a generated file and should
|
||||
not be edited directly.
|
||||
|
||||
div_gen_v3_0.ngc:
|
||||
Binary Xilinx implementation netlist file containing the information
|
||||
required to implement the module in a Xilinx (R) FPGA.
|
||||
|
||||
div_gen_v3_0.sym:
|
||||
Please see the core data sheet.
|
||||
|
||||
div_gen_v3_0.v:
|
||||
Verilog wrapper file provided to support functional simulation.
|
||||
This file contains simulation model customization data that is
|
||||
passed to a parameterized simulation model for the core.
|
||||
|
||||
div_gen_v3_0.veo:
|
||||
VEO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a Verilog design.
|
||||
|
||||
div_gen_v3_0.vhd:
|
||||
VHDL wrapper file provided to support functional simulation. This
|
||||
file contains simulation model customization data that is passed to
|
||||
a parameterized simulation model for the core.
|
||||
|
||||
div_gen_v3_0.vho:
|
||||
VHO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a VHDL design.
|
||||
|
||||
div_gen_v3_0.xco:
|
||||
CORE Generator input file containing the parameters used to
|
||||
regenerate a core.
|
||||
|
||||
div_gen_v3_0.xise:
|
||||
ISE Project Navigator support file. This is a generated file and should
|
||||
not be edited directly.
|
||||
|
||||
div_gen_v3_0_readme.txt:
|
||||
Text file indicating the files generated and how they are used.
|
||||
|
||||
div_gen_v3_0_xmdf.tcl:
|
||||
ISE Project Navigator interface file. ISE uses this file to determine
|
||||
how the files output by CORE Generator for the core can be integrated
|
||||
into your ISE project.
|
||||
|
||||
div_gen_v3_0_flist.txt:
|
||||
Text file listing all of the output files produced when a customized
|
||||
core was generated in the CORE Generator.
|
||||
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
80
verilog/coregen/div_gen_v3_0_xmdf.tcl
Normal file
80
verilog/coregen/div_gen_v3_0_xmdf.tcl
Normal file
@ -0,0 +1,80 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide div_gen_v3_0_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::div_gen_v3_0_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::div_gen_v3_0_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name div_gen_v3_0
|
||||
}
|
||||
# ::div_gen_v3_0_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::div_gen_v3_0_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_gen_v3_0.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_gen_v3_0.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_gen_v3_0.sym
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_gen_v3_0.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_gen_v3_0.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_gen_v3_0.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_gen_v3_0.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_gen_v3_0.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path div_gen_v3_0_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module div_gen_v3_0
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
29
verilog/coregen/rot_lut.asy
Normal file
29
verilog/coregen/rot_lut.asy
Normal file
@ -0,0 +1,29 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 rot_lut
|
||||
RECTANGLE Normal 32 32 544 672
|
||||
LINE Wide 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName addra[8:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 272 32 272
|
||||
PIN 0 272 LEFT 36
|
||||
PINATTR PinName clka
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 432 32 432
|
||||
PIN 0 432 LEFT 36
|
||||
PINATTR PinName addrb[8:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 624 32 624
|
||||
PIN 0 624 LEFT 36
|
||||
PINATTR PinName clkb
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 80 544 80
|
||||
PIN 576 80 RIGHT 36
|
||||
PINATTR PinName douta[31:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 368 544 368
|
||||
PIN 576 368 RIGHT 36
|
||||
PINATTR PinName doutb[31:0]
|
||||
PINATTR Polarity OUT
|
||||
|
||||
34
verilog/coregen/rot_lut.gise
Normal file
34
verilog/coregen/rot_lut.gise
Normal file
@ -0,0 +1,34 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="rot_lut.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="rot_lut.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="rot_lut.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="rot_lut.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="rot_lut.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
512
verilog/coregen/rot_lut.mif
Normal file
512
verilog/coregen/rot_lut.mif
Normal file
@ -0,0 +1,512 @@
|
||||
00001000000000000000000000000000
|
||||
00001000000000000000000000000100
|
||||
00001000000000000000000000001000
|
||||
00001000000000000000000000001100
|
||||
00001000000000000000000000010000
|
||||
00001000000000000000000000010100
|
||||
00001000000000000000000000011000
|
||||
00001000000000000000000000011100
|
||||
00001000000000000000000000100000
|
||||
00001000000000000000000000100100
|
||||
00001000000000000000000000101000
|
||||
00001000000000000000000000101100
|
||||
00000111111111110000000000110000
|
||||
00000111111111110000000000110100
|
||||
00000111111111110000000000111000
|
||||
00000111111111110000000000111100
|
||||
00000111111111110000000001000000
|
||||
00000111111111110000000001000100
|
||||
00000111111111110000000001001000
|
||||
00000111111111110000000001001100
|
||||
00000111111111100000000001010000
|
||||
00000111111111100000000001010100
|
||||
00000111111111100000000001011000
|
||||
00000111111111100000000001011100
|
||||
00000111111111100000000001100000
|
||||
00000111111111100000000001100100
|
||||
00000111111111010000000001101000
|
||||
00000111111111010000000001101100
|
||||
00000111111111010000000001110000
|
||||
00000111111111010000000001110100
|
||||
00000111111111000000000001111000
|
||||
00000111111111000000000001111100
|
||||
00000111111111000000000010000000
|
||||
00000111111111000000000010000100
|
||||
00000111111110110000000010001000
|
||||
00000111111110110000000010001100
|
||||
00000111111110110000000010010000
|
||||
00000111111110110000000010010100
|
||||
00000111111110100000000010011000
|
||||
00000111111110100000000010011100
|
||||
00000111111110100000000010100000
|
||||
00000111111110010000000010100100
|
||||
00000111111110010000000010101000
|
||||
00000111111110010000000010101100
|
||||
00000111111110000000000010110000
|
||||
00000111111110000000000010110100
|
||||
00000111111110000000000010111000
|
||||
00000111111101110000000010111100
|
||||
00000111111101110000000011000000
|
||||
00000111111101110000000011000100
|
||||
00000111111101100000000011001000
|
||||
00000111111101100000000011001100
|
||||
00000111111101010000000011010000
|
||||
00000111111101010000000011010100
|
||||
00000111111101010000000011011000
|
||||
00000111111101000000000011011100
|
||||
00000111111101000000000011100000
|
||||
00000111111100110000000011100100
|
||||
00000111111100110000000011101000
|
||||
00000111111100100000000011101100
|
||||
00000111111100100000000011110000
|
||||
00000111111100010000000011110011
|
||||
00000111111100010000000011110111
|
||||
00000111111100010000000011111011
|
||||
00000111111100000000000011111111
|
||||
00000111111100000000000100000011
|
||||
00000111111011110000000100000111
|
||||
00000111111011100000000100001011
|
||||
00000111111011100000000100001111
|
||||
00000111111011010000000100010011
|
||||
00000111111011010000000100010111
|
||||
00000111111011000000000100011011
|
||||
00000111111011000000000100011111
|
||||
00000111111010110000000100100011
|
||||
00000111111010110000000100100111
|
||||
00000111111010100000000100101011
|
||||
00000111111010010000000100101111
|
||||
00000111111010010000000100110011
|
||||
00000111111010000000000100110111
|
||||
00000111111010000000000100111011
|
||||
00000111111001110000000100111111
|
||||
00000111111001100000000101000011
|
||||
00000111111001100000000101000111
|
||||
00000111111001010000000101001011
|
||||
00000111111001000000000101001111
|
||||
00000111111001000000000101010011
|
||||
00000111111000110000000101010110
|
||||
00000111111000100000000101011010
|
||||
00000111111000100000000101011110
|
||||
00000111111000010000000101100010
|
||||
00000111111000000000000101100110
|
||||
00000111111000000000000101101010
|
||||
00000111110111110000000101101110
|
||||
00000111110111100000000101110010
|
||||
00000111110111100000000101110110
|
||||
00000111110111010000000101111010
|
||||
00000111110111000000000101111110
|
||||
00000111110110110000000110000010
|
||||
00000111110110110000000110000110
|
||||
00000111110110100000000110001010
|
||||
00000111110110010000000110001110
|
||||
00000111110110000000000110010010
|
||||
00000111110101110000000110010101
|
||||
00000111110101110000000110011001
|
||||
00000111110101100000000110011101
|
||||
00000111110101010000000110100001
|
||||
00000111110101000000000110100101
|
||||
00000111110100110000000110101001
|
||||
00000111110100110000000110101101
|
||||
00000111110100100000000110110001
|
||||
00000111110100010000000110110101
|
||||
00000111110100000000000110111001
|
||||
00000111110011110000000110111101
|
||||
00000111110011100000000111000000
|
||||
00000111110011010000000111000100
|
||||
00000111110011010000000111001000
|
||||
00000111110011000000000111001100
|
||||
00000111110010110000000111010000
|
||||
00000111110010100000000111010100
|
||||
00000111110010010000000111011000
|
||||
00000111110010000000000111011100
|
||||
00000111110001110000000111100000
|
||||
00000111110001100000000111100100
|
||||
00000111110001010000000111100111
|
||||
00000111110001000000000111101011
|
||||
00000111110000110000000111101111
|
||||
00000111110000100000000111110011
|
||||
00000111110000010000000111110111
|
||||
00000111110000000000000111111011
|
||||
00000111101111110000000111111111
|
||||
00000111101111100000001000000011
|
||||
00000111101111010000001000000110
|
||||
00000111101111000000001000001010
|
||||
00000111101110110000001000001110
|
||||
00000111101110100000001000010010
|
||||
00000111101110010000001000010110
|
||||
00000111101110000000001000011010
|
||||
00000111101101110000001000011110
|
||||
00000111101101100000001000100010
|
||||
00000111101101010000001000100101
|
||||
00000111101101000000001000101001
|
||||
00000111101100110000001000101101
|
||||
00000111101100100000001000110001
|
||||
00000111101100010000001000110101
|
||||
00000111101011110000001000111001
|
||||
00000111101011100000001000111100
|
||||
00000111101011010000001001000000
|
||||
00000111101011000000001001000100
|
||||
00000111101010110000001001001000
|
||||
00000111101010100000001001001100
|
||||
00000111101010010000001001010000
|
||||
00000111101010000000001001010011
|
||||
00000111101001100000001001010111
|
||||
00000111101001010000001001011011
|
||||
00000111101001000000001001011111
|
||||
00000111101000110000001001100011
|
||||
00000111101000100000001001100111
|
||||
00000111101000000000001001101010
|
||||
00000111100111110000001001101110
|
||||
00000111100111100000001001110010
|
||||
00000111100111010000001001110110
|
||||
00000111100111000000001001111010
|
||||
00000111100110100000001001111101
|
||||
00000111100110010000001010000001
|
||||
00000111100110000000001010000101
|
||||
00000111100101110000001010001001
|
||||
00000111100101010000001010001101
|
||||
00000111100101000000001010010000
|
||||
00000111100100110000001010010100
|
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||||
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|
||||
0
verilog/coregen/rot_lut.ncf
Normal file
0
verilog/coregen/rot_lut.ncf
Normal file
3
verilog/coregen/rot_lut.ngc
Normal file
3
verilog/coregen/rot_lut.ngc
Normal file
File diff suppressed because one or more lines are too long
27
verilog/coregen/rot_lut.sym
Normal file
27
verilog/coregen/rot_lut.sym
Normal file
@ -0,0 +1,27 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="rot_lut">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2016-11-7T19:10:59</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="addra[8:0]" />
|
||||
<pin polarity="Input" x="0" y="272" name="clka" />
|
||||
<pin polarity="Input" x="0" y="432" name="addrb[8:0]" />
|
||||
<pin polarity="Input" x="0" y="624" name="clkb" />
|
||||
<pin polarity="Output" x="576" y="80" name="douta[31:0]" />
|
||||
<pin polarity="Output" x="576" y="368" name="doutb[31:0]" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">rot_lut</text>
|
||||
<rect width="512" x="32" y="32" height="640" />
|
||||
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[8:0]" />
|
||||
<line x2="32" y1="272" y2="272" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
|
||||
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[8:0]" />
|
||||
<line x2="32" y1="624" y2="624" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
|
||||
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[31:0]" />
|
||||
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[31:0]" />
|
||||
</graph>
|
||||
</symbol>
|
||||
48
verilog/coregen/rot_lut.veo
Normal file
48
verilog/coregen/rot_lut.veo
Normal file
@ -0,0 +1,48 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used *
|
||||
* solely for design, simulation, implementation and creation of *
|
||||
* design files limited to Xilinx devices or technologies. Use *
|
||||
* with non-Xilinx devices or technologies is expressly prohibited *
|
||||
* and immediately terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
||||
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
||||
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
||||
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
||||
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
||||
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
||||
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
||||
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
||||
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
||||
* FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support *
|
||||
* appliances, devices, or systems. Use in such applications are *
|
||||
* expressly prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2009 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
rot_lut YourInstanceName (
|
||||
.clka(clka),
|
||||
.addra(addra), // Bus [8 : 0]
|
||||
.douta(douta), // Bus [31 : 0]
|
||||
.clkb(clkb),
|
||||
.addrb(addrb), // Bus [8 : 0]
|
||||
.doutb(doutb)); // Bus [31 : 0]
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file rot_lut.v when simulating
|
||||
// the core, rot_lut. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
135
verilog/coregen/rot_lut.vhd
Normal file
135
verilog/coregen/rot_lut.vhd
Normal file
@ -0,0 +1,135 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- You must compile the wrapper file rot_lut.vhd when simulating
|
||||
-- the core, rot_lut. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
-- The synthesis directives "translate_off/translate_on" specified
|
||||
-- below are supported by Xilinx, Mentor Graphics and Synplicity
|
||||
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
-- synthesis translate_off
|
||||
Library XilinxCoreLib;
|
||||
-- synthesis translate_on
|
||||
ENTITY rot_lut IS
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(8 downto 0);
|
||||
douta: OUT std_logic_VECTOR(31 downto 0);
|
||||
clkb: IN std_logic;
|
||||
addrb: IN std_logic_VECTOR(8 downto 0);
|
||||
doutb: OUT std_logic_VECTOR(31 downto 0));
|
||||
END rot_lut;
|
||||
|
||||
ARCHITECTURE rot_lut_a OF rot_lut IS
|
||||
-- synthesis translate_off
|
||||
component wrapped_rot_lut
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(8 downto 0);
|
||||
douta: OUT std_logic_VECTOR(31 downto 0);
|
||||
clkb: IN std_logic;
|
||||
addrb: IN std_logic_VECTOR(8 downto 0);
|
||||
doutb: OUT std_logic_VECTOR(31 downto 0));
|
||||
end component;
|
||||
|
||||
-- Configuration specification
|
||||
for all : wrapped_rot_lut use entity XilinxCoreLib.blk_mem_gen_v4_2(behavioral)
|
||||
generic map(
|
||||
c_has_regceb => 0,
|
||||
c_has_regcea => 0,
|
||||
c_mem_type => 4,
|
||||
c_rstram_b => 0,
|
||||
c_rstram_a => 0,
|
||||
c_has_injecterr => 0,
|
||||
c_rst_type => "SYNC",
|
||||
c_prim_type => 1,
|
||||
c_read_width_b => 32,
|
||||
c_initb_val => "0",
|
||||
c_family => "spartan3",
|
||||
c_read_width_a => 32,
|
||||
c_disable_warn_bhv_coll => 0,
|
||||
c_use_softecc => 0,
|
||||
c_write_mode_b => "WRITE_FIRST",
|
||||
c_init_file_name => "rot_lut.mif",
|
||||
c_write_mode_a => "WRITE_FIRST",
|
||||
c_mux_pipeline_stages => 0,
|
||||
c_has_softecc_output_regs_b => 0,
|
||||
c_has_mem_output_regs_b => 0,
|
||||
c_has_mem_output_regs_a => 0,
|
||||
c_load_init_file => 1,
|
||||
c_xdevicefamily => "spartan3adsp",
|
||||
c_write_depth_b => 512,
|
||||
c_write_depth_a => 512,
|
||||
c_has_rstb => 0,
|
||||
c_has_rsta => 0,
|
||||
c_has_mux_output_regs_b => 0,
|
||||
c_inita_val => "0",
|
||||
c_has_mux_output_regs_a => 0,
|
||||
c_addra_width => 9,
|
||||
c_has_softecc_input_regs_a => 0,
|
||||
c_addrb_width => 9,
|
||||
c_default_data => "0",
|
||||
c_use_ecc => 0,
|
||||
c_algorithm => 1,
|
||||
c_disable_warn_bhv_range => 0,
|
||||
c_write_width_b => 32,
|
||||
c_write_width_a => 32,
|
||||
c_read_depth_b => 512,
|
||||
c_read_depth_a => 512,
|
||||
c_byte_size => 9,
|
||||
c_sim_collision_check => "ALL",
|
||||
c_common_clk => 1,
|
||||
c_wea_width => 1,
|
||||
c_has_enb => 0,
|
||||
c_web_width => 1,
|
||||
c_has_ena => 0,
|
||||
c_use_byte_web => 0,
|
||||
c_use_byte_wea => 0,
|
||||
c_rst_priority_b => "CE",
|
||||
c_rst_priority_a => "CE",
|
||||
c_use_default_data => 0);
|
||||
-- synthesis translate_on
|
||||
BEGIN
|
||||
-- synthesis translate_off
|
||||
U0 : wrapped_rot_lut
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta,
|
||||
clkb => clkb,
|
||||
addrb => addrb,
|
||||
doutb => doutb);
|
||||
-- synthesis translate_on
|
||||
|
||||
END rot_lut_a;
|
||||
|
||||
66
verilog/coregen/rot_lut.vho
Normal file
66
verilog/coregen/rot_lut.vho
Normal file
@ -0,0 +1,66 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component rot_lut
|
||||
port (
|
||||
clka: IN std_logic;
|
||||
addra: IN std_logic_VECTOR(8 downto 0);
|
||||
douta: OUT std_logic_VECTOR(31 downto 0);
|
||||
clkb: IN std_logic;
|
||||
addrb: IN std_logic_VECTOR(8 downto 0);
|
||||
doutb: OUT std_logic_VECTOR(31 downto 0));
|
||||
end component;
|
||||
|
||||
-- Synplicity black box declaration
|
||||
attribute syn_black_box : boolean;
|
||||
attribute syn_black_box of rot_lut: component is true;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : rot_lut
|
||||
port map (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta,
|
||||
clkb => clkb,
|
||||
addrb => addrb,
|
||||
doutb => doutb);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file rot_lut.vhd when simulating
|
||||
-- the core, rot_lut. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
93
verilog/coregen/rot_lut.xco
Normal file
93
verilog/coregen/rot_lut.xco
Normal file
@ -0,0 +1,93 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 12.2
|
||||
# Date: Mon Nov 7 19:11:21 2016
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc3sd3400a
|
||||
SET devicefamily = spartan3adsp
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fg676
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -5
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Block_Memory_Generator family Xilinx,_Inc. 4.2
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET additional_inputs_for_power_estimation=false
|
||||
CSET algorithm=Minimum_Area
|
||||
CSET assume_synchronous_clk=true
|
||||
CSET byte_size=9
|
||||
CSET coe_file=/home/jinghaos/projects/jammer/uhd/fpga-src/usrp2/custom/rot_lut.coe
|
||||
CSET collision_warnings=ALL
|
||||
CSET component_name=rot_lut
|
||||
CSET disable_collision_warnings=false
|
||||
CSET disable_out_of_range_warnings=false
|
||||
CSET ecc=false
|
||||
CSET ecctype=No_ECC
|
||||
CSET enable_a=Always_Enabled
|
||||
CSET enable_b=Always_Enabled
|
||||
CSET error_injection_type=Single_Bit_Error_Injection
|
||||
CSET fill_remaining_memory_locations=false
|
||||
CSET load_init_file=true
|
||||
CSET memory_type=Dual_Port_ROM
|
||||
CSET operating_mode_a=WRITE_FIRST
|
||||
CSET operating_mode_b=WRITE_FIRST
|
||||
CSET output_reset_value_a=0
|
||||
CSET output_reset_value_b=0
|
||||
CSET pipeline_stages=0
|
||||
CSET port_a_clock=100
|
||||
CSET port_a_enable_rate=100
|
||||
CSET port_a_write_rate=0
|
||||
CSET port_b_clock=100
|
||||
CSET port_b_enable_rate=100
|
||||
CSET port_b_write_rate=0
|
||||
CSET primitive=8kx2
|
||||
CSET read_width_a=32
|
||||
CSET read_width_b=32
|
||||
CSET register_porta_input_of_softecc=false
|
||||
CSET register_porta_output_of_memory_core=false
|
||||
CSET register_porta_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_memory_core=false
|
||||
CSET register_portb_output_of_memory_primitives=false
|
||||
CSET register_portb_output_of_softecc=false
|
||||
CSET remaining_memory_locations=0
|
||||
CSET reset_memory_latch_a=false
|
||||
CSET reset_memory_latch_b=false
|
||||
CSET reset_priority_a=CE
|
||||
CSET reset_priority_b=CE
|
||||
CSET reset_type=SYNC
|
||||
CSET softecc=false
|
||||
CSET use_byte_write_enable=false
|
||||
CSET use_error_injection_pins=false
|
||||
CSET use_regcea_pin=false
|
||||
CSET use_regceb_pin=false
|
||||
CSET use_rsta_pin=false
|
||||
CSET use_rstb_pin=false
|
||||
CSET write_depth_a=512
|
||||
CSET write_width_a=32
|
||||
CSET write_width_b=32
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: eb4434e9
|
||||
79
verilog/coregen/rot_lut.xise
Normal file
79
verilog/coregen/rot_lut.xise
Normal file
@ -0,0 +1,79 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="rot_lut.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="rot_lut.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="rot_lut.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3sd3400a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan-3A DSP" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|rot_lut|rot_lut_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="rot_lut.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/rot_lut" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fg676" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="rot_lut" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3adsp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-11-07T14:11:22" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="924DBE55693A9D3F7CD05CC302B7C597" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
37
verilog/coregen/viterbi_v7_0.asy
Normal file
37
verilog/coregen/viterbi_v7_0.asy
Normal file
@ -0,0 +1,37 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 viterbi_v7_0
|
||||
RECTANGLE Normal 32 32 544 992
|
||||
LINE Wide 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName data_in0[2:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 112 32 112
|
||||
PIN 0 112 LEFT 36
|
||||
PINATTR PinName data_in1[2:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 336 32 336
|
||||
PIN 0 336 LEFT 36
|
||||
PINATTR PinName erase[1:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 912 32 912
|
||||
PIN 0 912 LEFT 36
|
||||
PINATTR PinName ce
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 944 32 944
|
||||
PIN 0 944 LEFT 36
|
||||
PINATTR PinName sclr
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 144 1024 144 992
|
||||
PIN 144 1024 BOTTOM 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 576 80 544 80
|
||||
PIN 576 80 RIGHT 36
|
||||
PINATTR PinName data_out
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 880 544 880
|
||||
PIN 576 880 RIGHT 36
|
||||
PINATTR PinName rdy
|
||||
PINATTR Polarity OUT
|
||||
|
||||
33
verilog/coregen/viterbi_v7_0.gise
Normal file
33
verilog/coregen/viterbi_v7_0.gise
Normal file
@ -0,0 +1,33 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="viterbi_v7_0.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="viterbi_v7_0.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="viterbi_v7_0.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="viterbi_v7_0.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="viterbi_v7_0.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
0
verilog/coregen/viterbi_v7_0.ncf
Normal file
0
verilog/coregen/viterbi_v7_0.ncf
Normal file
3
verilog/coregen/viterbi_v7_0.ngc
Normal file
3
verilog/coregen/viterbi_v7_0.ngc
Normal file
File diff suppressed because one or more lines are too long
33
verilog/coregen/viterbi_v7_0.sym
Normal file
33
verilog/coregen/viterbi_v7_0.sym
Normal file
@ -0,0 +1,33 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="viterbi_v7_0">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2016-10-29T21:52:21</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="data_in0[2:0]" />
|
||||
<pin polarity="Input" x="0" y="112" name="data_in1[2:0]" />
|
||||
<pin polarity="Input" x="0" y="336" name="erase[1:0]" />
|
||||
<pin polarity="Input" x="0" y="912" name="ce" />
|
||||
<pin polarity="Input" x="0" y="944" name="sclr" />
|
||||
<pin polarity="Input" x="144" y="1024" name="clk" />
|
||||
<pin polarity="Output" x="576" y="80" name="data_out" />
|
||||
<pin polarity="Output" x="576" y="880" name="rdy" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">viterbi_v7_0</text>
|
||||
<rect width="512" x="32" y="32" height="960" />
|
||||
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin data_in0[2:0]" />
|
||||
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin data_in1[2:0]" />
|
||||
<line x2="32" y1="336" y2="336" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="336" type="pin erase[1:0]" />
|
||||
<line x2="32" y1="912" y2="912" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="912" type="pin ce" />
|
||||
<line x2="32" y1="944" y2="944" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="944" type="pin sclr" />
|
||||
<line x2="144" y1="1024" y2="992" x1="144" />
|
||||
<attrtext style="alignment:BCENTER;fontsize:24;fontname:Arial" attrname="PinName" x="144" y="988" type="pin clk" />
|
||||
<line x2="544" y1="80" y2="80" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin data_out" />
|
||||
<line x2="544" y1="880" y2="880" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="880" type="pin rdy" />
|
||||
</graph>
|
||||
</symbol>
|
||||
50
verilog/coregen/viterbi_v7_0.veo
Normal file
50
verilog/coregen/viterbi_v7_0.veo
Normal file
@ -0,0 +1,50 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used *
|
||||
* solely for design, simulation, implementation and creation of *
|
||||
* design files limited to Xilinx devices or technologies. Use *
|
||||
* with non-Xilinx devices or technologies is expressly prohibited *
|
||||
* and immediately terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
||||
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
||||
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
||||
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
||||
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
||||
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
||||
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
||||
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
||||
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
||||
* FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support *
|
||||
* appliances, devices, or systems. Use in such applications are *
|
||||
* expressly prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2009 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
viterbi_v7_0 YourInstanceName (
|
||||
.data_in0(data_in0), // Bus [2 : 0]
|
||||
.data_in1(data_in1), // Bus [2 : 0]
|
||||
.erase(erase), // Bus [1 : 0]
|
||||
.data_out(data_out),
|
||||
.rdy(rdy),
|
||||
.ce(ce),
|
||||
.sclr(sclr),
|
||||
.clk(clk));
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file viterbi_v7_0.v when simulating
|
||||
// the core, viterbi_v7_0. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
82813
verilog/coregen/viterbi_v7_0.vhd
Normal file
82813
verilog/coregen/viterbi_v7_0.vhd
Normal file
File diff suppressed because it is too large
Load Diff
70
verilog/coregen/viterbi_v7_0.vho
Normal file
70
verilog/coregen/viterbi_v7_0.vho
Normal file
@ -0,0 +1,70 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component viterbi_v7_0
|
||||
port (
|
||||
data_in0: IN std_logic_VECTOR(2 downto 0);
|
||||
data_in1: IN std_logic_VECTOR(2 downto 0);
|
||||
erase: IN std_logic_VECTOR(1 downto 0);
|
||||
data_out: OUT std_logic;
|
||||
rdy: OUT std_logic;
|
||||
ce: IN std_logic;
|
||||
sclr: IN std_logic;
|
||||
clk: IN std_logic);
|
||||
end component;
|
||||
|
||||
-- Synplicity black box declaration
|
||||
attribute syn_black_box : boolean;
|
||||
attribute syn_black_box of viterbi_v7_0: component is true;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : viterbi_v7_0
|
||||
port map (
|
||||
data_in0 => data_in0,
|
||||
data_in1 => data_in1,
|
||||
erase => erase,
|
||||
data_out => data_out,
|
||||
rdy => rdy,
|
||||
ce => ce,
|
||||
sclr => sclr,
|
||||
clk => clk);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file viterbi_v7_0.vhd when simulating
|
||||
-- the core, viterbi_v7_0. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
85
verilog/coregen/viterbi_v7_0.xco
Normal file
85
verilog/coregen/viterbi_v7_0.xco
Normal file
@ -0,0 +1,85 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 12.2
|
||||
# Date: Sat Oct 29 21:54:23 2016
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc3sd3400a
|
||||
SET devicefamily = spartan3adsp
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fg676
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Structural
|
||||
SET speedgrade = -5
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Viterbi_Decoder family Xilinx,_Inc. 7.0
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET architecture=Parallel
|
||||
CSET ber_symbol_count=false
|
||||
CSET ber_thresh=600
|
||||
CSET best_state=true
|
||||
CSET best_state_width=3
|
||||
CSET block_valid=false
|
||||
CSET ce=true
|
||||
CSET channels=1
|
||||
CSET coding=Soft_Coding
|
||||
CSET component_name=viterbi_v7_0
|
||||
CSET constraint_length=7
|
||||
CSET convolution0_code0=133
|
||||
CSET convolution0_code1=171
|
||||
CSET convolution0_code2=0
|
||||
CSET convolution0_code3=0
|
||||
CSET convolution0_code4=0
|
||||
CSET convolution0_code5=0
|
||||
CSET convolution0_code6=0
|
||||
CSET convolution1_code0=1111001
|
||||
CSET convolution1_code1=1011011
|
||||
CSET convolution1_code2=0
|
||||
CSET convolution1_code3=0
|
||||
CSET convolution1_code4=0
|
||||
CSET convolution1_code5=0
|
||||
CSET convolution1_code6=0
|
||||
CSET convolution_code_0_radix=Octal
|
||||
CSET convolution_code_1_radix=Binary
|
||||
CSET data_format=Signed_Magnitude
|
||||
CSET direct_traceback=None
|
||||
CSET dynamic_thresholds=false
|
||||
CSET maximum_direct=24
|
||||
CSET norm=false
|
||||
CSET norm_thresh=250
|
||||
CSET number_of_ber_symbols=300
|
||||
CSET output_rate0=2
|
||||
CSET output_rate1=2
|
||||
CSET puncturing=External
|
||||
CSET rdy=true
|
||||
CSET reduced_latency=true
|
||||
CSET soft_width=3
|
||||
CSET synchronization=false
|
||||
CSET synchronous_clear=true
|
||||
CSET traceback_length=24
|
||||
CSET trellis_initialization=None
|
||||
CSET viterbi_type=Standard
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: a323316c
|
||||
79
verilog/coregen/viterbi_v7_0.xise
Normal file
79
verilog/coregen/viterbi_v7_0.xise
Normal file
@ -0,0 +1,79 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="viterbi_v7_0.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="viterbi_v7_0.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="viterbi_v7_0.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3sd3400a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan-3A DSP" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|viterbi_v7_0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="viterbi_v7_0.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/viterbi_v7_0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fg676" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="viterbi_v7_0" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3adsp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-10-29T17:54:24" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7541A8CD9CD2EC6979D8E26E2E7589BB" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
18
verilog/coregen/viterbi_v7_0_flist.txt
Normal file
18
verilog/coregen/viterbi_v7_0_flist.txt
Normal file
@ -0,0 +1,18 @@
|
||||
# Output products list for <viterbi_v7_0>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
viterbi_v7_0.asy
|
||||
viterbi_v7_0.gise
|
||||
viterbi_v7_0.ngc
|
||||
viterbi_v7_0.sym
|
||||
viterbi_v7_0.v
|
||||
viterbi_v7_0.veo
|
||||
viterbi_v7_0.vhd
|
||||
viterbi_v7_0.vho
|
||||
viterbi_v7_0.xco
|
||||
viterbi_v7_0.xise
|
||||
viterbi_v7_0_flist.txt
|
||||
viterbi_v7_0_readme.txt
|
||||
viterbi_v7_0_xmdf.tcl
|
||||
viterbi_v7_0rombram.mif
|
||||
viterbi_v7_0romlifo.mif
|
||||
viterbi_v7_0romwe.mif
|
||||
78
verilog/coregen/viterbi_v7_0_readme.txt
Normal file
78
verilog/coregen/viterbi_v7_0_readme.txt
Normal file
@ -0,0 +1,78 @@
|
||||
The following files were generated for 'viterbi_v7_0' in directory
|
||||
/home/jinghaos/projects/jammer/uhd/fpga-src/usrp2/top/N2x0/build-N210R4-custom/ipcore_dir/
|
||||
|
||||
viterbi_v7_0.asy:
|
||||
Graphical symbol information file. Used by the ISE tools and some
|
||||
third party tools to create a symbol representing the core.
|
||||
|
||||
viterbi_v7_0.gise:
|
||||
ISE Project Navigator support file. This is a generated file and should
|
||||
not be edited directly.
|
||||
|
||||
viterbi_v7_0.ngc:
|
||||
Binary Xilinx implementation netlist file containing the information
|
||||
required to implement the module in a Xilinx (R) FPGA.
|
||||
|
||||
viterbi_v7_0.sym:
|
||||
Please see the core data sheet.
|
||||
|
||||
viterbi_v7_0.v:
|
||||
Verilog wrapper file provided to support functional simulation.
|
||||
This file contains simulation model customization data that is
|
||||
passed to a parameterized simulation model for the core.
|
||||
|
||||
viterbi_v7_0.veo:
|
||||
VEO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a Verilog design.
|
||||
|
||||
viterbi_v7_0.vhd:
|
||||
VHDL wrapper file provided to support functional simulation. This
|
||||
file contains simulation model customization data that is passed to
|
||||
a parameterized simulation model for the core.
|
||||
|
||||
viterbi_v7_0.vho:
|
||||
VHO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a VHDL design.
|
||||
|
||||
viterbi_v7_0.xco:
|
||||
CORE Generator input file containing the parameters used to
|
||||
regenerate a core.
|
||||
|
||||
viterbi_v7_0.xise:
|
||||
ISE Project Navigator support file. This is a generated file and should
|
||||
not be edited directly.
|
||||
|
||||
viterbi_v7_0_readme.txt:
|
||||
Text file indicating the files generated and how they are used.
|
||||
|
||||
viterbi_v7_0_xmdf.tcl:
|
||||
ISE Project Navigator interface file. ISE uses this file to determine
|
||||
how the files output by CORE Generator for the core can be integrated
|
||||
into your ISE project.
|
||||
|
||||
viterbi_v7_0rombram.mif:
|
||||
Memory Initialization File which is automatically generated by the
|
||||
CORE Generator System for some modules when a simulation flow is
|
||||
specified. A MIF data file is used to support HDL functional
|
||||
simulation of modules which use arrays of values.
|
||||
|
||||
viterbi_v7_0romlifo.mif:
|
||||
Memory Initialization File which is automatically generated by the
|
||||
CORE Generator System for some modules when a simulation flow is
|
||||
specified. A MIF data file is used to support HDL functional
|
||||
simulation of modules which use arrays of values.
|
||||
|
||||
viterbi_v7_0romwe.mif:
|
||||
Memory Initialization File which is automatically generated by the
|
||||
CORE Generator System for some modules when a simulation flow is
|
||||
specified. A MIF data file is used to support HDL functional
|
||||
simulation of modules which use arrays of values.
|
||||
|
||||
viterbi_v7_0_flist.txt:
|
||||
Text file listing all of the output files produced when a customized
|
||||
core was generated in the CORE Generator.
|
||||
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
92
verilog/coregen/viterbi_v7_0_xmdf.tcl
Normal file
92
verilog/coregen/viterbi_v7_0_xmdf.tcl
Normal file
@ -0,0 +1,92 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide viterbi_v7_0_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::viterbi_v7_0_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::viterbi_v7_0_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name viterbi_v7_0
|
||||
}
|
||||
# ::viterbi_v7_0_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::viterbi_v7_0_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0.sym
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0rombram.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0romlifo.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path viterbi_v7_0romwe.mif
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module viterbi_v7_0
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
48
verilog/coregen/viterbi_v7_0rombram.mif
Normal file
48
verilog/coregen/viterbi_v7_0rombram.mif
Normal file
@ -0,0 +1,48 @@
|
||||
101111101110101101000000
|
||||
101011101100000001101010
|
||||
101001101000100111000010
|
||||
100101100110000011100100
|
||||
100011100010100001000100
|
||||
011111100000000101011110
|
||||
011101011100011011000110
|
||||
011001011010000111011000
|
||||
010111010110010101001000
|
||||
010011010100001001010010
|
||||
010001010000001111001010
|
||||
001101001110001011001100
|
||||
001011001010001001001100
|
||||
000111001000001101000110
|
||||
000101000100000011001110
|
||||
000001000010001111000000
|
||||
101111101110101101010000
|
||||
101011101100010001101010
|
||||
101001101000100111010010
|
||||
100101100110010011100100
|
||||
100011100010100001010100
|
||||
011111100000010101011110
|
||||
011101011100011011010110
|
||||
011001011010010111011000
|
||||
010111010110010101011000
|
||||
010011010100011001010010
|
||||
010001010000001111011010
|
||||
001101001110011011001100
|
||||
001011001010001001011100
|
||||
000111001000011101000110
|
||||
000101000100000011011110
|
||||
000001000010011111000000
|
||||
101111101110101101100000
|
||||
101011101100100001101010
|
||||
101001101000100111100010
|
||||
100101100110100011100100
|
||||
100011100010100001100100
|
||||
011111100000100101011110
|
||||
011101011100011011100110
|
||||
011001011010100111011000
|
||||
010111010110010101101000
|
||||
010011010100101001010010
|
||||
010001010000001111101010
|
||||
001101001110101011001100
|
||||
001011001010001001101100
|
||||
000111001000101101000110
|
||||
000101000100000011101110
|
||||
000001000010101111000000
|
||||
16
verilog/coregen/viterbi_v7_0romlifo.mif
Normal file
16
verilog/coregen/viterbi_v7_0romlifo.mif
Normal file
@ -0,0 +1,16 @@
|
||||
11
|
||||
11
|
||||
11
|
||||
10
|
||||
10
|
||||
10
|
||||
01
|
||||
01
|
||||
01
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
00
|
||||
16
verilog/coregen/viterbi_v7_0romwe.mif
Normal file
16
verilog/coregen/viterbi_v7_0romwe.mif
Normal file
@ -0,0 +1,16 @@
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
65
verilog/coregen/xfft_v7_1.asy
Normal file
65
verilog/coregen/xfft_v7_1.asy
Normal file
@ -0,0 +1,65 @@
|
||||
Version 4
|
||||
SymbolType BLOCK
|
||||
TEXT 32 32 LEFT 4 xfft_v7_1
|
||||
RECTANGLE Normal 32 32 544 3104
|
||||
LINE Wide 0 80 32 80
|
||||
PIN 0 80 LEFT 36
|
||||
PINATTR PinName xn_re[15:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 0 528 32 528
|
||||
PIN 0 528 LEFT 36
|
||||
PINATTR PinName xn_im[15:0]
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 976 32 976
|
||||
PIN 0 976 LEFT 36
|
||||
PINATTR PinName start
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1200 32 1200
|
||||
PIN 0 1200 LEFT 36
|
||||
PINATTR PinName fwd_inv
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 1648 32 1648
|
||||
PIN 0 1648 LEFT 36
|
||||
PINATTR PinName fwd_inv_we
|
||||
PINATTR Polarity IN
|
||||
LINE Normal 0 3056 32 3056
|
||||
PIN 0 3056 LEFT 36
|
||||
PINATTR PinName clk
|
||||
PINATTR Polarity IN
|
||||
LINE Wide 576 80 544 80
|
||||
PIN 576 80 RIGHT 36
|
||||
PINATTR PinName xk_re[22:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 528 544 528
|
||||
PIN 576 528 RIGHT 36
|
||||
PINATTR PinName xk_im[22:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 976 544 976
|
||||
PIN 576 976 RIGHT 36
|
||||
PINATTR PinName xn_index[5:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Wide 576 1008 544 1008
|
||||
PIN 576 1008 RIGHT 36
|
||||
PINATTR PinName xk_index[5:0]
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1040 544 1040
|
||||
PIN 576 1040 RIGHT 36
|
||||
PINATTR PinName rfd
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1072 544 1072
|
||||
PIN 576 1072 RIGHT 36
|
||||
PINATTR PinName busy
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1104 544 1104
|
||||
PIN 576 1104 RIGHT 36
|
||||
PINATTR PinName dv
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1136 544 1136
|
||||
PIN 576 1136 RIGHT 36
|
||||
PINATTR PinName edone
|
||||
PINATTR Polarity OUT
|
||||
LINE Normal 576 1168 544 1168
|
||||
PIN 576 1168 RIGHT 36
|
||||
PINATTR PinName done
|
||||
PINATTR Polarity OUT
|
||||
|
||||
33
verilog/coregen/xfft_v7_1.gise
Normal file
33
verilog/coregen/xfft_v7_1.gise
Normal file
@ -0,0 +1,33 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="xfft_v7_1.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_ASY" xil_pn:name="xfft_v7_1.asy" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="xfft_v7_1.sym" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VEO" xil_pn:name="xfft_v7_1.veo" xil_pn:origination="imported"/>
|
||||
<file xil_pn:fileType="FILE_VHO" xil_pn:name="xfft_v7_1.vho" xil_pn:origination="imported"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
|
||||
|
||||
</generated_project>
|
||||
0
verilog/coregen/xfft_v7_1.ncf
Normal file
0
verilog/coregen/xfft_v7_1.ncf
Normal file
3
verilog/coregen/xfft_v7_1.ngc
Normal file
3
verilog/coregen/xfft_v7_1.ngc
Normal file
File diff suppressed because one or more lines are too long
54
verilog/coregen/xfft_v7_1.sym
Normal file
54
verilog/coregen/xfft_v7_1.sym
Normal file
@ -0,0 +1,54 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<symbol version="7" name="xfft_v7_1">
|
||||
<symboltype>BLOCK</symboltype>
|
||||
<timestamp>2016-8-23T1:58:58</timestamp>
|
||||
<pin polarity="Input" x="0" y="80" name="xn_re[15:0]" />
|
||||
<pin polarity="Input" x="0" y="528" name="xn_im[15:0]" />
|
||||
<pin polarity="Input" x="0" y="976" name="start" />
|
||||
<pin polarity="Input" x="0" y="1200" name="fwd_inv" />
|
||||
<pin polarity="Input" x="0" y="1648" name="fwd_inv_we" />
|
||||
<pin polarity="Input" x="0" y="3056" name="clk" />
|
||||
<pin polarity="Output" x="576" y="80" name="xk_re[22:0]" />
|
||||
<pin polarity="Output" x="576" y="528" name="xk_im[22:0]" />
|
||||
<pin polarity="Output" x="576" y="976" name="xn_index[5:0]" />
|
||||
<pin polarity="Output" x="576" y="1008" name="xk_index[5:0]" />
|
||||
<pin polarity="Output" x="576" y="1040" name="rfd" />
|
||||
<pin polarity="Output" x="576" y="1072" name="busy" />
|
||||
<pin polarity="Output" x="576" y="1104" name="dv" />
|
||||
<pin polarity="Output" x="576" y="1136" name="edone" />
|
||||
<pin polarity="Output" x="576" y="1168" name="done" />
|
||||
<graph>
|
||||
<text style="fontsize:40;fontname:Arial" x="32" y="32">xfft_v7_1</text>
|
||||
<rect width="512" x="32" y="32" height="3072" />
|
||||
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin xn_re[15:0]" />
|
||||
<line x2="32" y1="528" y2="528" style="linewidth:W" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="528" type="pin xn_im[15:0]" />
|
||||
<line x2="32" y1="976" y2="976" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="976" type="pin start" />
|
||||
<line x2="32" y1="1200" y2="1200" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="1200" type="pin fwd_inv" />
|
||||
<line x2="32" y1="1648" y2="1648" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="1648" type="pin fwd_inv_we" />
|
||||
<line x2="32" y1="3056" y2="3056" x1="0" />
|
||||
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="3056" type="pin clk" />
|
||||
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin xk_re[22:0]" />
|
||||
<line x2="544" y1="528" y2="528" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="528" type="pin xk_im[22:0]" />
|
||||
<line x2="544" y1="976" y2="976" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="976" type="pin xn_index[5:0]" />
|
||||
<line x2="544" y1="1008" y2="1008" style="linewidth:W" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="1008" type="pin xk_index[5:0]" />
|
||||
<line x2="544" y1="1040" y2="1040" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="1040" type="pin rfd" />
|
||||
<line x2="544" y1="1072" y2="1072" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="1072" type="pin busy" />
|
||||
<line x2="544" y1="1104" y2="1104" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="1104" type="pin dv" />
|
||||
<line x2="544" y1="1136" y2="1136" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="1136" type="pin edone" />
|
||||
<line x2="544" y1="1168" y2="1168" x1="576" />
|
||||
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="1168" type="pin done" />
|
||||
</graph>
|
||||
</symbol>
|
||||
57
verilog/coregen/xfft_v7_1.veo
Normal file
57
verilog/coregen/xfft_v7_1.veo
Normal file
@ -0,0 +1,57 @@
|
||||
/*******************************************************************************
|
||||
* This file is owned and controlled by Xilinx and must be used *
|
||||
* solely for design, simulation, implementation and creation of *
|
||||
* design files limited to Xilinx devices or technologies. Use *
|
||||
* with non-Xilinx devices or technologies is expressly prohibited *
|
||||
* and immediately terminates your license. *
|
||||
* *
|
||||
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
|
||||
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
|
||||
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
|
||||
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
|
||||
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
|
||||
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
|
||||
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
|
||||
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
|
||||
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
|
||||
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
|
||||
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
|
||||
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
|
||||
* FOR A PARTICULAR PURPOSE. *
|
||||
* *
|
||||
* Xilinx products are not intended for use in life support *
|
||||
* appliances, devices, or systems. Use in such applications are *
|
||||
* expressly prohibited. *
|
||||
* *
|
||||
* (c) Copyright 1995-2009 Xilinx, Inc. *
|
||||
* All rights reserved. *
|
||||
*******************************************************************************/
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
xfft_v7_1 YourInstanceName (
|
||||
.clk(clk),
|
||||
.start(start),
|
||||
.xn_re(xn_re), // Bus [15 : 0]
|
||||
.xn_im(xn_im), // Bus [15 : 0]
|
||||
.fwd_inv(fwd_inv),
|
||||
.fwd_inv_we(fwd_inv_we),
|
||||
.rfd(rfd),
|
||||
.xn_index(xn_index), // Bus [5 : 0]
|
||||
.busy(busy),
|
||||
.edone(edone),
|
||||
.done(done),
|
||||
.dv(dv),
|
||||
.xk_index(xk_index), // Bus [5 : 0]
|
||||
.xk_re(xk_re), // Bus [22 : 0]
|
||||
.xk_im(xk_im)); // Bus [22 : 0]
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file xfft_v7_1.v when simulating
|
||||
// the core, xfft_v7_1. When compiling the wrapper file, be sure to
|
||||
// reference the XilinxCoreLib Verilog simulation library. For detailed
|
||||
// instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
61189
verilog/coregen/xfft_v7_1.vhd
Normal file
61189
verilog/coregen/xfft_v7_1.vhd
Normal file
File diff suppressed because it is too large
Load Diff
84
verilog/coregen/xfft_v7_1.vho
Normal file
84
verilog/coregen/xfft_v7_1.vho
Normal file
@ -0,0 +1,84 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- This file is owned and controlled by Xilinx and must be used --
|
||||
-- solely for design, simulation, implementation and creation of --
|
||||
-- design files limited to Xilinx devices or technologies. Use --
|
||||
-- with non-Xilinx devices or technologies is expressly prohibited --
|
||||
-- and immediately terminates your license. --
|
||||
-- --
|
||||
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
|
||||
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
|
||||
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
|
||||
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
|
||||
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
|
||||
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
|
||||
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
|
||||
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
|
||||
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
|
||||
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
|
||||
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
|
||||
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
|
||||
-- FOR A PARTICULAR PURPOSE. --
|
||||
-- --
|
||||
-- Xilinx products are not intended for use in life support --
|
||||
-- appliances, devices, or systems. Use in such applications are --
|
||||
-- expressly prohibited. --
|
||||
-- --
|
||||
-- (c) Copyright 1995-2009 Xilinx, Inc. --
|
||||
-- All rights reserved. --
|
||||
--------------------------------------------------------------------------------
|
||||
-- The following code must appear in the VHDL architecture header:
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
component xfft_v7_1
|
||||
port (
|
||||
clk: IN std_logic;
|
||||
start: IN std_logic;
|
||||
xn_re: IN std_logic_VECTOR(15 downto 0);
|
||||
xn_im: IN std_logic_VECTOR(15 downto 0);
|
||||
fwd_inv: IN std_logic;
|
||||
fwd_inv_we: IN std_logic;
|
||||
rfd: OUT std_logic;
|
||||
xn_index: OUT std_logic_VECTOR(5 downto 0);
|
||||
busy: OUT std_logic;
|
||||
edone: OUT std_logic;
|
||||
done: OUT std_logic;
|
||||
dv: OUT std_logic;
|
||||
xk_index: OUT std_logic_VECTOR(5 downto 0);
|
||||
xk_re: OUT std_logic_VECTOR(22 downto 0);
|
||||
xk_im: OUT std_logic_VECTOR(22 downto 0));
|
||||
end component;
|
||||
|
||||
-- Synplicity black box declaration
|
||||
attribute syn_black_box : boolean;
|
||||
attribute syn_black_box of xfft_v7_1: component is true;
|
||||
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : xfft_v7_1
|
||||
port map (
|
||||
clk => clk,
|
||||
start => start,
|
||||
xn_re => xn_re,
|
||||
xn_im => xn_im,
|
||||
fwd_inv => fwd_inv,
|
||||
fwd_inv_we => fwd_inv_we,
|
||||
rfd => rfd,
|
||||
xn_index => xn_index,
|
||||
busy => busy,
|
||||
edone => edone,
|
||||
done => done,
|
||||
dv => dv,
|
||||
xk_index => xk_index,
|
||||
xk_re => xk_re,
|
||||
xk_im => xk_im);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ------------
|
||||
|
||||
-- You must compile the wrapper file xfft_v7_1.vhd when simulating
|
||||
-- the core, xfft_v7_1. When compiling the wrapper file, be sure to
|
||||
-- reference the XilinxCoreLib VHDL simulation library. For detailed
|
||||
-- instructions, please refer to the "CORE Generator Help".
|
||||
|
||||
65
verilog/coregen/xfft_v7_1.xco
Normal file
65
verilog/coregen/xfft_v7_1.xco
Normal file
@ -0,0 +1,65 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 12.2
|
||||
# Date: Tue Aug 23 02:00:18 2016
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = Verilog
|
||||
SET device = xc3sd3400a
|
||||
SET devicefamily = spartan3adsp
|
||||
SET flowvendor = Foundation_ISE
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = fg676
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -5
|
||||
SET verilogsim = true
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Fast_Fourier_Transform family Xilinx,_Inc. 7.1
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET butterfly_type=use_luts
|
||||
CSET ce=false
|
||||
CSET channels=1
|
||||
CSET complex_mult_type=use_mults_resources
|
||||
CSET component_name=xfft_v7_1
|
||||
CSET cyclic_prefix_insertion=false
|
||||
CSET data_format=fixed_point
|
||||
CSET implementation_options=pipelined_streaming_io
|
||||
CSET input_data_offset=no_offset
|
||||
CSET input_width=16
|
||||
CSET memory_options_data=block_ram
|
||||
CSET memory_options_hybrid=false
|
||||
CSET memory_options_phase_factors=block_ram
|
||||
CSET memory_options_reorder=block_ram
|
||||
CSET number_of_stages_using_block_ram_for_data_and_phase_factors=0
|
||||
CSET output_ordering=natural_order
|
||||
CSET ovflo=false
|
||||
CSET phase_factor_width=16
|
||||
CSET rounding_modes=truncation
|
||||
CSET run_time_configurable_transform_length=false
|
||||
CSET scaling_options=unscaled
|
||||
CSET sclr=false
|
||||
CSET target_clock_frequency=100
|
||||
CSET target_data_throughput=50
|
||||
CSET transform_length=64
|
||||
# END Parameters
|
||||
GENERATE
|
||||
# CRC: 2da176bc
|
||||
79
verilog/coregen/xfft_v7_1.xise
Normal file
79
verilog/coregen/xfft_v7_1.xise
Normal file
@ -0,0 +1,79 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="xfft_v7_1.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
</file>
|
||||
<file xil_pn:name="xfft_v7_1.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
<file xil_pn:name="xfft_v7_1.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation"/>
|
||||
<association xil_pn:name="Implementation"/>
|
||||
<association xil_pn:name="PostMapSimulation"/>
|
||||
<association xil_pn:name="PostRouteSimulation"/>
|
||||
<association xil_pn:name="PostTranslateSimulation"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3sd3400a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan-3A DSP" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|xfft_v7_1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="xfft_v7_1.ngc" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/xfft_v7_1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="fg676" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="xfft_v7_1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3adsp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-08-22T19:00:19" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="034CA33B73FD7FC0A73F85518C92169C" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
15
verilog/coregen/xfft_v7_1_flist.txt
Normal file
15
verilog/coregen/xfft_v7_1_flist.txt
Normal file
@ -0,0 +1,15 @@
|
||||
# Output products list for <xfft_v7_1>
|
||||
_xmsgs/pn_parser.xmsgs
|
||||
xfft_v7_1.asy
|
||||
xfft_v7_1.gise
|
||||
xfft_v7_1.ngc
|
||||
xfft_v7_1.sym
|
||||
xfft_v7_1.v
|
||||
xfft_v7_1.veo
|
||||
xfft_v7_1.vhd
|
||||
xfft_v7_1.vho
|
||||
xfft_v7_1.xco
|
||||
xfft_v7_1.xise
|
||||
xfft_v7_1_flist.txt
|
||||
xfft_v7_1_readme.txt
|
||||
xfft_v7_1_xmdf.tcl
|
||||
60
verilog/coregen/xfft_v7_1_readme.txt
Normal file
60
verilog/coregen/xfft_v7_1_readme.txt
Normal file
@ -0,0 +1,60 @@
|
||||
The following files were generated for 'xfft_v7_1' in directory
|
||||
/home/jinghaos/projects/jammer/uhd/fpga-src/usrp2/top/N2x0/build-N210R4-custom/ipcore_dir/
|
||||
|
||||
xfft_v7_1.asy:
|
||||
Graphical symbol information file. Used by the ISE tools and some
|
||||
third party tools to create a symbol representing the core.
|
||||
|
||||
xfft_v7_1.gise:
|
||||
ISE Project Navigator support file. This is a generated file and should
|
||||
not be edited directly.
|
||||
|
||||
xfft_v7_1.ngc:
|
||||
Binary Xilinx implementation netlist file containing the information
|
||||
required to implement the module in a Xilinx (R) FPGA.
|
||||
|
||||
xfft_v7_1.sym:
|
||||
Please see the core data sheet.
|
||||
|
||||
xfft_v7_1.v:
|
||||
Verilog wrapper file provided to support functional simulation.
|
||||
This file contains simulation model customization data that is
|
||||
passed to a parameterized simulation model for the core.
|
||||
|
||||
xfft_v7_1.veo:
|
||||
VEO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a Verilog design.
|
||||
|
||||
xfft_v7_1.vhd:
|
||||
VHDL wrapper file provided to support functional simulation. This
|
||||
file contains simulation model customization data that is passed to
|
||||
a parameterized simulation model for the core.
|
||||
|
||||
xfft_v7_1.vho:
|
||||
VHO template file containing code that can be used as a model for
|
||||
instantiating a CORE Generator module in a VHDL design.
|
||||
|
||||
xfft_v7_1.xco:
|
||||
CORE Generator input file containing the parameters used to
|
||||
regenerate a core.
|
||||
|
||||
xfft_v7_1.xise:
|
||||
ISE Project Navigator support file. This is a generated file and should
|
||||
not be edited directly.
|
||||
|
||||
xfft_v7_1_readme.txt:
|
||||
Text file indicating the files generated and how they are used.
|
||||
|
||||
xfft_v7_1_xmdf.tcl:
|
||||
ISE Project Navigator interface file. ISE uses this file to determine
|
||||
how the files output by CORE Generator for the core can be integrated
|
||||
into your ISE project.
|
||||
|
||||
xfft_v7_1_flist.txt:
|
||||
Text file listing all of the output files produced when a customized
|
||||
core was generated in the CORE Generator.
|
||||
|
||||
|
||||
Please see the Xilinx CORE Generator online help for further details on
|
||||
generated files and how to use them.
|
||||
|
||||
80
verilog/coregen/xfft_v7_1_xmdf.tcl
Normal file
80
verilog/coregen/xfft_v7_1_xmdf.tcl
Normal file
@ -0,0 +1,80 @@
|
||||
# The package naming convention is <core_name>_xmdf
|
||||
package provide xfft_v7_1_xmdf 1.0
|
||||
|
||||
# This includes some utilities that support common XMDF operations
|
||||
package require utilities_xmdf
|
||||
|
||||
# Define a namespace for this package. The name of the name space
|
||||
# is <core_name>_xmdf
|
||||
namespace eval ::xfft_v7_1_xmdf {
|
||||
# Use this to define any statics
|
||||
}
|
||||
|
||||
# Function called by client to rebuild the params and port arrays
|
||||
# Optional when the use context does not require the param or ports
|
||||
# arrays to be available.
|
||||
proc ::xfft_v7_1_xmdf::xmdfInit { instance } {
|
||||
# Variable containg name of library into which module is compiled
|
||||
# Recommendation: <module_name>
|
||||
# Required
|
||||
utilities_xmdf::xmdfSetData $instance Module Attributes Name xfft_v7_1
|
||||
}
|
||||
# ::xfft_v7_1_xmdf::xmdfInit
|
||||
|
||||
# Function called by client to fill in all the xmdf* data variables
|
||||
# based on the current settings of the parameters
|
||||
proc ::xfft_v7_1_xmdf::xmdfApplyParams { instance } {
|
||||
|
||||
set fcount 0
|
||||
# Array containing libraries that are assumed to exist
|
||||
# Examples include unisim and xilinxcorelib
|
||||
# Optional
|
||||
# In this example, we assume that the unisim library will
|
||||
# be magically
|
||||
# available to the simulation and synthesis tool
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path xfft_v7_1.asy
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path xfft_v7_1.ngc
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path xfft_v7_1.sym
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path xfft_v7_1.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path xfft_v7_1.veo
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path xfft_v7_1.vhd
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path xfft_v7_1.vho
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path xfft_v7_1.xco
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path xfft_v7_1_xmdf.tcl
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module xfft_v7_1
|
||||
incr fcount
|
||||
|
||||
}
|
||||
|
||||
# ::gen_comp_name_xmdf::xmdfApplyParams
|
||||
Loading…
x
Reference in New Issue
Block a user