mirror of
https://github.com/jhshi/openofdm.git
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80 lines
5.0 KiB
XML
80 lines
5.0 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<header>
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<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="deinter_lut.ngc" xil_pn:type="FILE_NGC">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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</file>
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<file xil_pn:name="deinter_lut.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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<association xil_pn:name="PostMapSimulation"/>
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<association xil_pn:name="PostRouteSimulation"/>
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<association xil_pn:name="PostTranslateSimulation"/>
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</file>
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<file xil_pn:name="deinter_lut.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation"/>
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<association xil_pn:name="Implementation"/>
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<association xil_pn:name="PostMapSimulation"/>
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<association xil_pn:name="PostRouteSimulation"/>
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<association xil_pn:name="PostTranslateSimulation"/>
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</file>
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</files>
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<properties>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device" xil_pn:value="xc3sd3400a" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="Spartan-3A DSP" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|deinter_lut|deinter_lut_a" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="deinter_lut.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/deinter_lut" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Package" xil_pn:value="fg676" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_DesignName" xil_pn:value="deinter_lut" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3adsp" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-11-07T11:54:11" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3A40266961F7E507020FF3A42CC058B1" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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</properties>
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<bindings/>
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<libraries/>
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<autoManagedFiles>
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<!-- The following files are identified by `include statements in verilog -->
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<!-- source files and are automatically managed by Project Navigator. -->
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<!-- -->
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<!-- Do not hand-edit this section, as it will be overwritten when the -->
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<!-- project is analyzed based on files automatically identified as -->
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<!-- include files. -->
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</autoManagedFiles>
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</project>
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