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49 lines
3.0 KiB
Verilog
49 lines
3.0 KiB
Verilog
/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used *
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* solely for design, simulation, implementation and creation of *
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* design files limited to Xilinx devices or technologies. Use *
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* with non-Xilinx devices or technologies is expressly prohibited *
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* and immediately terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
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* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
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* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
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* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
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* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
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* FOR A PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support *
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* appliances, devices, or systems. Use in such applications are *
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* expressly prohibited. *
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* *
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* (c) Copyright 1995-2009 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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rot_lut YourInstanceName (
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.clka(clka),
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.addra(addra), // Bus [8 : 0]
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.douta(douta), // Bus [31 : 0]
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.clkb(clkb),
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.addrb(addrb), // Bus [8 : 0]
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.doutb(doutb)); // Bus [31 : 0]
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file rot_lut.v when simulating
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// the core, rot_lut. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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