openofdm/verilog/coregen/complex_multiplier_readme.txt
2017-04-14 16:29:33 -04:00

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The following files were generated for 'complex_multiplier' in directory
/home/jinghaos/projects/jammer/uhd/fpga-src/usrp2/top/N2x0/build-N210R4-custom/ipcore_dir/
complex_multiplier.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
complex_multiplier.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
complex_multiplier.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
complex_multiplier.sym:
Please see the core data sheet.
complex_multiplier.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
complex_multiplier.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
complex_multiplier.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
complex_multiplier.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
complex_multiplier.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
complex_multiplier.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
complex_multiplier_readme.txt:
Text file indicating the files generated and how they are used.
complex_multiplier_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
complex_multiplier_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.