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66 lines
1.9 KiB
Plaintext
66 lines
1.9 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 12.2
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# Date: Tue Aug 23 02:00:18 2016
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc3sd3400a
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SET devicefamily = spartan3adsp
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SET flowvendor = Foundation_ISE
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = fg676
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -5
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SET verilogsim = true
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT Fast_Fourier_Transform family Xilinx,_Inc. 7.1
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# END Select
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# BEGIN Parameters
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CSET butterfly_type=use_luts
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CSET ce=false
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CSET channels=1
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CSET complex_mult_type=use_mults_resources
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CSET component_name=xfft_v7_1
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CSET cyclic_prefix_insertion=false
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CSET data_format=fixed_point
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CSET implementation_options=pipelined_streaming_io
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CSET input_data_offset=no_offset
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CSET input_width=16
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CSET memory_options_data=block_ram
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CSET memory_options_hybrid=false
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CSET memory_options_phase_factors=block_ram
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CSET memory_options_reorder=block_ram
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CSET number_of_stages_using_block_ram_for_data_and_phase_factors=0
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CSET output_ordering=natural_order
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CSET ovflo=false
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CSET phase_factor_width=16
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CSET rounding_modes=truncation
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CSET run_time_configurable_transform_length=false
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CSET scaling_options=unscaled
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CSET sclr=false
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CSET target_clock_frequency=100
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CSET target_data_throughput=50
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CSET transform_length=64
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# END Parameters
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GENERATE
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# CRC: 2da176bc
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