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Add force ht smoothing option:

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> 1. Leave the module always enabled, so the slv_reg1 is free
> 2. Use the slv_reg1 to force ht smoothing
> 3. By default, the smoothing option of the receiver is still controlled by the received ht packet
This commit is contained in:
Xianjun Jiao 2022-01-28 12:15:49 +01:00
parent 23e61e6a29
commit 030cdb34ca
2 changed files with 4 additions and 2 deletions
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3
verilog/dot11.v
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@ -20,6 +20,7 @@ module dot11 (
input [31:0] sample_in,
input sample_in_strobe,
input soft_decoding,
input wire force_ht_smoothing,
// OUTPUT: bytes and FCS status
output reg demod_is_ongoing,
@ -374,7 +375,7 @@ equalizer equalizer_inst (
.sample_in_strobe(sync_long_out_strobe && !(state==S_HT_SIGNAL && num_ofdm_symbol==6)),
.ht_next(ht_next),
.pkt_ht(pkt_ht),
.ht_smoothing(ht_smoothing),
.ht_smoothing(ht_smoothing|force_ht_smoothing),
.phase_in_i(eq_phase_in_i),
.phase_in_q(eq_phase_in_q),

3
verilog/openofdm_rx.v
View File

@ -107,7 +107,7 @@
dot11 # (
) dot11_i (
.clock(s00_axi_aclk),
.enable( ~slv_reg1[0] ),
.enable( 1 ),
//.reset ( (~s00_axi_aresetn)|slv_reg0[0]|openofdm_core_rst ),
.reset ( (~s00_axi_aresetn)|slv_reg0[0] ),
@ -119,6 +119,7 @@
.sample_in(sample_in),
.sample_in_strobe(sample_in_strobe),
.soft_decoding(slv_reg4[0]),
.force_ht_smoothing(slv_reg1[0]),
// OUTPUT: bytes and FCS status
.demod_is_ongoing(demod_is_ongoing),