mirror of
https://github.com/jhshi/openofdm.git
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Merge pull request #19 from open-sdr/dot11zynq
Improvement for openwifi-1.3.0-wilsele
This commit is contained in:
Jinghao Shi
GitHub
commit
0ab83ce223
11
get_git_rev.sh
Executable file
11
get_git_rev.sh
Executable file
@ -0,0 +1,11 @@
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#!/bin/bash
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# xianjun.jiao@imec.be
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if git log -1 > /dev/null 2>&1; then
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GIT_REV=$(git log -1 --pretty=%h)
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else
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GIT_REV=ffffffff
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fi
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echo $GIT_REV
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1541
openofdm_rx.tcl
1541
openofdm_rx.tcl
File diff suppressed because it is too large
Load Diff
@ -13,6 +13,13 @@
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#
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#*****************************************************************************************
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# -----------generate openofdm_rx_git_rev.v---------------
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set fd [open "./verilog/openofdm_rx_git_rev.v" w]
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set HASHCODE [exec ./get_git_rev.sh]
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puts $fd "`define OPENOFDM_RX_GIT_REV (32'h$HASHCODE)"
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close $fd
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# ----end of generate openofdm_rx_git_rev.v---------------
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# Set the reference directory for source file relative paths (by default the value is script directory path)
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set origin_dir [file dirname [info script]]
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@ -23,6 +30,7 @@ if { [info exists ::origin_dir_loc] } {
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# Set the project name
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set project_name "openofdm_rx_side_ch_sim_ultra_scale"
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exec rm -rf $project_name
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# Use project name variable, if specified in the tcl shell
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if { [info exists ::user_project_name] } {
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File diff suppressed because it is too large
Load Diff
5461
testing_inputs/conducted/fake-demod-0.txt
Normal file
5461
testing_inputs/conducted/fake-demod-0.txt
Normal file
File diff suppressed because it is too large
Load Diff
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|
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4219 4219
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|
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|
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-1160 13095
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|
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4219 4219
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-12149 215
|
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-1236 -7203
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|
||||
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|
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13095 -1160
|
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-1236 -7203
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-12149 215
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4219 4219
|
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215 -12149
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|
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-1160 13095
|
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0 8439
|
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-1160 13095
|
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-7203 -1236
|
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215 -12149
|
||||
4219 4219
|
||||
-12149 215
|
||||
-1236 -7203
|
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13095 -1160
|
||||
8439 0
|
||||
13095 -1160
|
||||
-1236 -7203
|
||||
-12149 215
|
||||
4219 4219
|
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215 -12149
|
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-7203 -1236
|
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-1160 13095
|
||||
0 8439
|
||||
-1160 13095
|
||||
-7203 -1236
|
||||
215 -12149
|
||||
4219 4219
|
||||
-12149 215
|
||||
-1236 -7203
|
||||
13095 -1160
|
||||
8439 0
|
||||
13095 -1160
|
||||
-1236 -7203
|
||||
-12149 215
|
||||
4219 4219
|
||||
215 -12149
|
||||
-7203 -1236
|
||||
-1160 13095
|
||||
0 8439
|
||||
-1160 13095
|
||||
-7203 -1236
|
||||
215 -12149
|
||||
4219 4219
|
||||
-12149 215
|
||||
-1236 -7203
|
||||
13095 -1160
|
||||
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|
||||
13095 -1160
|
||||
-1236 -7203
|
||||
-12149 215
|
||||
4219 4219
|
||||
215 -12149
|
||||
-7203 -1236
|
||||
-1160 13095
|
||||
0 8439
|
||||
-1160 13095
|
||||
-7203 -1236
|
||||
215 -12149
|
||||
4219 4219
|
||||
-12149 215
|
||||
-1236 -7203
|
||||
13095 -1160
|
||||
8439 0
|
||||
13095 -1160
|
||||
-1236 -7203
|
||||
-12149 215
|
||||
4219 4219
|
||||
215 -12149
|
||||
-7203 -1236
|
||||
-1160 13095
|
||||
0 8439
|
||||
-1160 13095
|
||||
-7203 -1236
|
||||
215 -12149
|
||||
4219 4219
|
||||
-12149 215
|
||||
-1236 -7203
|
||||
13095 -1160
|
||||
8439 0
|
||||
13095 -1160
|
||||
-1236 -7203
|
||||
-12149 215
|
||||
4219 4219
|
||||
215 -12149
|
||||
-7203 -1236
|
||||
-1160 13095
|
||||
0 8439
|
||||
-1160 13095
|
||||
-7203 -1236
|
||||
215 -12149
|
||||
4219 4219
|
||||
-12149 215
|
||||
-1236 -7203
|
||||
13095 -1160
|
||||
8439 0
|
||||
13095 -1160
|
||||
-1236 -7203
|
||||
-12149 215
|
||||
4219 4219
|
||||
215 -12149
|
||||
-7203 -1236
|
||||
-1160 13095
|
||||
0 8439
|
||||
-1160 13095
|
||||
-7203 -1236
|
||||
215 -12149
|
||||
4219 4219
|
||||
-12149 215
|
||||
-1236 -7203
|
||||
13095 -1160
|
||||
8439 0
|
||||
13095 -1160
|
||||
-1236 -7203
|
||||
-12149 215
|
||||
4219 4219
|
||||
215 -12149
|
||||
-7203 -1236
|
||||
-1160 13095
|
||||
0 8439
|
||||
-1160 13095
|
||||
-7203 -1236
|
||||
215 -12149
|
||||
-14332 0
|
||||
1127 -8953
|
||||
8413 -9711
|
||||
-8429 -10560
|
||||
-257 -4933
|
||||
6886 6792
|
||||
-11679 1881
|
||||
-11180 1520
|
||||
-3214 13841
|
||||
-5178 2000
|
||||
-5532 -7456
|
||||
6380 -1295
|
||||
7542 -8472
|
||||
-12040 -5983
|
||||
-5247 -3605
|
||||
3386 -9021
|
||||
5733 5733
|
||||
10937 376
|
||||
-2062 -14737
|
||||
5382 1370
|
||||
2245 5369
|
||||
-12549 4346
|
||||
91 10549
|
||||
4893 -374
|
||||
8947 2375
|
||||
-3515 9739
|
||||
-10561 5062
|
||||
5487 8045
|
||||
1937 -2558
|
||||
8882 -7595
|
||||
3646 10196
|
||||
-470 11037
|
||||
14332 0
|
||||
-470 -11037
|
||||
3646 -10196
|
||||
8882 7595
|
||||
1937 2558
|
||||
5487 -8045
|
||||
-10561 -5062
|
||||
-3515 -9739
|
||||
8947 -2375
|
||||
4893 374
|
||||
91 -10549
|
||||
-12549 -4346
|
||||
2245 -5369
|
||||
5382 -1370
|
||||
-2062 14737
|
||||
10937 -376
|
||||
5733 -5733
|
||||
3386 9021
|
||||
-5247 3605
|
||||
-12040 5983
|
||||
7542 8472
|
||||
6380 1295
|
||||
-5532 7456
|
||||
-5178 -2000
|
||||
-3214 -13841
|
||||
-11180 -1520
|
||||
-11679 -1881
|
||||
6886 -6792
|
||||
-257 4933
|
||||
-8429 10560
|
||||
8413 9711
|
||||
1127 8953
|
||||
-14332 0
|
||||
1127 -8953
|
||||
8413 -9711
|
||||
-8429 -10560
|
||||
-257 -4933
|
||||
6886 6792
|
||||
-11679 1881
|
||||
-11180 1520
|
||||
-3214 13841
|
||||
-5178 2000
|
||||
-5532 -7456
|
||||
6380 -1295
|
||||
7542 -8472
|
||||
-12040 -5983
|
||||
-5247 -3605
|
||||
3386 -9021
|
||||
5733 5733
|
||||
10937 376
|
||||
-2062 -14737
|
||||
5382 1370
|
||||
2245 5369
|
||||
-12549 4346
|
||||
91 10549
|
||||
4893 -374
|
||||
8947 2375
|
||||
-3515 9739
|
||||
-10561 5062
|
||||
5487 8045
|
||||
1937 -2558
|
||||
8882 -7595
|
||||
3646 10196
|
||||
-470 11037
|
||||
14332 0
|
||||
-470 -11037
|
||||
3646 -10196
|
||||
8882 7595
|
||||
1937 2558
|
||||
5487 -8045
|
||||
-10561 -5062
|
||||
-3515 -9739
|
||||
8947 -2375
|
||||
4893 374
|
||||
91 -10549
|
||||
-12549 -4346
|
||||
2245 -5369
|
||||
5382 -1370
|
||||
-2062 14737
|
||||
10937 -376
|
||||
5733 -5733
|
||||
3386 9021
|
||||
-5247 3605
|
||||
-12040 5983
|
||||
7542 8472
|
||||
6380 1295
|
||||
-5532 7456
|
||||
-5178 -2000
|
||||
-3214 -13841
|
||||
-11180 -1520
|
||||
-11679 -1881
|
||||
6886 -6792
|
||||
-257 4933
|
||||
-8429 10560
|
||||
8413 9711
|
||||
1127 8953
|
||||
-14332 0
|
||||
1127 -8953
|
||||
8413 -9711
|
||||
-8429 -10560
|
||||
-257 -4933
|
||||
6886 6792
|
||||
-11679 1881
|
||||
-11180 1520
|
||||
-3214 13841
|
||||
-5178 2000
|
||||
-5532 -7456
|
||||
6380 -1295
|
||||
7542 -8472
|
||||
-12040 -5983
|
||||
-5247 -3605
|
||||
3386 -9021
|
||||
5733 5733
|
||||
10937 376
|
||||
-2062 -14737
|
||||
5382 1370
|
||||
2245 5369
|
||||
-12549 4346
|
||||
91 10549
|
||||
4893 -374
|
||||
8947 2375
|
||||
-3515 9739
|
||||
-10561 5062
|
||||
5487 8045
|
||||
1937 -2558
|
||||
8882 -7595
|
||||
3646 10196
|
||||
-470 11037
|
||||
-8599 14332
|
||||
-594 4430
|
||||
1020 -4743
|
||||
-10572 -6979
|
||||
3033 -891
|
||||
9081 6117
|
||||
6090 8418
|
||||
9227 2119
|
||||
4054 2027
|
||||
1097 8196
|
||||
-11000 -6451
|
||||
-5106 -4406
|
||||
10190 1533
|
||||
-3248 -2924
|
||||
8919 7283
|
||||
11487 2642
|
||||
-8599 0
|
||||
11487 -2642
|
||||
8919 -7283
|
||||
-3248 2924
|
||||
10190 -1533
|
||||
-5106 4406
|
||||
-11000 6451
|
||||
1097 -8196
|
||||
4054 -2027
|
||||
9227 -2119
|
||||
6090 -8418
|
||||
9081 -6117
|
||||
3033 891
|
||||
-10572 6979
|
||||
1020 4743
|
||||
-594 -4430
|
||||
-8599 -14332
|
||||
8 8675
|
||||
3943 13991
|
||||
4778 -16384
|
||||
-1354 -10575
|
||||
1433 -2610
|
||||
2643 3521
|
||||
-14571 11761
|
||||
-4054 -2027
|
||||
7967 2837
|
||||
-5841 6923
|
||||
-2922 3320
|
||||
-403 9933
|
||||
-9659 14115
|
||||
-5774 13431
|
||||
1594 899
|
||||
2866 0
|
||||
1594 -899
|
||||
-5774 -13431
|
||||
-9659 -14115
|
||||
-403 -9933
|
||||
-2922 -3320
|
||||
-5841 -6923
|
||||
7967 -2837
|
||||
-4054 2027
|
||||
-14571 -11761
|
||||
2643 -3521
|
||||
1433 2610
|
||||
-1354 10575
|
||||
4778 16384
|
||||
3943 -13991
|
||||
8 -8675
|
||||
-8599 14332
|
||||
-594 4430
|
||||
1020 -4743
|
||||
-10572 -6979
|
||||
3033 -891
|
||||
9081 6117
|
||||
6090 8418
|
||||
9227 2119
|
||||
4054 2027
|
||||
1097 8196
|
||||
-11000 -6451
|
||||
-5106 -4406
|
||||
10190 1533
|
||||
-3248 -2924
|
||||
8919 7283
|
||||
11487 2642
|
||||
2654 5078
|
||||
551 4494
|
||||
-14593 4592
|
||||
-6605 4703
|
||||
-5036 -1978
|
||||
-6020 278
|
||||
1514 3786
|
||||
1556 -9782
|
||||
-2030 -7397
|
||||
7435 7704
|
||||
9396 -3256
|
||||
-3213 -10864
|
||||
-7190 -1529
|
||||
3299 4499
|
||||
12556 3134
|
||||
8515 -8677
|
||||
7290 -4865
|
||||
-2543 11911
|
||||
-15942 6673
|
||||
-5979 -1135
|
||||
-5320 -408
|
||||
-11715 -4372
|
||||
-3411 -1385
|
||||
6135 5004
|
||||
3581 3903
|
||||
-8770 -528
|
||||
-2340 -4665
|
||||
4603 -4229
|
||||
-1779 -6503
|
||||
-1961 -12399
|
||||
-4804 -8514
|
||||
-6574 -5216
|
||||
-6192 -10386
|
||||
2556 -2677
|
||||
8989 12436
|
||||
4968 5590
|
||||
9674 -2294
|
||||
-2874 3976
|
||||
-12261 1394
|
||||
-5617 8455
|
||||
-8586 9167
|
||||
3308 -13013
|
||||
9685 -692
|
||||
5221 11335
|
||||
1212 -6066
|
||||
-4988 -605
|
||||
4889 2461
|
||||
11634 -410
|
||||
13941 8404
|
||||
-3648 6317
|
||||
-13572 4214
|
||||
13567 230
|
||||
2452 1141
|
||||
-2834 9346
|
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5340
testing_inputs/simulated/ag_54M_len1537_pre100_post200_openwifi.txt
Normal file
5340
testing_inputs/simulated/ag_54M_len1537_pre100_post200_openwifi.txt
Normal file
File diff suppressed because it is too large
Load Diff
12620
testing_inputs/simulated/ag_54M_len4000_pre100_post200_openwifi.txt
Normal file
12620
testing_inputs/simulated/ag_54M_len4000_pre100_post200_openwifi.txt
Normal file
File diff suppressed because it is too large
Load Diff
1180
testing_inputs/simulated/ag_6M_len14_pre100_post200_openwifi.txt
Normal file
1180
testing_inputs/simulated/ag_6M_len14_pre100_post200_openwifi.txt
Normal file
File diff suppressed because it is too large
Load Diff
41820
testing_inputs/simulated/ag_6M_len1537_pre100_post200_openwifi.txt
Normal file
41820
testing_inputs/simulated/ag_6M_len1537_pre100_post200_openwifi.txt
Normal file
File diff suppressed because it is too large
Load Diff
107500
testing_inputs/simulated/ag_6M_len4000_pre100_post200_openwifi.txt
Normal file
107500
testing_inputs/simulated/ag_6M_len4000_pre100_post200_openwifi.txt
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,258 +0,0 @@
|
||||
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011110101
|
||||
011110111
|
||||
011111000
|
||||
011111010
|
||||
011111100
|
||||
011111101
|
||||
011111111
|
||||
100000000
|
||||
100000010
|
||||
100000011
|
||||
100000101
|
||||
100000110
|
||||
100001000
|
||||
100001001
|
||||
100001011
|
||||
100001100
|
||||
100001110
|
||||
100001111
|
||||
100010001
|
||||
100010010
|
||||
100010100
|
||||
100010101
|
||||
100010111
|
||||
100011000
|
||||
100011010
|
||||
100011011
|
||||
100011101
|
||||
100011110
|
||||
100011111
|
||||
100100001
|
||||
100100010
|
||||
100100100
|
||||
100100101
|
||||
100100111
|
||||
100101000
|
||||
100101001
|
||||
100101011
|
||||
100101100
|
||||
100101110
|
||||
100101111
|
||||
100110000
|
||||
100110010
|
||||
100110011
|
||||
100110100
|
||||
100110110
|
||||
100110111
|
||||
100111000
|
||||
100111010
|
||||
100111011
|
||||
100111100
|
||||
100111110
|
||||
100111111
|
||||
101000000
|
||||
101000010
|
||||
101000011
|
||||
101000100
|
||||
101000110
|
||||
101000111
|
||||
101001000
|
||||
101001001
|
||||
101001011
|
||||
101001100
|
||||
101001101
|
||||
101001111
|
||||
101010000
|
||||
101010001
|
||||
101010010
|
||||
101010100
|
||||
101010101
|
||||
101010110
|
||||
101010111
|
||||
101011000
|
||||
101011010
|
||||
101011011
|
||||
101011100
|
||||
101011101
|
||||
101011111
|
||||
101100000
|
||||
101100001
|
||||
101100010
|
||||
101100011
|
||||
101100100
|
||||
101100110
|
||||
101100111
|
||||
101101000
|
||||
101101001
|
||||
101101010
|
||||
101101011
|
||||
101101101
|
||||
101101110
|
||||
101101111
|
||||
101110000
|
||||
101110001
|
||||
101110010
|
||||
101110011
|
||||
101110101
|
||||
101110110
|
||||
101110111
|
||||
101111000
|
||||
101111001
|
||||
101111010
|
||||
101111011
|
||||
101111100
|
||||
101111101
|
||||
101111110
|
||||
101111111
|
||||
110000001
|
||||
110000010
|
||||
110000011
|
||||
110000100
|
||||
110000101
|
||||
110000110
|
||||
110000111
|
||||
110001000
|
||||
110001001
|
||||
110001010
|
||||
110001011
|
||||
110001100
|
||||
110001101
|
||||
110001110
|
||||
110001111
|
||||
110010000
|
||||
110010001
|
||||
@ -21,6 +21,7 @@ module dot11 (
|
||||
input sample_in_strobe,
|
||||
input soft_decoding,
|
||||
input wire force_ht_smoothing,
|
||||
input wire disable_all_smoothing,
|
||||
|
||||
// OUTPUT: bytes and FCS status
|
||||
output reg demod_is_ongoing,
|
||||
@ -376,6 +377,7 @@ equalizer equalizer_inst (
|
||||
.ht_next(ht_next),
|
||||
.pkt_ht(pkt_ht),
|
||||
.ht_smoothing(ht_smoothing|force_ht_smoothing),
|
||||
.disable_all_smoothing(disable_all_smoothing),
|
||||
|
||||
.phase_in_i(eq_phase_in_i),
|
||||
.phase_in_q(eq_phase_in_q),
|
||||
|
||||
@ -49,6 +49,7 @@ reg signal_done;
|
||||
|
||||
wire [3:0] dot11_state;
|
||||
|
||||
wire pkt_header_valid;
|
||||
wire pkt_header_valid_strobe;
|
||||
wire [7:0] byte_out;
|
||||
wire byte_out_strobe;
|
||||
@ -64,6 +65,10 @@ reg [7:0] set_addr;
|
||||
reg [31:0] set_data;
|
||||
|
||||
wire fcs_out_strobe, fcs_ok;
|
||||
wire demod_is_ongoing;
|
||||
wire receiver_rst;
|
||||
|
||||
wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
|
||||
|
||||
integer addr;
|
||||
|
||||
@ -104,10 +109,31 @@ integer file_i, file_q, file_rssi_half_db, iq_sample_file;
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_6.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_52mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/dot11n_19.5mbps_openwifi.txt"
|
||||
`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_58.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_58.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_65mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/ack-ok-openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/fake-demod-0.txt"
|
||||
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi1_aggr0_len14_pre100_post200_openwifi.txt"
|
||||
`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi1_aggr0_len1537_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi1_aggr0_len4000_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi0_aggr0_len14_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi0_aggr0_len1537_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs7_gi0_aggr0_len4000_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi1_aggr0_len14_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi1_aggr0_len1537_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi1_aggr0_len4000_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi0_aggr0_len14_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi0_aggr0_len1537_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ht_mcs0_gi0_aggr0_len4000_pre100_post200_openwifi.txt"
|
||||
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_54M_len14_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_54M_len1537_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_54M_len4000_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_6M_len14_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_6M_len1537_pre100_post200_openwifi.txt"
|
||||
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/ag_6M_len4000_pre100_post200_openwifi.txt"
|
||||
|
||||
`define NUM_SAMPLE 118560
|
||||
|
||||
@ -308,10 +334,28 @@ always @(posedge clock) begin
|
||||
end
|
||||
end
|
||||
|
||||
signal_watchdog signal_watchdog_inst (
|
||||
.clk(clock),
|
||||
.rstn(~reset),
|
||||
.enable(~demod_is_ongoing),
|
||||
|
||||
.i_data(sample_in[31:16]),
|
||||
.q_data(sample_in[15:0]),
|
||||
.iq_valid(sample_in_strobe),
|
||||
|
||||
.signal_len(pkt_len),
|
||||
.sig_valid(sig_valid),
|
||||
|
||||
.max_signal_len_th(4095),
|
||||
.dc_running_sum_th(64),
|
||||
|
||||
.receiver_rst(receiver_rst)
|
||||
);
|
||||
|
||||
dot11 dot11_inst (
|
||||
.clock(clock),
|
||||
.enable(enable),
|
||||
.reset(reset),
|
||||
.reset(reset|receiver_rst),
|
||||
|
||||
//.set_stb(set_stb),
|
||||
//.set_addr(set_addr),
|
||||
@ -325,6 +369,8 @@ dot11 dot11_inst (
|
||||
.sample_in_strobe(sample_in_strobe),
|
||||
.soft_decoding(1'b1),
|
||||
|
||||
.demod_is_ongoing(demod_is_ongoing),
|
||||
.pkt_header_valid(pkt_header_valid),
|
||||
.pkt_header_valid_strobe(pkt_header_valid_strobe),
|
||||
.pkt_len(pkt_len),
|
||||
.pkt_len_total(pkt_len_total),
|
||||
|
||||
@ -11,6 +11,7 @@ module equalizer
|
||||
input ht_next,
|
||||
input pkt_ht,
|
||||
input ht_smoothing,
|
||||
input wire disable_all_smoothing,
|
||||
|
||||
output [31:0] phase_in_i,
|
||||
output [31:0] phase_in_q,
|
||||
@ -548,8 +549,7 @@ always @(posedge clock) begin
|
||||
lts_raddr <= 62;
|
||||
lts_in_stb <= 0;
|
||||
lts_div_in_stb <= 0;
|
||||
// Always smooth legacy channel
|
||||
state <= S_SMOOTH_CH_DC;
|
||||
state <= (disable_all_smoothing?S_GET_POLARITY:S_SMOOTH_CH_DC);
|
||||
end else begin
|
||||
lts_waddr <= lts_waddr + 1;
|
||||
end
|
||||
@ -848,7 +848,7 @@ always @(posedge clock) begin
|
||||
lts_in_stb <= 0;
|
||||
lts_div_in_stb <= 0;
|
||||
// Depending on smoothing bit in HT-SIG, smooth the channel
|
||||
if(ht_smoothing) begin
|
||||
if(ht_smoothing==1 && disable_all_smoothing==0) begin
|
||||
state <= S_SMOOTH_CH_DC;
|
||||
end else begin
|
||||
state <= S_GET_POLARITY;
|
||||
|
||||
@ -39,8 +39,8 @@ reg [1:0] conv_erase, conv_erase_dly;
|
||||
wire [15:0] input_i = sample_in[31:16];
|
||||
wire [15:0] input_q = sample_in[15:0];
|
||||
|
||||
wire vit_ce = reset | (enable & conv_in_stb) | conv_in_stb_dly;
|
||||
//wire vit_ce = 1'b1 ;
|
||||
// wire vit_ce = reset | (enable & conv_in_stb) | conv_in_stb_dly; //Seems new viter decoder IP core does not need this complicated CE signal
|
||||
wire vit_ce = 1'b1 ; //Need to be 1 to avoid the viterbi decoder freezing issue on adrv9364z7020 (demod_is_ongoing always high. dot11 stuck at state 3)
|
||||
wire vit_clr = reset;
|
||||
reg vit_clr_dly;
|
||||
wire vit_rdy;
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
`include "openofdm_rx_git_rev.v"
|
||||
|
||||
module openofdm_rx #
|
||||
(
|
||||
@ -101,15 +103,38 @@
|
||||
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg28;
|
||||
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg29;
|
||||
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg30;
|
||||
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31;
|
||||
*/
|
||||
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31;
|
||||
|
||||
assign slv_reg31 = `OPENOFDM_RX_GIT_REV;
|
||||
|
||||
wire sig_valid = (pkt_header_valid_strobe&pkt_header_valid);
|
||||
wire receiver_rst;
|
||||
|
||||
signal_watchdog signal_watchdog_inst (
|
||||
.clk(s00_axi_aclk),
|
||||
.rstn(s00_axi_aresetn),
|
||||
.enable(~demod_is_ongoing),
|
||||
|
||||
.i_data(sample_in[31:16]),
|
||||
.q_data(sample_in[15:0]),
|
||||
.iq_valid(sample_in_strobe),
|
||||
|
||||
.signal_len(pkt_len),
|
||||
.sig_valid(sig_valid),
|
||||
|
||||
.max_signal_len_th(slv_reg4[31:16]),
|
||||
.dc_running_sum_th(slv_reg2[23:16]),
|
||||
|
||||
.receiver_rst(receiver_rst)
|
||||
);
|
||||
|
||||
dot11 # (
|
||||
) dot11_i (
|
||||
.clock(s00_axi_aclk),
|
||||
.enable( 1 ),
|
||||
//.reset ( (~s00_axi_aresetn)|slv_reg0[0]|openofdm_core_rst ),
|
||||
.reset ( (~s00_axi_aresetn)|slv_reg0[0] ),
|
||||
.reset ( (~s00_axi_aresetn)|slv_reg0[0]|receiver_rst ),
|
||||
|
||||
.power_thres(slv_reg2[10:0]),
|
||||
.min_plateau(slv_reg3),
|
||||
@ -120,6 +145,7 @@
|
||||
.sample_in_strobe(sample_in_strobe),
|
||||
.soft_decoding(slv_reg4[0]),
|
||||
.force_ht_smoothing(slv_reg1[0]),
|
||||
.disable_all_smoothing(slv_reg1[4]),
|
||||
|
||||
// OUTPUT: bytes and FCS status
|
||||
.demod_is_ongoing(demod_is_ongoing),
|
||||
@ -258,7 +284,7 @@
|
||||
.SLV_REG17(slv_reg17),
|
||||
.SLV_REG18(slv_reg18),
|
||||
.SLV_REG19(slv_reg19),*/
|
||||
.SLV_REG20(slv_reg20)/*
|
||||
.SLV_REG20(slv_reg20),/*
|
||||
.SLV_REG21(slv_reg21),
|
||||
.SLV_REG22(slv_reg22),
|
||||
.SLV_REG23(slv_reg23),
|
||||
@ -268,8 +294,8 @@
|
||||
.SLV_REG27(slv_reg27),
|
||||
.SLV_REG28(slv_reg28),
|
||||
.SLV_REG29(slv_reg29),
|
||||
.SLV_REG30(slv_reg30),
|
||||
.SLV_REG31(slv_reg31)*/
|
||||
.SLV_REG30(slv_reg30),*/
|
||||
.SLV_REG31(slv_reg31)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
// based on Xilinx module template
|
||||
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
@ -45,8 +47,8 @@
|
||||
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG27,
|
||||
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG28,
|
||||
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG29,
|
||||
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG30,
|
||||
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG31,*/
|
||||
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG30,*/
|
||||
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG31,
|
||||
// User ports ends
|
||||
// Do not modify the ports beyond this line
|
||||
|
||||
@ -165,8 +167,8 @@
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;*/
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;*/
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;
|
||||
wire slv_reg_rden;
|
||||
wire slv_reg_wren;
|
||||
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
|
||||
@ -712,8 +714,8 @@
|
||||
5'h1B : reg_data_out <= slv_reg27;
|
||||
5'h1C : reg_data_out <= slv_reg28;
|
||||
5'h1D : reg_data_out <= slv_reg29;
|
||||
5'h1E : reg_data_out <= slv_reg30;
|
||||
5'h1F : reg_data_out <= slv_reg31;*/
|
||||
5'h1E : reg_data_out <= slv_reg30;*/
|
||||
5'h1F : reg_data_out <= slv_reg31;
|
||||
default : reg_data_out <= 0;
|
||||
endcase
|
||||
end
|
||||
@ -752,8 +754,8 @@
|
||||
slv_reg27 <= 32'h0;
|
||||
slv_reg28 <= 32'h0;
|
||||
slv_reg29 <= 32'h0;
|
||||
slv_reg30 <= 32'h0;
|
||||
slv_reg31 <= 32'h0;*/
|
||||
slv_reg30 <= 32'h0;*/
|
||||
slv_reg31 <= 32'h0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
@ -767,8 +769,8 @@
|
||||
slv_reg27 <= SLV_REG27;
|
||||
slv_reg28 <= SLV_REG28;
|
||||
slv_reg29 <= SLV_REG29;
|
||||
slv_reg30 <= SLV_REG30;
|
||||
slv_reg31 <= SLV_REG31;*/
|
||||
slv_reg30 <= SLV_REG30;*/
|
||||
slv_reg31 <= SLV_REG31;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
93
verilog/running_sum.v
Normal file
93
verilog/running_sum.v
Normal file
@ -0,0 +1,93 @@
|
||||
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
|
||||
|
||||
module running_sum
|
||||
#(
|
||||
parameter DATA_WIDTH = 16,
|
||||
parameter LOG2_SUM_LEN = 6
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rstn,
|
||||
|
||||
input signed [DATA_WIDTH-1:0] data_in,
|
||||
input data_in_valid,
|
||||
|
||||
output reg signed [(DATA_WIDTH + LOG2_SUM_LEN-1):0] running_sum_result,
|
||||
output reg data_out_valid
|
||||
);
|
||||
|
||||
localparam FIFO_SIZE = 1<<LOG2_SUM_LEN;
|
||||
localparam TOTAL_WIDTH = DATA_WIDTH + LOG2_SUM_LEN;
|
||||
|
||||
wire signed [DATA_WIDTH-1:0] data_in_old;
|
||||
|
||||
wire signed [TOTAL_WIDTH-1:0] ext_data_in_old = {{LOG2_SUM_LEN{data_in_old[DATA_WIDTH-1]}}, data_in_old};
|
||||
wire signed [TOTAL_WIDTH-1:0] ext_data_in = {{LOG2_SUM_LEN{data_in[DATA_WIDTH-1]}}, data_in };
|
||||
|
||||
reg data_in_valid_reg;
|
||||
reg rd_en, rd_en_start;
|
||||
wire [LOG2_SUM_LEN:0] wr_data_count;
|
||||
|
||||
xpm_fifo_sync #(
|
||||
.DOUT_RESET_VALUE("0"), // String
|
||||
.ECC_MODE("no_ecc"), // String
|
||||
.FIFO_MEMORY_TYPE("auto"), // String
|
||||
.FIFO_READ_LATENCY(0), // DECIMAL
|
||||
.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL
|
||||
.FULL_RESET_VALUE(0), // DECIMAL
|
||||
.PROG_EMPTY_THRESH(10), // DECIMAL
|
||||
.PROG_FULL_THRESH(10), // DECIMAL
|
||||
.RD_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1), // DECIMAL
|
||||
.READ_DATA_WIDTH(DATA_WIDTH), // DECIMAL
|
||||
.READ_MODE("fwft"), // String
|
||||
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
|
||||
.WAKEUP_TIME(0), // DECIMAL
|
||||
.WRITE_DATA_WIDTH(DATA_WIDTH), // DECIMAL
|
||||
.WR_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1) // DECIMAL
|
||||
) fifo_1clk_for_mv_avg_i (
|
||||
.almost_empty(),
|
||||
.almost_full(),
|
||||
.data_valid(),
|
||||
.dbiterr(),
|
||||
.dout(data_in_old),
|
||||
.empty(empty),
|
||||
.full(full),
|
||||
.overflow(),
|
||||
.prog_empty(),
|
||||
.prog_full(),
|
||||
.rd_data_count(),
|
||||
.rd_rst_busy(),
|
||||
.sbiterr(),
|
||||
.underflow(),
|
||||
.wr_ack(),
|
||||
.wr_data_count(wr_data_count),
|
||||
.wr_rst_busy(),
|
||||
.din(data_in),
|
||||
.injectdbiterr(),
|
||||
.injectsbiterr(),
|
||||
.rd_en(rd_en),
|
||||
.rst(~rstn),
|
||||
.sleep(),
|
||||
.wr_clk(clk),
|
||||
.wr_en(data_in_valid)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (~rstn) begin
|
||||
data_in_valid_reg <= 0;
|
||||
running_sum_result <= 0;
|
||||
data_out_valid <= 0;
|
||||
rd_en <= 0;
|
||||
rd_en_start <= 0;
|
||||
end else begin
|
||||
data_in_valid_reg <= data_in_valid;
|
||||
data_out_valid <= data_in_valid_reg;
|
||||
rd_en_start <= ((wr_data_count == FIFO_SIZE)?1:rd_en_start);
|
||||
rd_en <= (rd_en_start?data_in_valid:rd_en);
|
||||
if (data_in_valid) begin
|
||||
running_sum_result <= running_sum_result + ext_data_in - (rd_en_start?ext_data_in_old:0);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
103
verilog/running_sum_dual_ch.v
Normal file
103
verilog/running_sum_dual_ch.v
Normal file
@ -0,0 +1,103 @@
|
||||
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
|
||||
|
||||
module running_sum_dual_ch
|
||||
#(
|
||||
parameter DATA_WIDTH0 = 16,
|
||||
parameter DATA_WIDTH1 = 16,
|
||||
parameter LOG2_SUM_LEN = 6
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rstn,
|
||||
|
||||
input signed [DATA_WIDTH0-1:0] data_in0,
|
||||
input signed [DATA_WIDTH1-1:0] data_in1,
|
||||
input data_in_valid,
|
||||
|
||||
output reg signed [(DATA_WIDTH0 + LOG2_SUM_LEN-1):0] running_sum_result0,
|
||||
output reg signed [(DATA_WIDTH1 + LOG2_SUM_LEN-1):0] running_sum_result1,
|
||||
output reg data_out_valid
|
||||
);
|
||||
|
||||
localparam FIFO_SIZE = 1<<LOG2_SUM_LEN;
|
||||
localparam TOTAL_WIDTH0 = DATA_WIDTH0 + LOG2_SUM_LEN;
|
||||
localparam TOTAL_WIDTH1 = DATA_WIDTH1 + LOG2_SUM_LEN;
|
||||
|
||||
wire signed [DATA_WIDTH0-1:0] data_in_old0;
|
||||
wire signed [DATA_WIDTH1-1:0] data_in_old1;
|
||||
|
||||
wire signed [TOTAL_WIDTH0-1:0] ext_data_in_old0 = {{LOG2_SUM_LEN{data_in_old0[DATA_WIDTH0-1]}}, data_in_old0};
|
||||
wire signed [TOTAL_WIDTH0-1:0] ext_data_in0 = {{LOG2_SUM_LEN{data_in0[DATA_WIDTH0-1]}}, data_in0 };
|
||||
|
||||
wire signed [TOTAL_WIDTH1-1:0] ext_data_in_old1 = {{LOG2_SUM_LEN{data_in_old1[DATA_WIDTH1-1]}}, data_in_old1};
|
||||
wire signed [TOTAL_WIDTH1-1:0] ext_data_in1 = {{LOG2_SUM_LEN{data_in1[DATA_WIDTH1-1]}}, data_in1 };
|
||||
|
||||
reg data_in_valid_reg;
|
||||
reg rd_en, rd_en_start;
|
||||
wire [LOG2_SUM_LEN:0] wr_data_count;
|
||||
|
||||
xpm_fifo_sync #(
|
||||
.DOUT_RESET_VALUE("0"), // String
|
||||
.ECC_MODE("no_ecc"), // String
|
||||
.FIFO_MEMORY_TYPE("auto"), // String
|
||||
.FIFO_READ_LATENCY(0), // DECIMAL
|
||||
.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL
|
||||
.FULL_RESET_VALUE(0), // DECIMAL
|
||||
.PROG_EMPTY_THRESH(10), // DECIMAL
|
||||
.PROG_FULL_THRESH(10), // DECIMAL
|
||||
.RD_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1), // DECIMAL
|
||||
.READ_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL
|
||||
.READ_MODE("fwft"), // String
|
||||
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
|
||||
.WAKEUP_TIME(0), // DECIMAL
|
||||
.WRITE_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL
|
||||
.WR_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1) // DECIMAL
|
||||
) fifo_1clk_for_running_sum_dual_ch_i (
|
||||
.almost_empty(),
|
||||
.almost_full(),
|
||||
.data_valid(),
|
||||
.dbiterr(),
|
||||
.dout({data_in_old1, data_in_old0}),
|
||||
.empty(empty),
|
||||
.full(full),
|
||||
.overflow(),
|
||||
.prog_empty(),
|
||||
.prog_full(),
|
||||
.rd_data_count(),
|
||||
.rd_rst_busy(),
|
||||
.sbiterr(),
|
||||
.underflow(),
|
||||
.wr_ack(),
|
||||
.wr_data_count(wr_data_count),
|
||||
.wr_rst_busy(),
|
||||
.din({data_in1, data_in0}),
|
||||
.injectdbiterr(),
|
||||
.injectsbiterr(),
|
||||
.rd_en(rd_en),
|
||||
.rst(~rstn),
|
||||
.sleep(),
|
||||
.wr_clk(clk),
|
||||
.wr_en(data_in_valid)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (~rstn) begin
|
||||
data_in_valid_reg <= 0;
|
||||
running_sum_result0 <= 0;
|
||||
running_sum_result1 <= 0;
|
||||
data_out_valid <= 0;
|
||||
rd_en <= 0;
|
||||
rd_en_start <= 0;
|
||||
end else begin
|
||||
data_in_valid_reg <= data_in_valid;
|
||||
data_out_valid <= data_in_valid_reg;
|
||||
rd_en_start <= ((wr_data_count == FIFO_SIZE)?1:rd_en_start);
|
||||
rd_en <= (rd_en_start?data_in_valid:rd_en);
|
||||
if (data_in_valid) begin
|
||||
running_sum_result0 <= running_sum_result0 + ext_data_in0 - (rd_en_start?ext_data_in_old0:0);
|
||||
running_sum_result1 <= running_sum_result1 + ext_data_in1 - (rd_en_start?ext_data_in_old1:0);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
68
verilog/signal_watchdog.v
Normal file
68
verilog/signal_watchdog.v
Normal file
@ -0,0 +1,68 @@
|
||||
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
|
||||
|
||||
module signal_watchdog
|
||||
#(
|
||||
parameter integer IQ_DATA_WIDTH = 16,
|
||||
parameter LOG2_SUM_LEN = 6
|
||||
)
|
||||
(
|
||||
input clk,
|
||||
input rstn,
|
||||
input enable,
|
||||
|
||||
input signed [(IQ_DATA_WIDTH-1):0] i_data,
|
||||
input signed [(IQ_DATA_WIDTH-1):0] q_data,
|
||||
input iq_valid,
|
||||
|
||||
input [15:0] signal_len,
|
||||
input sig_valid,
|
||||
|
||||
input [15:0] max_signal_len_th,
|
||||
input signed [(LOG2_SUM_LEN+2-1):0] dc_running_sum_th,
|
||||
|
||||
output receiver_rst
|
||||
);
|
||||
wire signed [1:0] i_sign;
|
||||
wire signed [1:0] q_sign;
|
||||
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i;
|
||||
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q;
|
||||
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i_abs;
|
||||
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q_abs;
|
||||
|
||||
wire receiver_rst_internal;
|
||||
reg receiver_rst_reg;
|
||||
wire receiver_rst_pulse;
|
||||
|
||||
assign i_sign = (i_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
|
||||
assign q_sign = (q_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
|
||||
|
||||
assign running_sum_result_i_abs = (running_sum_result_i[LOG2_SUM_LEN+2-1]?(-running_sum_result_i):running_sum_result_i);
|
||||
assign running_sum_result_q_abs = (running_sum_result_q[LOG2_SUM_LEN+2-1]?(-running_sum_result_q):running_sum_result_q);
|
||||
|
||||
assign receiver_rst_internal = (enable&(running_sum_result_i_abs>=dc_running_sum_th || running_sum_result_q_abs>=dc_running_sum_th));
|
||||
|
||||
assign receiver_rst_pulse = (receiver_rst_internal&&(~receiver_rst_reg));
|
||||
|
||||
assign receiver_rst = ( receiver_rst_reg | (sig_valid && (signal_len<14 || signal_len>max_signal_len_th)) );
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (~rstn) begin
|
||||
receiver_rst_reg <= 0;
|
||||
end else begin
|
||||
receiver_rst_reg <= receiver_rst_internal;
|
||||
end
|
||||
end
|
||||
|
||||
running_sum_dual_ch #(.DATA_WIDTH0(2), .DATA_WIDTH1(2), .LOG2_SUM_LEN(LOG2_SUM_LEN)) signal_watchdog_running_sum_inst (
|
||||
.clk(clk),
|
||||
.rstn(rstn),
|
||||
|
||||
.data_in0(i_sign),
|
||||
.data_in1(q_sign),
|
||||
.data_in_valid(iq_valid),
|
||||
.running_sum_result0(running_sum_result_i),
|
||||
.running_sum_result1(running_sum_result_q),
|
||||
.data_out_valid()
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user