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Merge pull request #18 from open-sdr/dot11zynq

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openwifi receiver improvements 2021
This commit is contained in:
Jinghao Shi 2022-01-28 11:11:57 -08:00 committed by GitHub
commit 4ad09c44c3
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GPG Key ID: 4AEE18F83AFDEB23
16 changed files with 1215 additions and 293 deletions
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258
verilog/Xilinx/zynq/atan_lut/atan_lut.coe
View File

@ -1,258 +1,514 @@
memory_initialization_radix=2;
memory_initialization_vector=
000000000,
000000001,
000000010,
000000011,
000000100,
000000101,
000000110,
000000111,
000001000,
000001001,
000001010,
000001011,
000001100,
000001101,
000001110,
000001111,
000010000,
000010001,
000010010,
000010011,
000010100,
000010101,
000010110,
000010111,
000011000,
000011001,
000011010,
000011011,
000011100,
000011101,
000011110,
000011111,
000100000,
000100001,
000100010,
000100011,
000100100,
000100101,
000100110,
000100111,
000101000,
000101001,
000101010,
000101011,
000101100,
000101101,
000101110,
000101111,
000110000,
000110001,
000110010,
000110011,
000110100,
000110101,
000110110,
000110111,
000111000,
000111001,
000111010,
000111011,
000111100,
000111101,
000111110,
000111111,
001000000,
001000001,
001000010,
001000011,
001000100,
001000101,
001000110,
001000111,
001001000,
001001001,
001001001,
001001010,
001001011,
001001100,
001001101,
001001110,
001001111,
001010000,
001010001,
001010010,
001010011,
001010100,
001010101,
001010110,
001010111,
001011000,
001011001,
001011010,
001011011,
001011100,
001011101,
001011110,
001011111,
001100000,
001100001,
001100010,
001100011,
001100100,
001100101,
001100110,
001100111,
001101000,
001101001,
001101001,
001101010,
001101011,
001101100,
001101101,
001101110,
001101111,
001110000,
001110001,
001110010,
001110011,
001110100,
001110101,
001110110,
001110111,
001111000,
001111001,
001111010,
001111011,
001111100,
001111100,
001111101,
001111110,
001111111,
010000000,
010000001,
010000010,
010000011,
010000100,
010000101,
010000110,
010000111,
010001000,
010001001,
010001010,
010001011,
010001011,
010001100,
010001101,
010001110,
010001111,
010010000,
010010001,
010010010,
010010011,
010010100,
010010101,
010010110,
010010111,
010010111,
010011000,
010011001,
010011010,
010011011,
010011100,
010011101,
010011110,
010011111,
010100000,
010100001,
010100001,
010100010,
010100011,
010100100,
010100101,
010100110,
010100111,
010101000,
010101001,
010101010,
010101010,
010101011,
010101100,
010101101,
010101110,
010101111,
010110000,
010110001,
010110010,
010110010,
010110011,
010110100,
010110101,
010110110,
010110111,
010111000,
010111001,
010111001,
010111010,
010111011,
010111100,
010111101,
010111110,
010111111,
011000000,
011000000,
011000001,
011000010,
011000011,
011000100,
011000101,
011000110,
011000110,
011000111,
011001000,
011001001,
011001010,
011001011,
011001100,
011001100,
011001101,
011001110,
011001111,
011010000,
011010001,
011010001,
011010010,
011010011,
011010100,
011010101,
011010110,
011010111,
011010111,
011011000,
011011001,
011011010,
011011011,
011011011,
011011100,
011011101,
011011110,
011011111,
011100000,
011100000,
011100001,
011100010,
011100011,
011100100,
011100101,
011100101,
011100110,
011100111,
011101000,
011101001,
011101001,
011101010,
011101011,
011101100,
011101101,
011101101,
011101110,
011101111,
011110000,
011110001,
011110001,
011110010,
011110011,
011110100,
011110101,
011110101,
011110110,
011110111,
011111000,
011111000,
011111001,
011111010,
011111011,
011111100,
011111100,
011111101,
011111110,
011111111,
011111111,
100000000,
100000001,
100000010,
100000011,
100000011,
100000100,
100000101,
100000110,
100000110,
100000111,
100001000,
100001001,
100001001,
100001010,
100001011,
100001100,
100001100,
100001101,
100001110,
100001111,
100001111,
100010000,
100010001,
100010010,
100010010,
100010011,
100010100,
100010101,
100010101,
100010110,
100010111,
100010111,
100011000,
100011001,
100011010,
100011010,
100011011,
100011100,
100011101,
100011101,
100011110,
100011111,
100011111,
100100000,
100100001,
100100010,
100100010,
100100011,
100100100,
100100100,
100100101,
100100110,
100100111,
100100111,
100101000,
100101001,
100101001,
100101010,
100101011,
100101011,
100101100,
100101101,
100101110,
100101110,
100101111,
100110000,
100110000,
100110001,
100110010,
100110010,
100110011,
100110100,
100110100,
100110101,
100110110,
100110110,
100110111,
100111000,
100111000,
100111001,
100111010,
100111010,
100111011,
100111100,
100111100,
100111101,
100111110,
100111110,
100111111,
101000000,
101000000,
101000001,
101000010,
101000010,
101000011,
101000100,
101000100,
101000101,
101000110,
101000110,
101000111,
101001000,
101001000,
101001001,
101001001,
101001010,
101001011,
101001011,
101001100,
101001101,
101001101,
101001110,
101001111,
101001111,
101010000,
101010000,
101010001,
101010010,
101010010,
101010011,
101010100,
101010100,
101010101,
101010101,
101010110,
101010111,
101010111,
101011000,
101011000,
101011001,
101011010,
101011010,
101011011,
101011100,
101011100,
101011101,
101011101,
101011110,
101011111,
101011111,
101100000,
101100000,
101100001,
101100010,
101100010,
101100011,
101100011,
101100100,
101100100,
101100101,
101100110,
101100110,
101100111,
101100111,
101101000,
101101001,
101101001,
101101010,
101101010,
101101011,
101101011,
101101100,
101101101,
101101101,
101101110,
101101110,
101101111,
101101111,
101110000,
101110001,
101110001,
101110010,
101110010,
101110011,
101110011,
101110100,
101110101,
101110101,
101110110,
101110110,
101110111,
101110111,
101111000,
101111000,
101111001,
101111010,
101111010,
101111011,
101111011,
101111100,
101111100,
101111101,
101111101,
101111110,
101111110,
101111111,
101111111,
110000000,
110000001,
110000001,
110000010,
110000010,
110000011,
110000011,
110000100,
110000100,
110000101,
110000101,
110000110,
110000110,
110000111,
110000111,
110001000,
110001000,
110001001,
110001001,
110001010,
110001011,
110001011,
110001100,
110001100,
110001101,
110001101,
110001110,
110001110,
110001111,
110001111,
110010000,
110010001;
110010000,
110010001,
110010001,
110010010;

14
verilog/Xilinx/zynq/atan_lut/atan_lut.xci
View File

@ -89,8 +89,8 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
@ -137,8 +137,8 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">9</spirit:configurableElementValue>
@ -157,8 +157,8 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">9</spirit:configurableElementValue>
@ -228,7 +228,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>

258
verilog/Xilinx/zynquplus/atan_lut/atan_lut.coe
View File

@ -1,258 +1,514 @@
memory_initialization_radix=2;
memory_initialization_vector=
000000000,
000000001,
000000010,
000000011,
000000100,
000000101,
000000110,
000000111,
000001000,
000001001,
000001010,
000001011,
000001100,
000001101,
000001110,
000001111,
000010000,
000010001,
000010010,
000010011,
000010100,
000010101,
000010110,
000010111,
000011000,
000011001,
000011010,
000011011,
000011100,
000011101,
000011110,
000011111,
000100000,
000100001,
000100010,
000100011,
000100100,
000100101,
000100110,
000100111,
000101000,
000101001,
000101010,
000101011,
000101100,
000101101,
000101110,
000101111,
000110000,
000110001,
000110010,
000110011,
000110100,
000110101,
000110110,
000110111,
000111000,
000111001,
000111010,
000111011,
000111100,
000111101,
000111110,
000111111,
001000000,
001000001,
001000010,
001000011,
001000100,
001000101,
001000110,
001000111,
001001000,
001001001,
001001001,
001001010,
001001011,
001001100,
001001101,
001001110,
001001111,
001010000,
001010001,
001010010,
001010011,
001010100,
001010101,
001010110,
001010111,
001011000,
001011001,
001011010,
001011011,
001011100,
001011101,
001011110,
001011111,
001100000,
001100001,
001100010,
001100011,
001100100,
001100101,
001100110,
001100111,
001101000,
001101001,
001101001,
001101010,
001101011,
001101100,
001101101,
001101110,
001101111,
001110000,
001110001,
001110010,
001110011,
001110100,
001110101,
001110110,
001110111,
001111000,
001111001,
001111010,
001111011,
001111100,
001111100,
001111101,
001111110,
001111111,
010000000,
010000001,
010000010,
010000011,
010000100,
010000101,
010000110,
010000111,
010001000,
010001001,
010001010,
010001011,
010001011,
010001100,
010001101,
010001110,
010001111,
010010000,
010010001,
010010010,
010010011,
010010100,
010010101,
010010110,
010010111,
010010111,
010011000,
010011001,
010011010,
010011011,
010011100,
010011101,
010011110,
010011111,
010100000,
010100001,
010100001,
010100010,
010100011,
010100100,
010100101,
010100110,
010100111,
010101000,
010101001,
010101010,
010101010,
010101011,
010101100,
010101101,
010101110,
010101111,
010110000,
010110001,
010110010,
010110010,
010110011,
010110100,
010110101,
010110110,
010110111,
010111000,
010111001,
010111001,
010111010,
010111011,
010111100,
010111101,
010111110,
010111111,
011000000,
011000000,
011000001,
011000010,
011000011,
011000100,
011000101,
011000110,
011000110,
011000111,
011001000,
011001001,
011001010,
011001011,
011001100,
011001100,
011001101,
011001110,
011001111,
011010000,
011010001,
011010001,
011010010,
011010011,
011010100,
011010101,
011010110,
011010111,
011010111,
011011000,
011011001,
011011010,
011011011,
011011011,
011011100,
011011101,
011011110,
011011111,
011100000,
011100000,
011100001,
011100010,
011100011,
011100100,
011100101,
011100101,
011100110,
011100111,
011101000,
011101001,
011101001,
011101010,
011101011,
011101100,
011101101,
011101101,
011101110,
011101111,
011110000,
011110001,
011110001,
011110010,
011110011,
011110100,
011110101,
011110101,
011110110,
011110111,
011111000,
011111000,
011111001,
011111010,
011111011,
011111100,
011111100,
011111101,
011111110,
011111111,
011111111,
100000000,
100000001,
100000010,
100000011,
100000011,
100000100,
100000101,
100000110,
100000110,
100000111,
100001000,
100001001,
100001001,
100001010,
100001011,
100001100,
100001100,
100001101,
100001110,
100001111,
100001111,
100010000,
100010001,
100010010,
100010010,
100010011,
100010100,
100010101,
100010101,
100010110,
100010111,
100010111,
100011000,
100011001,
100011010,
100011010,
100011011,
100011100,
100011101,
100011101,
100011110,
100011111,
100011111,
100100000,
100100001,
100100010,
100100010,
100100011,
100100100,
100100100,
100100101,
100100110,
100100111,
100100111,
100101000,
100101001,
100101001,
100101010,
100101011,
100101011,
100101100,
100101101,
100101110,
100101110,
100101111,
100110000,
100110000,
100110001,
100110010,
100110010,
100110011,
100110100,
100110100,
100110101,
100110110,
100110110,
100110111,
100111000,
100111000,
100111001,
100111010,
100111010,
100111011,
100111100,
100111100,
100111101,
100111110,
100111110,
100111111,
101000000,
101000000,
101000001,
101000010,
101000010,
101000011,
101000100,
101000100,
101000101,
101000110,
101000110,
101000111,
101001000,
101001000,
101001001,
101001001,
101001010,
101001011,
101001011,
101001100,
101001101,
101001101,
101001110,
101001111,
101001111,
101010000,
101010000,
101010001,
101010010,
101010010,
101010011,
101010100,
101010100,
101010101,
101010101,
101010110,
101010111,
101010111,
101011000,
101011000,
101011001,
101011010,
101011010,
101011011,
101011100,
101011100,
101011101,
101011101,
101011110,
101011111,
101011111,
101100000,
101100000,
101100001,
101100010,
101100010,
101100011,
101100011,
101100100,
101100100,
101100101,
101100110,
101100110,
101100111,
101100111,
101101000,
101101001,
101101001,
101101010,
101101010,
101101011,
101101011,
101101100,
101101101,
101101101,
101101110,
101101110,
101101111,
101101111,
101110000,
101110001,
101110001,
101110010,
101110010,
101110011,
101110011,
101110100,
101110101,
101110101,
101110110,
101110110,
101110111,
101110111,
101111000,
101111000,
101111001,
101111010,
101111010,
101111011,
101111011,
101111100,
101111100,
101111101,
101111101,
101111110,
101111110,
101111111,
101111111,
110000000,
110000001,
110000001,
110000010,
110000010,
110000011,
110000011,
110000100,
110000100,
110000101,
110000101,
110000110,
110000110,
110000111,
110000111,
110001000,
110001000,
110001001,
110001001,
110001010,
110001011,
110001011,
110001100,
110001100,
110001101,
110001101,
110001110,
110001110,
110001111,
110001111,
110010000,
110010001;
110010000,
110010001,
110010001,
110010010;

14
verilog/Xilinx/zynquplus/atan_lut/atan_lut.xci
View File

@ -89,8 +89,8 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
@ -137,8 +137,8 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">9</spirit:configurableElementValue>
@ -157,8 +157,8 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">9</spirit:configurableElementValue>
@ -228,7 +228,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">512</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>

2
verilog/common_defs.v
View File

@ -1,4 +1,4 @@
`define ATAN_LUT_LEN_SHIFT 8
`define ATAN_LUT_LEN_SHIFT 9
// changing this requires changing PI definition in common_params.v accordingly
`define ATAN_LUT_SCALE_SHIFT 9

14
verilog/common_params.v
View File

@ -35,10 +35,12 @@ localparam S_CHECK_HT_SIG_CRC = 7;
localparam S_CHECK_HT_SIG = 8;
localparam S_HT_STS = 9;
localparam S_HT_LTS = 10;
localparam S_DECODE_DATA = 11;
localparam S_SIGNAL_ERROR = 12;
localparam S_HT_SIG_ERROR = 13;
localparam S_DECODE_DONE = 14;
localparam S_MPDU_DELIM = 11;
localparam S_DECODE_DATA = 12;
localparam S_MPDU_PAD = 13;
localparam S_SIGNAL_ERROR = 14;
localparam S_HT_SIG_ERROR = 15;
localparam S_DECODE_DONE = 16;
//////////////////////////////////////////////////////////////////////////
@ -62,7 +64,9 @@ localparam E_UNSUPPORTED_FEC = 5;
localparam E_UNSUPPORTED_SGI = 6;
localparam E_UNSUPPORTED_SPATIAL = 7;
localparam E_HT_WRONG_TAIL = 8;
localparam E_WRONG_CRC = 9;
localparam E_HT_AMPDU_WARN = 9;
localparam E_HT_AMPDU_ERROR = 10;
localparam E_WRONG_CRC = 11;
// fcs error
localparam E_WRONG_FCS = 1;

197
verilog/dot11.v
View File

@ -20,6 +20,7 @@ module dot11 (
input [31:0] sample_in,
input sample_in_strobe,
input soft_decoding,
input wire force_ht_smoothing,
// OUTPUT: bytes and FCS status
output reg demod_is_ongoing,
@ -44,7 +45,7 @@ module dot11 (
// decode status
// (* mark_debug = "true", DONT_TOUCH = "TRUE" *)
output reg [3:0] state,
output reg [4:0] state,
output reg [3:0] status_code,
output state_changed,
output reg [31:0] state_history,
@ -54,7 +55,7 @@ module dot11 (
// sync short
output short_preamble_detected,
output [31:0] phase_offset,
output [15:0] phase_offset,
// sync long
output [31:0] sync_long_metric,
@ -68,7 +69,7 @@ module dot11 (
// equalizer
output [31:0] equalizer_out,
output equalizer_out_strobe,
output [2:0] equalizer_state,
output [3:0] equalizer_state,
output wire ofdm_symbol_eq_out_pulse,
// legacy signal info
@ -87,7 +88,8 @@ module dot11 (
output [15:0] ht_len,
output ht_smoothing,
output ht_not_sounding,
output ht_aggregation,
output ht_aggr,
output reg ht_aggr_last,
output [1:0] ht_stbc,
output ht_fec_coding,
output ht_sgi,
@ -96,6 +98,8 @@ module dot11 (
// decoding pipeline
output [5:0] demod_out,
output [5:0] demod_soft_bits,
output [3:0] demod_soft_bits_pos,
output demod_out_strobe,
output [7:0] deinterleave_erase_out,
@ -117,9 +121,9 @@ module dot11 (
////////////////////////////////////////////////////////////////////////////////
// extra info output to ease side info and viterbi state monitor
////////////////////////////////////////////////////////////////////////////////
reg [2:0] equalizer_state_reg;
reg [3:0] equalizer_state_reg;
assign ofdm_symbol_eq_out_pulse = (equalizer_state==4 && equalizer_state_reg==6);
assign ofdm_symbol_eq_out_pulse = (equalizer_state==4 && equalizer_state_reg==7);
always @(posedge clock) begin
if (reset==1) begin
@ -163,13 +167,13 @@ rot_lut rot_lut_inst (
wire [31:0] sync_short_phase_in_i;
wire [31:0] sync_short_phase_in_q;
wire sync_short_phase_in_stb;
wire [31:0] sync_short_phase_out;
wire [15:0] sync_short_phase_out;
wire sync_short_phase_out_stb;
wire [31:0] eq_phase_in_i;
wire [31:0] eq_phase_in_q;
wire eq_phase_in_stb;
wire [31:0] eq_phase_out;
wire [15:0] eq_phase_out;
wire eq_phase_out_stb;
wire[31:0] phase_in_i = state == S_SYNC_SHORT?
@ -179,7 +183,7 @@ wire[31:0] phase_in_q = state == S_SYNC_SHORT?
wire phase_in_stb = state == S_SYNC_SHORT?
sync_short_phase_in_stb: eq_phase_in_stb;
wire [31:0] phase_out;
wire [15:0] phase_out;
wire phase_out_stb;
assign sync_short_phase_out = phase_out;
@ -234,7 +238,7 @@ reg do_descramble;
reg [31:0] num_bits_to_decode;
reg short_gi;
reg [3:0] old_state;
reg [4:0] old_state;
assign power_trigger = (rssi_half_db>=power_thres? 1: 0);
assign state_changed = state != old_state;
@ -260,7 +264,7 @@ assign ht_len = ht_sig1[23:8];
assign ht_smoothing = ht_sig2[0];
assign ht_not_sounding = ht_sig2[1];
assign ht_aggregation = ht_sig2[3];
assign ht_aggr = ht_sig2[3];
assign ht_stbc = ht_sig2[5:4];
assign ht_fec_coding = ht_sig2[6];
assign ht_sgi = ht_sig2[7];
@ -271,6 +275,9 @@ wire ht_rsvd = ht_sig2[2];
wire [7:0] crc = ht_sig2[17:10];
wire [5:0] ht_sig_tail = ht_sig2[23:18];
reg [15:0] pkt_len_rem;
reg [7:0] mpdu_del_crc;
reg [1:0] mpdu_pad;
reg crc_in_stb;
reg crc_in;
@ -365,9 +372,10 @@ equalizer equalizer_inst (
.enable(enable & equalizer_enable),
.sample_in(sync_long_out),
.sample_in_strobe(sync_long_out_strobe),
.sample_in_strobe(sync_long_out_strobe && !(state==S_HT_SIGNAL && num_ofdm_symbol==6)),
.ht_next(ht_next),
.pkt_ht(pkt_ht),
.ht_smoothing(ht_smoothing|force_ht_smoothing),
.phase_in_i(eq_phase_in_i),
.phase_in_q(eq_phase_in_q),
@ -389,7 +397,7 @@ equalizer equalizer_inst (
);
delayT #(.DATA_WIDTH(33), .DELAY(6)) eq_delay_inst (
delayT #(.DATA_WIDTH(33), .DELAY(9)) eq_delay_inst (
.clock(clock),
.reset(reset),
@ -415,6 +423,8 @@ ofdm_decoder ofdm_decoder_inst (
.byte_out_strobe(byte_out_strobe),
.demod_out(demod_out),
.demod_soft_bits(demod_soft_bits),
.demod_soft_bits_pos(demod_soft_bits_pos),
.demod_out_strobe(demod_out_strobe),
.deinterleave_erase_out(deinterleave_erase_out),
@ -481,6 +491,9 @@ always @(posedge clock) begin
equalizer_enable <= 0;
ht_next <= 0;
pkt_len_rem <= 0;
mpdu_del_crc <= 0;
mpdu_pad <= 0;
pkt_len <= 0;
pkt_len_total <= 0;
@ -505,6 +518,7 @@ always @(posedge clock) begin
crc_reset <= 0;
ht_sig_crc_ok <= 0;
ht_sig_stb <= 0;
ht_aggr_last <= 0;
fcs_out_strobe <= 0;
fcs_ok <= 0;
@ -523,6 +537,9 @@ always @(posedge clock) begin
ofdm_enable <= 0;
ofdm_reset <= 0;
pkt_len_total <= 16'hffff;
ht_sig1 <= 0;
ht_sig2 <= 0;
pkt_len_rem <= 0;
if (power_trigger) begin
`ifdef DEBUG_PRINT
@ -679,7 +696,7 @@ always @(posedge clock) begin
abs_eq_q <= eq_out_q[15]? ~eq_out_q+1: eq_out_q;
if (abs_eq_q > abs_eq_i) begin
rot_eq_count <= rot_eq_count + 1;
end else begin
end else if (abs_eq_q < abs_eq_i) begin
normal_eq_count <= normal_eq_count + 1;
end
end
@ -724,7 +741,8 @@ always @(posedge clock) begin
"CBW: %d, ", ht_cbw? 40: 20,
"length = %012b (%d), ", ht_len, ht_len,
"rsvd = %d, ", ht_rsvd,
"aggr = %d, ", ht_aggregation,
"aggr = %d, ", ht_aggr,
"aggr_last = %d, ", ht_aggr_last,
"stbd = %02b, ", ht_stbc,
"fec = %d, ", ht_fec_coding,
"sgi = %d, ", ht_sgi,
@ -735,6 +753,7 @@ always @(posedge clock) begin
num_bits_to_decode <= (22+(ht_len<<3))<<1;
pkt_rate <= {1'b1, ht_mcs};
pkt_len_rem <= ht_len;
pkt_len <= ht_len;
pkt_len_total <= ht_len+3+6; //(6 bytes for 3 byte HT-SIG1 and 3 byte HT-SIG2)
@ -779,9 +798,8 @@ always @(posedge clock) begin
S_CHECK_HT_SIG: begin
ofdm_reset <= 1;
ht_sig_stb <= 0;
ht_aggr_last <= 0;
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
if (ht_mcs > 7) begin
ht_unsupport <= 1;
status_code <= E_UNSUPPORTED_MCS;
@ -840,8 +858,6 @@ always @(posedge clock) begin
end
S_HT_STS: begin
pkt_header_valid <= 0;
pkt_header_valid_strobe <= 0;
if (sync_long_out_strobe) begin
sync_long_out_count <= sync_long_out_count + 1;
end
@ -853,8 +869,6 @@ always @(posedge clock) begin
end
S_HT_LTS: begin
pkt_header_valid <= 0;
pkt_header_valid_strobe <= 0;
short_gi <= ht_sgi;
if (sync_long_out_strobe) begin
sync_long_out_count <= sync_long_out_count + 1;
@ -864,8 +878,118 @@ always @(posedge clock) begin
//num_bits_to_decode <= (ht_len+3)<<4;
do_descramble <= 1;
ofdm_reset <= 1;
pkt_begin <= 1;
state <= S_DECODE_DATA;
if(ht_aggr) begin
crc_reset <= 1;
crc_count <= 0;
state <= S_MPDU_DELIM;
end else begin
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_begin <= 1;
pkt_len_rem <= 0;
state <= S_DECODE_DATA;
end
end
end
S_MPDU_DELIM: begin
crc_reset <= 0;
ofdm_reset <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
ofdm_in_i <= eq_out_i_delayed;
ofdm_in_q <= eq_out_q_delayed;
if(byte_out_strobe) begin
if(byte_count == 3) begin
byte_count <= 0;
byte_count_total <= 3+6;
if(crc_out == mpdu_del_crc && byte_out == 8'h4e) begin
// Jump over an empty MPDU delimiter
if(pkt_len == 0) begin
pkt_len_rem <= pkt_len_rem - 4;
crc_reset <= 1;
crc_count <= 0;
state <= S_MPDU_DELIM;
// Start actual packet decoding
end else begin
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_len_total <= pkt_len+3+6;
pkt_begin <= 1;
state <= S_DECODE_DATA;
// All MPDUs except last one does include padding
if((pkt_len_rem-pkt_len-mpdu_pad) > 4) begin
ht_aggr_last <= 0;
pkt_len_rem <= pkt_len_rem - (4 + pkt_len + mpdu_pad);
end else begin
ht_aggr_last <= 1;
pkt_len_rem <= 0;
end
end
// MPDU delimiter is erroneous and remaining packet length is less than 8. Stop searching
end else if(|pkt_len_rem[15:3] == 0) begin
ht_aggr_last <= 1;
fcs_out_strobe <= 1;
fcs_ok <= 0;
status_code <= E_HT_AMPDU_ERROR;
state <= S_DECODE_DONE;
// Else, restart searching
end else begin
pkt_len_rem <= pkt_len_rem - 4;
crc_reset <= 1;
crc_count <= 0;
status_code <= E_HT_AMPDU_WARN;
state <= S_MPDU_DELIM;
end
end else begin
byte_count <= byte_count + 1;
byte_count_total <= byte_count_total + 1;
if(byte_count == 0) begin
pkt_len[3:0] <= byte_out[7:4];
end else if(byte_count == 1) begin
pkt_len[11:4] <= byte_out;
end else if(byte_count == 2) begin
pkt_len[15:12] <= 0;
mpdu_del_crc <= byte_out;
if(pkt_len[1:0] == 0)
mpdu_pad <= 0;
else if(pkt_len[1:0] == 1)
mpdu_pad <= 3;
else if(pkt_len[1:0] == 2)
mpdu_pad <= 2;
else
mpdu_pad <= 1;
end
// Enable CRC calculation on the first two bytes
if(crc_count[4] == 0) begin
crc_in <= byte_out[crc_count[2:0]];
crc_in_stb <= 1;
crc_count <= crc_count + 1;
end else begin
crc_in_stb <= 0;
end
end
// Enable CRC calculation on the first two bytes
end else if((^byte_count[1:0] == 1) && (|crc_count[2:0] == 1)) begin
crc_in <= byte_out[crc_count[2:0]];
crc_in_stb <= 1;
crc_count <= crc_count + 1;
end else begin
crc_in_stb <= 0;
end
end
@ -902,7 +1026,31 @@ always @(posedge clock) begin
fcs_ok <= 0;
status_code <= E_WRONG_FCS;
end
state <= S_DECODE_DONE;
// restart the decoding process on remaining MPDUs
if(|pkt_len_rem[15:2] == 1) begin
state <= S_MPDU_PAD;
end else begin
state <= S_DECODE_DONE;
end
end
end
S_MPDU_PAD: begin
fcs_out_strobe <= 0;
fcs_ok <= 0;
ofdm_in_stb <= eq_out_stb_delayed;
ofdm_in_i <= eq_out_i_delayed;
ofdm_in_q <= eq_out_q_delayed;
if (byte_out_strobe)
mpdu_pad <= mpdu_pad - 1;
if (mpdu_pad == 0) begin
crc_reset <= 1;
crc_count <= 0;
state <= S_MPDU_DELIM;
end
end
@ -915,6 +1063,7 @@ always @(posedge clock) begin
$display("FCS WRONG");
end
`endif
ht_aggr_last <= 0;
fcs_out_strobe <= 0;
fcs_ok <= 0;
state <= S_WAIT_POWER_TRIGGER;

59
verilog/dot11_tb.v
View File

@ -26,6 +26,8 @@ wire [31:0] equalizer_out;
wire equalizer_out_strobe;
wire [5:0] demod_out;
wire [5:0] demod_soft_bits;
wire [3:0] demod_soft_bits_pos;
wire demod_out_strobe;
wire [7:0] deinterleave_erase_out;
@ -76,6 +78,8 @@ integer sync_long_out_fd;
integer equalizer_out_fd;
integer demod_out_fd;
integer demod_soft_bits_fd;
integer demod_soft_bits_pos_fd;
integer deinterleave_erase_out_fd;
integer conv_out_fd;
integer descramble_out_fd;
@ -86,21 +90,26 @@ integer byte_out_fd;
integer file_i, file_q, file_rssi_half_db, iq_sample_file;
//`define SPEED_100M // comment out this to use 200M
// ONLY allow 100(low FPGA), 200(high FPGA), 240(ultra_scal FPGA) and 400(test)
// do NOT turn on more than one of them
`define CLK_SPEED_100M
//`define CLK_SPEED_200M
//`define CLK_SPEED_240M
//`define CLK_SPEED_400M
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_ht_unsupport_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_ht_sig_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_sig_openwifi.txt"
`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_6.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_52mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/dot11n_19.5mbps_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_58.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_58.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_65mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/ack-ok-openwifi.txt"
`define NUM_SAMPLE 8560
`define NUM_SAMPLE 118560
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/openofdm_tx/PL_100Bytes/54Mbps.txt"
//`define NUM_SAMPLE 2048
@ -144,6 +153,8 @@ always @(posedge clock) begin
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
demod_out_fd = $fopen("./demod_out.txt", "w");
demod_soft_bits_fd = $fopen("./demod_soft_bits.txt", "w");
demod_soft_bits_pos_fd = $fopen("./demod_soft_bits_pos.txt", "w");
deinterleave_erase_out_fd = $fopen("./deinterleave_erase_out.txt", "w");
conv_out_fd = $fopen("./conv_out.txt", "w");
descramble_out_fd = $fopen("./descramble_out.txt", "w");
@ -154,15 +165,17 @@ always @(posedge clock) begin
end
end
`ifdef SPEED_100M
always begin //100MHz
always begin
`ifdef CLK_SPEED_100M
#5 clock = !clock;
end
`else
always begin //200MHz
`elsif CLK_SPEED_200M
#2.5 clock = !clock;
end
`elsif CLK_SPEED_240M
#2.0833333333 clock = !clock;
`elsif CLK_SPEED_400M
#1.25 clock = !clock;
`endif
end
always @(posedge clock) begin
if (reset) begin
@ -171,10 +184,14 @@ always @(posedge clock) begin
sample_in_strobe <= 0;
addr <= 0;
end else if (enable) begin
`ifdef SPEED_100M
`ifdef CLK_SPEED_100M
if (clk_count == 4) begin // for 100M; 100/20 = 5
`else
`elsif CLK_SPEED_200M
if (clk_count == 9) begin // for 200M; 200/20 = 10
`elsif CLK_SPEED_240M
if (clk_count == 11) begin // for 200M; 240/20 = 12
`elsif CLK_SPEED_400M
if (clk_count == 19) begin // for 200M; 400/20 = 20
`endif
sample_in_strobe <= 1;
//$fscanf(iq_sample_file, "%d %d %d", file_i, file_q, file_rssi_half_db);
@ -225,6 +242,8 @@ always @(posedge clock) begin
$fclose(equalizer_out_fd);
$fclose(demod_out_fd);
$fclose(demod_soft_bits_fd);
$fclose(demod_soft_bits_pos_fd);
$fclose(deinterleave_erase_out_fd);
$fclose(conv_out_fd);
$fclose(descramble_out_fd);
@ -257,27 +276,31 @@ always @(posedge clock) begin
$fflush(signal_fd);
end
if (dot11_state == S_DECODE_DATA && demod_out_strobe) begin
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && demod_out_strobe) begin
$fwrite(demod_out_fd, "%b %b %b %b %b %b\n",demod_out[0],demod_out[1],demod_out[2],demod_out[3],demod_out[4],demod_out[5]);
$fwrite(demod_soft_bits_fd, "%b %b %b %b %b %b\n",demod_soft_bits[0],demod_soft_bits[1],demod_soft_bits[2],demod_soft_bits[3],demod_soft_bits[4],demod_soft_bits[5]);
$fwrite(demod_soft_bits_pos_fd, "%b %b %b %b\n",demod_soft_bits_pos[0],demod_soft_bits_pos[1],demod_soft_bits_pos[2],demod_soft_bits_pos[3]);
$fflush(demod_out_fd);
$fflush(demod_soft_bits_fd);
$fflush(demod_soft_bits_pos_fd);
end
if (dot11_state == S_DECODE_DATA && deinterleave_erase_out_strobe) begin
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && deinterleave_erase_out_strobe) begin
$fwrite(deinterleave_erase_out_fd, "%b %b %b %b %b %b %b %b\n", deinterleave_erase_out[0], deinterleave_erase_out[1], deinterleave_erase_out[2], deinterleave_erase_out[3], deinterleave_erase_out[4], deinterleave_erase_out[5], deinterleave_erase_out[6], deinterleave_erase_out[7]);
$fflush(deinterleave_erase_out_fd);
end
if (dot11_state == S_DECODE_DATA && conv_decoder_out_stb) begin
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && conv_decoder_out_stb) begin
$fwrite(conv_out_fd, "%b\n", conv_decoder_out);
$fflush(conv_out_fd);
end
if (dot11_state == S_DECODE_DATA && descramble_out_strobe) begin
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && descramble_out_strobe) begin
$fwrite(descramble_out_fd, "%b\n", descramble_out);
$fflush(descramble_out_fd);
end
if (dot11_state == S_DECODE_DATA && byte_out_strobe) begin
if ((dot11_state == S_MPDU_DELIM || dot11_state == S_DECODE_DATA || dot11_state == S_MPDU_PAD) && byte_out_strobe) begin
$fwrite(byte_out_fd, "%02x\n", byte_out);
$fflush(byte_out_fd);
end
@ -335,6 +358,8 @@ dot11 dot11_inst (
.legacy_sig_tail(legacy_sig_tail),
.demod_out(demod_out),
.demod_soft_bits(demod_soft_bits),
.demod_soft_bits_pos(demod_soft_bits_pos),
.demod_out_strobe(demod_out_strobe),
.deinterleave_erase_out(deinterleave_erase_out),

188
verilog/equalizer.v
View File

@ -10,11 +10,12 @@ module equalizer
input sample_in_strobe,
input ht_next,
input pkt_ht,
input ht_smoothing,
output [31:0] phase_in_i,
output [31:0] phase_in_q,
output reg phase_in_stb,
input [31:0] phase_out,
input [15:0] phase_out,
input phase_out_stb,
output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
@ -23,7 +24,7 @@ module equalizer
output reg [31:0] sample_out,
output reg sample_out_strobe,
output reg [2:0] state,
output reg [3:0] state,
// for side channel
output wire [31:0] csi,
@ -81,7 +82,7 @@ reg [63:0] pilot_mask;
reg [126:0] polarity;
reg [3:0] ht_polarity;
reg [3:0] current_polarity;
reg [3:0] pilot_count;
reg [3:0] pilot_count1, pilot_count2;
reg signed [15:0] input_i;
reg signed [15:0] input_q;
@ -111,14 +112,33 @@ wire [15:0] buf_q_out;
reg pilot_in_stb;
wire signed [31:0] pilot_i;
wire signed [31:0] pilot_q;
reg signed [31:0] pilot_i_reg, pilot_q_reg;
reg signed [15:0] pilot_iq_phase[0:3];
reg signed [31:0] pilot_sum_i;
reg signed [31:0] pilot_sum_q;
assign phase_in_i = pilot_sum_i;
assign phase_in_q = pilot_sum_q;
assign phase_in_i = pilot_i_reg;
assign phase_in_q = pilot_q_reg;
reg signed [31:0] pilot_phase;
reg signed [15:0] pilot_phase_err;
reg signed [15:0] cpe; // common phase error due to RFO
reg signed [15:0] Sxy;
localparam Sx2 = 980;
// linear varying phase error (LVPE) parameters
reg signed [7:0] sym_idx;
reg lvpe_in_stb;
wire lvpe_out_stb;
wire signed [31:0] lvpe_dividend, lvpe;
wire signed [23:0] lvpe_divisor;
assign lvpe_dividend = (sym_idx <= 33 ? sym_idx*Sxy : (sym_idx-64)*Sxy);
assign lvpe_divisor = Sx2;
reg signed [15:0] phase_err;
wire signed [15:0] sym_phase;
assign sym_phase = (phase_err > 1608) ? (phase_err - 3217) : ((phase_err < -1608) ? (phase_err + 3217) : phase_err);
reg rot_in_stb;
wire signed [15:0] rot_i;
@ -151,11 +171,11 @@ reg signed [18:0] lts_sum_q;
reg [2:0] lts_mv_avg_len;
reg lts_div_in_stb;
wire [31:0] dividend_i = (state == S_UPDATE_DC_LTS || state == S_MV_AVG_LTS) ? (lts_sum_i[18] == 0 ? {13'h0,lts_sum_i} : {13'h1FFF,lts_sum_i}) : (state == S_ADJUST_FREQ_OFFSET ? prod_i_scaled : 0);
wire [31:0] dividend_q = (state == S_UPDATE_DC_LTS || state == S_MV_AVG_LTS) ? (lts_sum_q[18] == 0 ? {13'h0,lts_sum_q} : {13'h1FFF,lts_sum_q}) : (state == S_ADJUST_FREQ_OFFSET ? prod_q_scaled : 0);
wire [23:0] divisor_i = (state == S_UPDATE_DC_LTS || state == S_MV_AVG_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ADJUST_FREQ_OFFSET ? mag_sq[23:0] : 1);
wire [23:0] divisor_q = (state == S_UPDATE_DC_LTS || state == S_MV_AVG_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ADJUST_FREQ_OFFSET ? mag_sq[23:0] : 1);
wire div_in_stb = (state == S_UPDATE_DC_LTS || state == S_MV_AVG_LTS) ? lts_div_in_stb : (state == S_ADJUST_FREQ_OFFSET ? prod_out_strobe : 0);
wire [31:0] dividend_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_i[18] == 0 ? {13'h0,lts_sum_i} : {13'h1FFF,lts_sum_i}) : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? prod_i_scaled : 0);
wire [31:0] dividend_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_q[18] == 0 ? {13'h0,lts_sum_q} : {13'h1FFF,lts_sum_q}) : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? prod_q_scaled : 0);
wire [23:0] divisor_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? mag_sq[23:0] : 1);
wire [23:0] divisor_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? mag_sq[23:0] : 1);
wire div_in_stb = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? lts_div_in_stb : (state == S_ADJUST_FREQ_and_SAMPL_OFFSET ? prod_out_strobe : 0);
reg [15:0] num_output;
@ -187,7 +207,8 @@ wire signed [15:0] norm_i_signed, norm_q_signed;
assign norm_i_signed = sample_out[31:16];
assign norm_q_signed = sample_out[15:0];
wire signed [31:0] prod_i_signed, prod_q_signed, prod_i_scaled_signed, prod_q_scaled_signed, phase_out_signed;
wire signed [31:0] prod_i_signed, prod_q_signed, prod_i_scaled_signed, prod_q_scaled_signed;
wire signed [15:0] phase_out_signed;
assign prod_i_signed = prod_i;
assign prod_q_signed = prod_q;
assign prod_i_scaled_signed = prod_i_scaled;
@ -210,7 +231,7 @@ always @(posedge clock) begin
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
end
if (num_ofdm_sym == 1 && state == S_CALC_FREQ_OFFSET && sample_in_strobe_dly == 1 && enable && (~reset) ) begin
if ((num_ofdm_sym == 1 || (pkt_ht==1 && num_ofdm_sym==5)) && state == S_CALC_FREQ_OFFSET && sample_in_strobe_dly == 1 && enable && (~reset) ) begin
$fwrite(new_lts_fd, "%d %d\n", lts_i_out, lts_q_out);
$fflush(new_lts_fd);
end
@ -337,7 +358,7 @@ rotate rotate_inst (
.in_i(buf_i_out),
.in_q(buf_q_out),
.phase(pilot_phase),
.phase(sym_phase),
.input_strobe(rot_in_stb),
.rot_addr(rot_addr),
@ -399,14 +420,29 @@ divider norm_q_inst (
.quotient(quotient_q)
);
// LVPE calculation to estimate SFO
divider lvpe_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.dividend(lvpe_dividend),
.divisor(lvpe_divisor),
.input_strobe(lvpe_in_stb),
.quotient(lvpe),
.output_strobe(lvpe_out_stb)
);
localparam S_FIRST_LTS = 0;
localparam S_SECOND_LTS = 1;
localparam S_UPDATE_DC_LTS = 2;
localparam S_MV_AVG_LTS = 3;
localparam S_SMOOTH_CH_DC = 2;
localparam S_SMOOTH_CH_LTS = 3;
localparam S_GET_POLARITY = 4;
localparam S_CALC_FREQ_OFFSET = 5;
localparam S_ADJUST_FREQ_OFFSET = 6;
localparam S_HT_LTS = 7;
localparam S_CALC_SAMPL_OFFSET = 6;
localparam S_ADJUST_FREQ_and_SAMPL_OFFSET = 7;
localparam S_HT_LTS = 8;
always @(posedge clock) begin
if (reset) begin
@ -433,22 +469,32 @@ always @(posedge clock) begin
ht_polarity <= HT_POLARITY;
current_polarity <= 0;
pilot_count <= 0;
pilot_count1 <= 0;
pilot_count2 <= 0;
in_waddr <= 0;
in_raddr <= 0;
sym_idx <= 0;
lts_reg1_i <= 0; lts_reg2_i <= 0; lts_reg3_i <= 0; lts_reg4_i <= 0; lts_reg5_i <= 0;
lts_reg1_q <= 0; lts_reg2_q <= 0; lts_reg3_q <= 0; lts_reg4_q <= 0; lts_reg5_q <= 0;
lts_sum_i <= 0;
lts_sum_q <= 0;
lts_mv_avg_len <= 0;
lts_div_in_stb <= 0;
phase_in_stb <= 0;
pilot_sum_i <= 0;
pilot_sum_q <= 0;
pilot_phase <= 0;
pilot_phase_err <= 0;
cpe <= 0;
Sxy <= 0;
lvpe_in_stb <= 0;
phase_err <= 0;
pilot_in_stb <= 0;
pilot_i_reg <= 0;
pilot_q_reg <= 0;
pilot_iq_phase[0] <= 0; pilot_iq_phase[1] <= 0; pilot_iq_phase[2] <= 0; pilot_iq_phase[3] <= 0;
prod_in_strobe <= 0;
@ -502,14 +548,17 @@ always @(posedge clock) begin
lts_raddr <= 62;
lts_in_stb <= 0;
lts_div_in_stb <= 0;
state <= S_UPDATE_DC_LTS;
// Always smooth legacy channel
state <= S_SMOOTH_CH_DC;
end else begin
lts_waddr <= lts_waddr + 1;
end
end
end
S_UPDATE_DC_LTS: begin
// 802.11-2012.pdf: 20.3.9.4.3 Table 20-11
// channel estimate smoothing (averaging length = 5)
S_SMOOTH_CH_DC: begin
if(lts_div_in_stb == 1) begin
lts_div_in_stb <= 0;
end else if(lts_raddr == 4) begin
@ -528,7 +577,7 @@ always @(posedge clock) begin
lts_waddr <= 37;
lts_raddr <= 38;
lts_in_stb <= 0;
state <= S_MV_AVG_LTS;
state <= S_SMOOTH_CH_LTS;
end else if(lts_div_out_stb == 1) begin
lts_i_in <= lts_div_i[15:0];
lts_q_in <= lts_div_q[15:0];
@ -538,7 +587,9 @@ always @(posedge clock) begin
end
S_MV_AVG_LTS: begin
// 802.11-2012.pdf: 20.3.9.4.3 Table 20-11
// channel estimate smoothing (averaging length = 5)
S_SMOOTH_CH_LTS: begin
if(lts_raddr == 42) begin
lts_sum_i <= lts_sum_1_3_i;
lts_sum_q <= lts_sum_1_3_q;
@ -609,7 +660,9 @@ always @(posedge clock) begin
pilot_sum_i <= 0;
pilot_sum_q <= 0;
pilot_count <= 0;
pilot_count1 <= 0;
pilot_count2 <= 0;
cpe <= 0;
in_waddr <= 0;
in_raddr <= 0;
input_i <= 0;
@ -640,7 +693,7 @@ always @(posedge clock) begin
pilot_mask <= {pilot_mask[0], pilot_mask[63:1]};
if (pilot_mask[0]) begin
pilot_count <= pilot_count + 1;
pilot_count1 <= pilot_count1 + 1;
current_polarity <= {current_polarity[0],
current_polarity[3:1]};
// obtain the conjugate of current pilot sub carrier
@ -662,34 +715,90 @@ always @(posedge clock) begin
if (pilot_out_stb) begin
pilot_sum_i <= pilot_sum_i + pilot_i;
pilot_sum_q <= pilot_sum_q + pilot_q;
if (pilot_count == 4) begin
phase_in_stb <= 1;
end else begin
phase_in_stb <= 0;
end
pilot_i_reg <= pilot_i;
pilot_q_reg <= pilot_q;
phase_in_stb <= 1;
end else begin
phase_in_stb <= 0;
end
if (phase_out_stb) begin
pilot_count2 <= pilot_count2 + 1;
pilot_iq_phase[pilot_count2] <= phase_out;
`ifdef DEBUG_PRINT
$display("[PILOT OFFSET] %d", phase_out);
`endif
pilot_phase <= phase_out;
end else if (pilot_count2 > 3) begin
pilot_count2 <= pilot_count2 + 1;
end
if (pilot_count2 == 8) begin
pilot_count1 <= 0;
pilot_count2 <= 0;
cpe <= {(cpe[15] == 0 ? 2'b00:2'b11),cpe[15:2]};
Sxy <= 0;
state <= S_CALC_SAMPL_OFFSET;
end else if (pilot_count2 > 3) begin
// sampling rate offset (SFO) is calculated as pilot phase error
if(pilot_sum_i < 0 && pilot_sum_q > 0 && pilot_iq_phase[pilot_count2[1:0]] < 0) begin
cpe = cpe + pilot_iq_phase[pilot_count2[1:0]] + 3217;
end else if(pilot_sum_i < 0 && pilot_sum_q < 0 && pilot_iq_phase[pilot_count2[1:0]] > 0) begin
cpe = cpe + pilot_iq_phase[pilot_count2[1:0]] - 3217;
end else begin
cpe = cpe + pilot_iq_phase[pilot_count2[1:0]];
end
end
end
S_CALC_SAMPL_OFFSET: begin
if (pilot_count1 < 4) begin
// sampling rate offset (SFO) is calculated as pilot phase error
if(cpe > 804 && pilot_iq_phase[pilot_count1] < 0) begin
pilot_phase_err <= pilot_iq_phase[pilot_count1] - cpe + 3217;
end else if(cpe < -804 && pilot_iq_phase[pilot_count1] > 0) begin
pilot_phase_err <= pilot_iq_phase[pilot_count1] - cpe - 3217;
end else begin
pilot_phase_err <= pilot_iq_phase[pilot_count1] - cpe;
end
pilot_count1 <= pilot_count1 + 1;
end
if(pilot_count1 == 1) begin
Sxy <= Sxy + 7*pilot_phase_err;
end else if(pilot_count1 == 2) begin
Sxy <= Sxy + 21*pilot_phase_err;
end else if(pilot_count1 == 3) begin
Sxy <= Sxy + -21*pilot_phase_err;
end else if(pilot_count1 == 4) begin
Sxy <= Sxy + -7*pilot_phase_err;
in_raddr <= 0;
sym_idx <= 0;
lvpe_in_stb <= 0;
// compensate for RAM read delay
lts_raddr <= 1;
rot_in_stb <= 0;
num_output <= 0;
state <= S_ADJUST_FREQ_OFFSET;
state <= S_ADJUST_FREQ_and_SAMPL_OFFSET;
end
// Sx² = ∑(x-x̄)*(x-x̄) = ∑x² = (7² + 21² + (-21)² + (-7)²) = 980
// phase error gradient (PEG) = Sxy/Sx²
end
S_ADJUST_FREQ_OFFSET: begin
S_ADJUST_FREQ_and_SAMPL_OFFSET: begin
if (sym_idx < 64) begin
sym_idx <= sym_idx + 1;
lvpe_in_stb <= 1;
end else begin
lvpe_in_stb <= 0;
end
// first rotate, then normalize by avg LTS
if (in_raddr < 64) begin
in_raddr <= in_raddr + 1;
if (lvpe_out_stb) begin
phase_err <= cpe + lvpe[15:0];
rot_in_stb <= 1;
in_raddr <= in_raddr + 1;
end else begin
rot_in_stb <= 0;
end
@ -738,7 +847,12 @@ always @(posedge clock) begin
lts_raddr <= 62;
lts_in_stb <= 0;
lts_div_in_stb <= 0;
state <= S_UPDATE_DC_LTS;
// Depending on smoothing bit in HT-SIG, smooth the channel
if(ht_smoothing) begin
state <= S_SMOOTH_CH_DC;
end else begin
state <= S_GET_POLARITY;
end
end else begin
lts_waddr <= lts_waddr + 1;
end

5
verilog/ofdm_decoder.v
View File

@ -14,6 +14,8 @@ module ofdm_decoder
input [31:0] num_bits_to_decode,
output [5:0] demod_out,
output [5:0] demod_soft_bits,
output [3:0] demod_soft_bits_pos,
output demod_out_strobe,
output [7:0] deinterleave_erase_out,
@ -29,9 +31,6 @@ module ofdm_decoder
output byte_out_strobe
);
wire [5:0] demod_soft_bits;
wire [3:0] demod_soft_bits_pos;
reg conv_in_stb, conv_in_stb_dly, do_descramble_dly;
reg [2:0] conv_in0, conv_in0_dly;
reg [2:0] conv_in1, conv_in1_dly;

10
verilog/openofdm_rx.v
View File

@ -25,6 +25,8 @@
output wire ht_unsupport,
output wire [7:0] pkt_rate,
output wire [15:0] pkt_len,
output ht_aggr,
output ht_aggr_last,
output wire ht_sgi,
// output wire [15:0] pkt_len_total, // for interface to byte_to_word.v in rx_intf.v
output wire byte_out_strobe,
@ -105,7 +107,7 @@
dot11 # (
) dot11_i (
.clock(s00_axi_aclk),
.enable( ~slv_reg1[0] ),
.enable( 1 ),
//.reset ( (~s00_axi_aresetn)|slv_reg0[0]|openofdm_core_rst ),
.reset ( (~s00_axi_aresetn)|slv_reg0[0] ),
@ -117,6 +119,7 @@
.sample_in(sample_in),
.sample_in_strobe(sample_in_strobe),
.soft_decoding(slv_reg4[0]),
.force_ht_smoothing(slv_reg1[0]),
// OUTPUT: bytes and FCS status
.demod_is_ongoing(demod_is_ongoing),
@ -181,7 +184,8 @@
.ht_len(),
.ht_smoothing(),
.ht_not_sounding(),
.ht_aggregation(),
.ht_aggr(ht_aggr),
.ht_aggr_last(ht_aggr_last),
.ht_stbc(),
.ht_fec_coding(),
.ht_sgi(ht_sgi),
@ -190,6 +194,8 @@
// decoding pipeline
.demod_out(),
.demod_soft_bits(),
.demod_soft_bits_pos(),
.demod_out_strobe(),
.deinterleave_erase_out(),

14
verilog/phase.v
View File

@ -14,7 +14,7 @@ module phase
input input_strobe,
// [-pi, pi) scaled up by 512
output reg signed [31:0] phase,
output reg signed [15:0] phase,
output output_strobe
);
`include "common_params.v"
@ -25,6 +25,10 @@ reg [DATA_WIDTH-1:0] abs_i;
reg [DATA_WIDTH-1:0] abs_q;
reg [DATA_WIDTH-1:0] max;
reg [DATA_WIDTH-1:0] min;
wire [DATA_WIDTH-1:0] dividend;
wire [DATA_WIDTH-`ATAN_LUT_LEN_SHIFT-1:0] divisor;
assign dividend = (max > 4194304) ? min : {min[DATA_WIDTH-`ATAN_LUT_LEN_SHIFT-1:0], {`ATAN_LUT_LEN_SHIFT{1'b0}}};
assign divisor = (max > 4194304) ? max[DATA_WIDTH-1:`ATAN_LUT_LEN_SHIFT] : max[DATA_WIDTH-`ATAN_LUT_LEN_SHIFT-1:0];
wire div_in_stb;
@ -34,7 +38,7 @@ wire div_out_stb;
wire [`ATAN_LUT_LEN_SHIFT-1:0] atan_addr;
wire [`ATAN_LUT_SCALE_SHIFT-1:0] atan_data;
assign atan_addr = (quotient>255?255:quotient[`ATAN_LUT_LEN_SHIFT-1:0]);
assign atan_addr = (quotient>511?511:quotient[`ATAN_LUT_LEN_SHIFT-1:0]);
wire signed [`ATAN_LUT_SCALE_SHIFT:0] _phase = {1'b0, atan_data};
reg [2:0] quadrant;
@ -66,15 +70,15 @@ divider div_inst (
.enable(enable),
.reset(reset),
.dividend(min),
.divisor({{(`ATAN_LUT_LEN_SHIFT-8){1'b0}}, max[31:`ATAN_LUT_LEN_SHIFT]}),
.dividend(dividend),
.divisor({{(`ATAN_LUT_LEN_SHIFT-8){1'b0}}, divisor}),
.input_strobe(div_in_stb),
.quotient(quotient),
.output_strobe(div_out_stb)
);
delayT #(.DATA_WIDTH(3), .DELAY(36)) quadrant_inst (
delayT #(.DATA_WIDTH(3), .DELAY(37)) quadrant_inst (
.clock(clock),
.reset(reset),

18
verilog/rotate.v
View File

@ -10,7 +10,7 @@ module rotate
input [15:0] in_q,
// [-PI, PI]
// scaled up by ATAN_LUT_SCALE_SHIFT
input signed [31:0] phase,
input signed [15:0] phase,
input input_strobe,
output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
@ -22,15 +22,15 @@ module rotate
);
`include "common_params.v"
reg [31:0] phase_delayed;
reg [31:0] phase_abs;
reg [15:0] phase_delayed;
reg [15:0] phase_abs;
reg [2:0] quadrant;
reg [2:0] quadrant_delayed;
wire [15:0] in_i_delayed;
wire [15:0] in_q_delayed;
reg [31:0] actual_phase;
reg [15:0] actual_phase;
wire [15:0] raw_rot_i;
wire [15:0] raw_rot_q;
@ -100,21 +100,21 @@ always @(posedge clock) begin
`endif
// cycle 1
phase_abs <= phase[31]? ~phase+1: phase;
phase_abs <= phase[15]? ~phase+1: phase;
phase_delayed <= phase;
// cycle 2
if (phase_abs <= PI_4) begin
quadrant <= {phase_delayed[31], 2'b00};
quadrant <= {phase_delayed[15], 2'b00};
actual_phase <= phase_abs;
end else if (phase_abs <= PI_2) begin
quadrant <= {phase_delayed[31], 2'b01};
quadrant <= {phase_delayed[15], 2'b01};
actual_phase <= PI_2 - phase_abs;
end else if (phase_abs <= PI_3_4) begin
quadrant <= {phase_delayed[31], 2'b10};
quadrant <= {phase_delayed[15], 2'b10};
actual_phase <= phase_abs - PI_2;
end else begin
quadrant <= {phase_delayed[31], 2'b11};
quadrant <= {phase_delayed[15], 2'b11};
actual_phase <= PI - phase_abs;
end

190
verilog/stage_mult.v
View File

@ -4,24 +4,23 @@ module stage_mult
input enable,
input reset,
input signed [15:0] X0,
input signed [15:0] X1,
input signed [15:0] X2,
input signed [15:0] X3,
input signed [15:0] X4,
input signed [15:0] X5,
input signed [15:0] X6,
input signed [15:0] X7,
input signed [31:0] X0,
input signed [31:0] X1,
input signed [31:0] X2,
input signed [31:0] X3,
input signed [31:0] X4,
input signed [31:0] X5,
input signed [31:0] X6,
input signed [31:0] X7,
input signed [15:0] Y0,
input signed [15:0] Y1,
input signed [15:0] Y2,
input signed [15:0] Y3,
input signed [15:0] Y4,
input signed [15:0] Y5,
input signed [15:0] Y6,
input signed [15:0] Y7,
input signed [31:0] Y0,
input signed [31:0] Y1,
input signed [31:0] Y2,
input signed [31:0] Y3,
input signed [31:0] Y4,
input signed [31:0] Y5,
input signed [31:0] Y6,
input signed [31:0] Y7,
input input_strobe,
@ -29,6 +28,40 @@ module stage_mult
output output_strobe
);
wire signed [15:0] X0_q = X0[31:16];
wire signed [15:0] X0_i = X0[15:0];
wire signed [15:0] X1_q = X1[31:16];
wire signed [15:0] X1_i = X1[15:0];
wire signed [15:0] X2_q = X2[31:16];
wire signed [15:0] X2_i = X2[15:0];
wire signed [15:0] X3_q = X3[31:16];
wire signed [15:0] X3_i = X3[15:0];
wire signed [15:0] X4_q = X4[31:16];
wire signed [15:0] X4_i = X4[15:0];
wire signed [15:0] X5_q = X5[31:16];
wire signed [15:0] X5_i = X5[15:0];
wire signed [15:0] X6_q = X6[31:16];
wire signed [15:0] X6_i = X6[15:0];
wire signed [15:0] X7_q = X7[31:16];
wire signed [15:0] X7_i = X7[15:0];
wire signed [15:0] Y0_q = Y0[31:16];
wire signed [15:0] Y0_i = Y0[15:0];
wire signed [15:0] Y1_q = Y1[31:16];
wire signed [15:0] Y1_i = Y1[15:0];
wire signed [15:0] Y2_q = Y2[31:16];
wire signed [15:0] Y2_i = Y2[15:0];
wire signed [15:0] Y3_q = Y3[31:16];
wire signed [15:0] Y3_i = Y3[15:0];
wire signed [15:0] Y4_q = Y4[31:16];
wire signed [15:0] Y4_i = Y4[15:0];
wire signed [15:0] Y5_q = Y5[31:16];
wire signed [15:0] Y5_i = Y5[15:0];
wire signed [15:0] Y6_q = Y6[31:16];
wire signed [15:0] Y6_i = Y6[15:0];
wire signed [15:0] Y7_q = Y7[31:16];
wire signed [15:0] Y7_i = Y7[15:0];
wire signed [31:0] prod_0_i;
wire signed [31:0] prod_0_q;
wire signed [31:0] prod_1_i;
@ -37,52 +70,103 @@ wire signed [31:0] prod_2_i;
wire signed [31:0] prod_2_q;
wire signed [31:0] prod_3_i;
wire signed [31:0] prod_3_q;
wire signed [31:0] prod_4_i;
wire signed [31:0] prod_4_q;
wire signed [31:0] prod_5_i;
wire signed [31:0] prod_5_q;
wire signed [31:0] prod_6_i;
wire signed [31:0] prod_6_q;
wire signed [31:0] prod_7_i;
wire signed [31:0] prod_7_q;
complex_multiplier mult_inst (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X1,X0}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y1,Y0}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_0_q,prod_0_i})
complex_multiplier mult_inst1 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X0_i,X0_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y0_i,Y0_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_0_q,prod_0_i})
);
complex_multiplier mult_inst2 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X3,X2}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y3,Y2}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_1_q,prod_1_i})
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X1_i,X1_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y1_i,Y1_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_1_q,prod_1_i})
);
complex_multiplier mult_inst3 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X5,X4}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y5,Y4}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_2_q,prod_2_i})
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X2_i,X2_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y2_i,Y2_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_2_q,prod_2_i})
);
complex_multiplier mult_inst4 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X7,X6}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y7,Y6}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_3_q,prod_3_i})
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X3_i,X3_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y3_i,Y3_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_3_q,prod_3_i})
);
complex_multiplier mult_inst5 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X4_i,X4_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y4_i,Y4_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_4_q,prod_4_i})
);
complex_multiplier mult_inst6 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X5_i,X5_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y5_i,Y5_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_5_q,prod_5_i})
);
complex_multiplier mult_inst7 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X6_i,X6_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y6_i,Y6_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_6_q,prod_6_i})
);
complex_multiplier mult_inst8 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X7_i,X7_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y7_i,Y7_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_7_q,prod_7_i})
);
reg signed [31:0] sum_i1;
reg signed [31:0] sum_i2;
reg signed [31:0] sum_i3;
reg signed [31:0] sum_i4;
reg signed [31:0] sum_q1;
reg signed [31:0] sum_q2;
reg signed [31:0] sum_q3;
reg signed [31:0] sum_q4;
delayT #(.DATA_WIDTH(1), .DELAY(5)) sum_delay_inst (
.clock(clock),
@ -97,16 +181,24 @@ always @(posedge clock) begin
sum <= 0;
sum_i1 <= 0;
sum_i2 <= 0;
sum_i3 <= 0;
sum_i4 <= 0;
sum_q1 <= 0;
sum_q2 <= 0;
sum_q3 <= 0;
sum_q4 <= 0;
end else if (enable) begin
sum_i1 <= prod_0_i + prod_1_i;
sum_i2 <= prod_2_i + prod_3_i;
sum_i3 <= prod_4_i + prod_5_i;
sum_i4 <= prod_6_i + prod_7_i;
sum_q1 <= prod_0_q + prod_1_q;
sum_q2 <= prod_2_q + prod_3_q;
sum_q3 <= prod_4_q + prod_5_q;
sum_q4 <= prod_6_q + prod_7_q;
sum[63:32] <= sum_i1 + sum_i2;
sum[31:0] <= sum_q1 + sum_q2;
sum[63:32] <= sum_i1 + sum_i2 + sum_i3 + sum_i4;
sum[31:0] <= sum_q1 + sum_q2 + sum_q3 + sum_q4;
end
end

251
verilog/sync_long.v
View File

@ -5,7 +5,7 @@ module sync_long (
input [31:0] sample_in,
input sample_in_strobe,
input signed [31:0] phase_offset,
input signed [15:0] phase_offset,
input short_gi,
output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
@ -20,7 +20,7 @@ module sync_long (
output reg [15:0] num_ofdm_symbol,
output reg signed [31:0] phase_offset_taken,
output reg [2:0] state
output reg [1:0] state
);
`include "common_params.v"
@ -122,44 +122,49 @@ complex_to_mag #(.DATA_WIDTH(32)) sum_mag_inst (
reg [31:0] metric_max1;
reg [(IN_BUF_LEN_SHIFT-1):0] addr1;
reg [31:0] metric_max2;
reg [(IN_BUF_LEN_SHIFT-1):0] addr2;
reg [15:0] gap;
reg [31:0] cross_corr_buf[0:15];
reg [31:0] cross_corr_buf[0:31];
reg [31:0] stage_X0;
reg [31:0] stage_X1;
reg [31:0] stage_X2;
reg [31:0] stage_X3;
reg [31:0] stage_X4;
reg [31:0] stage_X5;
reg [31:0] stage_X6;
reg [31:0] stage_X7;
reg [31:0] stage_Y0;
reg [31:0] stage_Y1;
reg [31:0] stage_Y2;
reg [31:0] stage_Y3;
reg [31:0] stage_Y4;
reg [31:0] stage_Y5;
reg [31:0] stage_Y6;
reg [31:0] stage_Y7;
stage_mult stage_mult_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.X0(stage_X0[31:16]),
.X1(stage_X0[15:0]),
.X2(stage_X1[31:16]),
.X3(stage_X1[15:0]),
.X4(stage_X2[31:16]),
.X5(stage_X2[15:0]),
.X6(stage_X3[31:16]),
.X7(stage_X3[15:0]),
.X0(stage_X0),
.X1(stage_X1),
.X2(stage_X2),
.X3(stage_X3),
.X4(stage_X4),
.X5(stage_X5),
.X6(stage_X6),
.X7(stage_X7),
.Y0(stage_Y0[31:16]),
.Y1(stage_Y0[15:0]),
.Y2(stage_Y1[31:16]),
.Y3(stage_Y1[15:0]),
.Y4(stage_Y2[31:16]),
.Y5(stage_Y2[15:0]),
.Y6(stage_Y3[31:16]),
.Y7(stage_Y3[15:0]),
.Y0(stage_Y0),
.Y1(stage_Y1),
.Y2(stage_Y2),
.Y3(stage_Y3),
.Y4(stage_Y4),
.Y5(stage_Y5),
.Y6(stage_Y6),
.Y7(stage_Y7),
.input_strobe(mult_strobe),
@ -169,9 +174,8 @@ stage_mult stage_mult_inst (
localparam S_SKIPPING = 0;
localparam S_WAIT_FOR_FIRST_PEAK = 1;
localparam S_WAIT_FOR_SECOND_PEAK = 2;
localparam S_IDLE = 3;
localparam S_FFT = 4;
localparam S_IDLE = 2;
localparam S_FFT = 3;
reg fft_start;
//wire fft_start_delayed;
@ -291,7 +295,7 @@ integer i;
integer j;
always @(posedge clock) begin
if (reset) begin
for (j = 0; j < 16; j= j+1) begin
for (j = 0; j < 32; j= j+1) begin
cross_corr_buf[j] <= 0;
end
do_clear();
@ -323,53 +327,27 @@ always @(posedge clock) begin
addr1 <= in_raddr - 1;
end
if (num_sample >= 64) begin
if (num_sample >= 88) begin
long_preamble_detected <= 1;
num_sample <= 0;
addr2 <= 0;
state <= S_WAIT_FOR_SECOND_PEAK;
mult_strobe <= 0;
sum_stb <= 0;
// offset it by the length of cross correlation buffer
// size
in_raddr <= addr1 - 32;
num_input_consumed <= addr1 - 32;
in_offset <= 0;
num_ofdm_symbol <= 0;
phase_correction <= 0;
next_phase_correction <= phase_offset;
phase_offset_taken <= phase_offset;
state <= S_FFT;
end else if (metric_stb) begin
num_sample <= num_sample + 1;
end
end
S_WAIT_FOR_SECOND_PEAK: begin
do_mult();
if (metric_stb && (metric > metric_max2)) begin
metric_max2 <= metric;
addr2 <= in_raddr - 1;
end
gap <= addr2 - addr1;
if (num_sample >= 64) begin
`ifdef DEBUG_PRINT
$display("PEAK GAP: %d (%d - %d)", gap, addr2, addr1);
$display("PHASE OFFSET: %d", phase_offset);
`endif
if (gap > 62 && gap < 66) begin
long_preamble_detected <= 1;
num_sample <= 0;
mult_strobe <= 0;
sum_stb <= 0;
// offset it by the length of cross correlation buffer
// size
in_raddr <= addr1 - 16;
num_input_consumed <= addr1 - 16;
in_offset <= 0;
num_ofdm_symbol <= 0;
phase_correction <= 0;
next_phase_correction <= phase_offset;
phase_offset_taken <= phase_offset;
state <= S_FFT;
end else begin
state <= S_IDLE;
end
end else if (metric_stb) begin
num_sample <= num_sample + 1;
end
end
S_FFT: begin
if (long_preamble_detected) begin
`ifdef DEBUG_PRINT
@ -378,7 +356,7 @@ always @(posedge clock) begin
long_preamble_detected <= 0;
end
if (~fft_loading && num_input_avail > 64) begin
if (~fft_loading && num_input_avail > 88) begin
fft_start <= 1;
in_offset <= 0;
end
@ -393,18 +371,30 @@ always @(posedge clock) begin
if (phase_offset > 0) begin
if (next_phase_correction > PI) begin
phase_correction <= next_phase_correction - DOUBLE_PI;
next_phase_correction <= next_phase_correction + phase_offset - DOUBLE_PI;
if(in_offset == 63 && num_ofdm_symbol > 0)
next_phase_correction <= next_phase_correction - DOUBLE_PI + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
else
next_phase_correction <= next_phase_correction - DOUBLE_PI + phase_offset;
end else begin
phase_correction <= next_phase_correction;
next_phase_correction <= next_phase_correction + phase_offset;
if(in_offset == 63 && num_ofdm_symbol > 0)
next_phase_correction <= next_phase_correction + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
else
next_phase_correction <= next_phase_correction + phase_offset;
end
end else begin
if (next_phase_correction < -PI) begin
phase_correction <= next_phase_correction + DOUBLE_PI;
next_phase_correction <= next_phase_correction + DOUBLE_PI + phase_offset;
if(in_offset == 63 && num_ofdm_symbol > 0)
next_phase_correction <= next_phase_correction + DOUBLE_PI + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
else
next_phase_correction <= next_phase_correction + DOUBLE_PI + phase_offset;
end else begin
phase_correction <= next_phase_correction;
next_phase_correction <= next_phase_correction + phase_offset;
if(in_offset == 63 && num_ofdm_symbol > 0)
next_phase_correction <= next_phase_correction + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
else
next_phase_correction <= next_phase_correction + phase_offset;
end
end
end
@ -454,8 +444,8 @@ integer do_mult_i;
task do_mult; begin
// cross correlation of the first 16 samples of LTS
if (sample_in_strobe) begin
cross_corr_buf[15] <= sample_in;
for (do_mult_i = 0; do_mult_i < 15; do_mult_i = do_mult_i+1) begin
cross_corr_buf[31] <= sample_in;
for (do_mult_i = 0; do_mult_i < 31; do_mult_i = do_mult_i+1) begin
cross_corr_buf[do_mult_i] <= cross_corr_buf[do_mult_i+1];
end
@ -468,66 +458,82 @@ task do_mult; begin
stage_X1 <= cross_corr_buf[2];
stage_X2 <= cross_corr_buf[3];
stage_X3 <= cross_corr_buf[4];
stage_X4 <= cross_corr_buf[5];
stage_X5 <= cross_corr_buf[6];
stage_X6 <= cross_corr_buf[7];
stage_X7 <= cross_corr_buf[8];
stage_Y0[31:16] <= 156;
stage_Y0[15:0] <= 0;
stage_Y1[31:16] <= -5;
stage_Y1[15:0] <= 120;
stage_Y2[31:16] <= 40;
stage_Y2[15:0] <= 111;
stage_Y3[31:16] <= 97;
stage_Y3[15:0] <= -83;
stage_Y0 <= { 16'd156, 16'd0};
stage_Y1 <= {-16'd5, 16'd120};
stage_Y2 <= { 16'd40, 16'd111};
stage_Y3 <= { 16'd97, -16'd83};
stage_Y4 <= { 16'd21, -16'd28};
stage_Y5 <= { 16'd60, 16'd88};
stage_Y6 <= {-16'd115, 16'd55};
stage_Y7 <= {-16'd38, 16'd106};
mult_strobe <= 1;
mult_stage <= 1;
end
if (mult_stage == 1) begin
stage_X0 <= cross_corr_buf[4];
stage_X1 <= cross_corr_buf[5];
stage_X2 <= cross_corr_buf[6];
stage_X3 <= cross_corr_buf[7];
stage_Y0[31:16] <= 21;
stage_Y0[15:0] <= -28;
stage_Y1[31:16] <= 60;
stage_Y1[15:0] <= 88;
stage_Y2[31:16] <= -115;
stage_Y2[15:0] <= 55;
stage_Y3[31:16] <= -38;
stage_Y3[15:0] <= 106;
mult_stage <= 2;
end else if (mult_stage == 2) begin
stage_X0 <= cross_corr_buf[8];
stage_X1 <= cross_corr_buf[9];
stage_X2 <= cross_corr_buf[10];
stage_X3 <= cross_corr_buf[11];
stage_X4 <= cross_corr_buf[12];
stage_X5 <= cross_corr_buf[13];
stage_X6 <= cross_corr_buf[14];
stage_X7 <= cross_corr_buf[15];
stage_Y0[31:16] <= 98;
stage_Y0[15:0] <= 26;
stage_Y1[31:16] <= 53;
stage_Y1[15:0] <= -4;
stage_Y2[31:16] <= 1;
stage_Y2[15:0] <= 115;
stage_Y3[31:16] <= -137;
stage_Y3[15:0] <= 47;
stage_Y0 <= { 16'd98, 16'd26};
stage_Y1 <= { 16'd53, -16'd4};
stage_Y2 <= { 16'd1, 16'd115};
stage_Y3 <= {-16'd137, 16'd47};
stage_Y4 <= { 16'd24, 16'd59};
stage_Y5 <= { 16'd59, 16'd15};
stage_Y6 <= {-16'd22, -16'd161};
stage_Y7 <= { 16'd119, 16'd4};
mult_stage <= 2;
end else if (mult_stage == 2) begin
stage_X0 <= cross_corr_buf[16];
stage_X1 <= cross_corr_buf[17];
stage_X2 <= cross_corr_buf[18];
stage_X3 <= cross_corr_buf[19];
stage_X4 <= cross_corr_buf[20];
stage_X5 <= cross_corr_buf[21];
stage_X6 <= cross_corr_buf[22];
stage_X7 <= cross_corr_buf[23];
stage_Y0 <= { 16'd62, 16'd62};
stage_Y1 <= { 16'd37, -16'd98};
stage_Y2 <= {-16'd57, -16'd39};
stage_Y3 <= {-16'd131, -16'd65};
stage_Y4 <= { 16'd82, -16'd92};
stage_Y5 <= { 16'd70, -16'd14};
stage_Y6 <= {-16'd60, -16'd81};
stage_Y7 <= {-16'd56, 16'd22};
mult_stage <= 3;
end else if (mult_stage == 3) begin
stage_X0 <= cross_corr_buf[12];
stage_X1 <= cross_corr_buf[13];
stage_X2 <= cross_corr_buf[14];
stage_X3 <= cross_corr_buf[15];
stage_X0 <= cross_corr_buf[24];
stage_X1 <= cross_corr_buf[25];
stage_X2 <= cross_corr_buf[26];
stage_X3 <= cross_corr_buf[27];
stage_X4 <= cross_corr_buf[28];
stage_X5 <= cross_corr_buf[29];
stage_X6 <= cross_corr_buf[30];
stage_X7 <= cross_corr_buf[31];
stage_Y0[31:16] <= 24;
stage_Y0[15:0] <= 59;
stage_Y1[31:16] <= 59;
stage_Y1[15:0] <= 15;
stage_Y2[31:16] <= -22;
stage_Y2[15:0] <= -161;
stage_Y3[31:16] <= 119;
stage_Y3[15:0] <= 4;
stage_Y0 <= {-16'd35, 16'd151};
stage_Y1 <= {-16'd122, 16'd17};
stage_Y2 <= {-16'd127, 16'd21};
stage_Y3 <= { 16'd75, 16'd74};
stage_Y4 <= {-16'd3, -16'd54};
stage_Y5 <= {-16'd92, -16'd115};
stage_Y6 <= { 16'd92, -16'd106};
stage_Y7 <= { 16'd12, -16'd98};
mult_stage <= 4;
end else if (mult_stage == 4) begin
@ -553,7 +559,6 @@ end
endtask
task do_clear; begin
gap <= 0;
in_waddr <= 0;
in_raddr <= 0;
@ -575,8 +580,6 @@ task do_clear; begin
metric_max1 <= 0;
addr1 <= 0;
metric_max2 <= 0;
addr2 <= 0;
mult_stage <= 0;
@ -594,11 +597,19 @@ task do_clear; begin
stage_X1 <= 0;
stage_X2 <= 0;
stage_X3 <= 0;
stage_X4 <= 0;
stage_X5 <= 0;
stage_X6 <= 0;
stage_X7 <= 0;
stage_Y0 <= 0;
stage_Y1 <= 0;
stage_Y2 <= 0;
stage_Y3 <= 0;
stage_Y4 <= 0;
stage_Y5 <= 0;
stage_Y6 <= 0;
stage_Y7 <= 0;
end
endtask

16
verilog/sync_short.v
View File

@ -12,14 +12,14 @@ module sync_short (
output reg short_preamble_detected,
input [31:0] phase_out,
input [15:0] phase_out,
input phase_out_stb,
output [31:0] phase_in_i,
output [31:0] phase_in_q,
output phase_in_stb,
output reg signed [31:0] phase_offset
output reg signed [15:0] phase_offset
);
`include "common_params.v"
@ -52,7 +52,8 @@ wire [31:0] freq_offset_i;
wire [31:0] freq_offset_q;
wire freq_offset_stb;
reg [31:0] phase_out_neg;
reg [15:0] phase_out_neg;
reg [15:0] phase_offset_neg;
wire [31:0] delay_prod_avg_mag;
wire delay_prod_avg_mag_stb;
@ -81,7 +82,8 @@ reg has_neg;
// =============save signal to file for matlab bit-true comparison===========
integer file_open_trigger = 0;
integer mag_sq_fd, mag_sq_avg_fd, prod_fd, prod_avg_fd, phase_in_fd, phase_out_fd, delay_prod_avg_mag_fd;
wire signed [31:0] prod_i, prod_q, prod_avg_i, prod_avg_q, phase_in_i_signed, phase_in_q_signed, phase_out_signed;
wire signed [31:0] prod_i, prod_q, prod_avg_i, prod_avg_q, phase_in_i_signed, phase_in_q_signed;
wire signed [15:0] phase_out_signed;
assign prod_i = prod[63:32];
assign prod_q = prod[31:0];
assign prod_avg_i = prod_avg[63:32];
@ -270,6 +272,7 @@ always @(posedge clock) begin
has_neg <= neg_count > min_neg;
phase_out_neg <= ~phase_out + 1;
phase_offset_neg <= {{4{phase_out[15]}}, phase_out[15:4]};
prod_thres <= {1'b0, mag_sq_avg[31:1]} + {2'b0, mag_sq_avg[31:2]};
@ -285,7 +288,10 @@ always @(posedge clock) begin
pos_count <= 0;
neg_count <= 0;
short_preamble_detected <= has_pos & has_neg;
phase_offset <= {{4{phase_out_neg[31]}}, phase_out_neg[31:4]};
if(phase_out_neg[3] == 0) // E.g. 131/16 = 8.1875 -> 8, -138/16 = -8.625 -> -9
phase_offset <= {{4{phase_out_neg[15]}}, phase_out_neg[15:4]};
else // E.g. -131/16 = -8.1875 -> -8, 138/16 = 8.625 -> 9
phase_offset <= ~phase_offset_neg + 1;
end else begin
plateau_count <= plateau_count + 1;
short_preamble_detected <= 0;