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Add phy len indication for decoding latency prediciton:

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Add n_ofdm_sym, n_bit_in_last_sym and phy_len_valid to openofdm_rx ip
This commit is contained in:
Xianjun Jiao 2023-01-09 15:28:25 +01:00
parent 4359e4f96d
commit 73475306b7
4 changed files with 155 additions and 1 deletions
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10
openofdm_rx.tcl
View File

@ -263,7 +263,7 @@ set files [list \
"[file normalize "$origin_dir/verilog/crc32.v"]"\
"[file normalize "$origin_dir/verilog/deinterleave.v"]"\
"[file normalize "$origin_dir/verilog/delayT.v"]"\
"[file normalize "$origin_dir/verilog/delay_sample.v"]"\
"[file normalize "$origin_dir/verilog/fifo_sample_delay.v"]"\
"[file normalize "$origin_dir/verilog/common_defs.v"]"\
"[file normalize "$origin_dir/verilog/demodulate.v"]"\
"[file normalize "$origin_dir/verilog/descramble.v"]"\
@ -272,6 +272,8 @@ set files [list \
"[file normalize "$origin_dir/verilog/equalizer.v"]"\
"[file normalize "$origin_dir/verilog/ht_sig_crc.v"]"\
"[file normalize "$origin_dir/verilog/moving_avg.v"]"\
"[file normalize "$origin_dir/verilog/mv_avg.v"]"\
"[file normalize "$origin_dir/verilog/mv_avg_dual_ch.v"]"\
"[file normalize "$origin_dir/verilog/ofdm_decoder.v"]"\
"[file normalize "$origin_dir/verilog/openofdm_rx_s_axi.v"]"\
"[file normalize "$origin_dir/verilog/phase.v"]"\
@ -283,6 +285,7 @@ set files [list \
"[file normalize "$origin_dir/verilog/openofdm_rx.v"]"\
"[file normalize "$origin_dir/verilog/running_sum_dual_ch.v"]"\
"[file normalize "$origin_dir/verilog/signal_watchdog.v"]"\
"[file normalize "$origin_dir/verilog/phy_len_calculation.v"]"\
"[file normalize "$origin_dir/ip_repo/complex_multiplier/complex_multiplier.xci"]"\
"[file normalize "$origin_dir/ip_repo/atan_lut/atan_lut.coe"]"\
"[file normalize "$origin_dir/ip_repo/atan_lut/atan_lut.xci"]"\
@ -328,6 +331,11 @@ set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "0" -objects $file_obj
set file "phy_len_calculation.v"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "used_in" -value "synthesis simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "0" -objects $file_obj
# Set 'sources_1' fileset file properties for local files
# Set 'sources_1' fileset properties

21
verilog/dot11.v
View File

@ -99,6 +99,10 @@ module dot11 (
output [1:0] ht_num_ext,
output reg ht_sig_crc_ok,
output [14:0] n_ofdm_sym,//max 20166 = (22+65535*8)/26 (max ht len 65535 in sig, min ndbps 26 for mcs0)
output [9:0] n_bit_in_last_sym,//max ht ndbps 260 (ht mcs7)
output phy_len_valid,
// decoding pipeline
output [5:0] demod_out,
output [5:0] demod_soft_bits,
@ -121,6 +125,9 @@ module dot11 (
`include "common_params.v"
wire [19:0] n_bit_in_last_sym_tmp;
assign n_bit_in_last_sym = n_bit_in_last_sym_tmp[9:0];
////////////////////////////////////////////////////////////////////////////////
// extra info output to ease side info and viterbi state monitor
////////////////////////////////////////////////////////////////////////////////
@ -460,6 +467,20 @@ crc32 fcs_inst (
.crc_out(pkt_fcs)
);
phy_len_calculation phy_len_calculation_inst(
.clock(clock),
.reset(reset | long_preamble_detected),
.enable(),
.state(state),
.old_state(old_state),
.num_bits_to_decode(num_bits_to_decode),
.pkt_rate(pkt_rate),//bit [7] 1 means ht; 0 means non-ht
.n_ofdm_sym(n_ofdm_sym),//max 20166 = (22+65535*8)/26
.n_bit_in_last_sym(n_bit_in_last_sym_tmp),//max ht ndbps 260
.phy_len_valid(phy_len_valid)
);
always @(posedge clock) begin
if (reset) begin

9
verilog/openofdm_rx.v
View File

@ -47,6 +47,11 @@
output wire equalizer_valid,
output wire ofdm_symbol_eq_out_pulse,
// phy len info
output [14:0] n_ofdm_sym,//max 20166 = (22+65535*8)/26 (max ht len 65535 in sig, min ndbps 26 for mcs0)
output [9:0] n_bit_in_last_sym,//max ht ndbps 260 (ht mcs7)
output phy_len_valid,
// axi lite based register configuration interface
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
@ -167,6 +172,10 @@
.fcs_out_strobe(fcs_out_strobe),
.fcs_ok(fcs_ok),
.n_ofdm_sym(n_ofdm_sym),//max 20166 = (22+65535*8)/26 (max ht len 65535 in sig, min ndbps 26 for mcs0)
.n_bit_in_last_sym(n_bit_in_last_sym),//max ht ndbps 260 (ht mcs7)
.phy_len_valid(phy_len_valid),
/////////////////////////////////////////////////////////
// DEBUG PORTS
/////////////////////////////////////////////////////////

116
verilog/phy_len_calculation.v Normal file
View File

@ -0,0 +1,116 @@
// Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be;
// Calculate PHY related info:
// n_ofdm_sym, n_bit_in_last_sym (for decoding latency prediction)
module phy_len_calculation
(
input clock,
input reset,
input enable,
input [4:0] state,
input [4:0] old_state,
input [19:0] num_bits_to_decode,
input [7:0] pkt_rate,//bit [7] 1 means ht; 0 means non-ht
output reg [14:0] n_ofdm_sym,//max 20166 = (22+65535*8)/26
output reg [19:0] n_bit_in_last_sym,//max ht ndbps 260
output reg phy_len_valid
);
reg start_calculation;
reg end_calculation;
reg [8:0] n_dbps;
// lookup table for N_DBPS (Number of data bits per OFDM symbol)
always @( pkt_rate[7],pkt_rate[3:0] )
begin
case ({pkt_rate[7],pkt_rate[3:0]})
5'b01011 : begin //non-ht 6Mbps
n_dbps = 24;
end
5'b01111 : begin //non-ht 9Mbps
n_dbps = 36;
end
5'b01010 : begin //non-ht 12Mbps
n_dbps = 48;
end
5'b01110 : begin //non-ht 18Mbps
n_dbps = 72;
end
5'b01001 : begin //non-ht 24Mbps
n_dbps = 96;
end
5'b01101 : begin //non-ht 36Mbps
n_dbps = 144;
end
5'b01000 : begin //non-ht 48Mbps
n_dbps = 192;
end
5'b01100 : begin //non-ht 54Mbps
n_dbps = 216;
end
5'b10000 : begin //ht mcs 0
n_dbps = 26;
end
5'b10001 : begin //ht mcs 1
n_dbps = 52;
end
5'b10010 : begin //ht mcs 2
n_dbps = 78;
end
5'b10011 : begin //ht mcs 3
n_dbps = 104;
end
5'b10100 : begin //ht mcs 4
n_dbps = 156;
end
5'b10101 : begin //ht mcs 5
n_dbps = 208;
end
5'b10110 : begin //ht mcs 6
n_dbps = 234;
end
5'b10111 : begin //ht mcs 7
n_dbps = 260;
end
default: begin
n_dbps = 0;
end
endcase
end
`include "common_params.v"
always @(posedge clock) begin
if (reset) begin
n_ofdm_sym <= 1;
n_bit_in_last_sym <= 130; // half of max num bits to have a rough mid-point estimation in case no calculation happen
phy_len_valid <= 0;
start_calculation <= 0;
end_calculation <= 0;
end else begin
if ( (state != S_HT_SIG_ERROR && old_state == S_CHECK_HT_SIG) || ((state == S_DECODE_DATA && (old_state == S_CHECK_SIGNAL || old_state == S_DETECT_HT))) ) begin
n_bit_in_last_sym <= num_bits_to_decode;
if (num_bits_to_decode <= n_dbps) begin
phy_len_valid <= 1;
end_calculation <= 1;
end else begin
start_calculation <= 1;
end
end
if (start_calculation == 1 && end_calculation != 1) begin
if (n_bit_in_last_sym <= n_dbps) begin
phy_len_valid <= 1;
end_calculation <= 1;
end else begin
n_bit_in_last_sym <= n_bit_in_last_sym - n_dbps;
n_ofdm_sym = n_ofdm_sym + 1;
end
end
end
end
endmodule