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Let sync short restart earlier before the end of current packet decoding, so that the next packet can come earlier (smaller inter packet gap is achieved)

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This commit is contained in:
Xianjun Jiao 2023-01-09 14:48:34 +01:00
parent e65ee43101
commit 8e59685c65
2 changed files with 19 additions and 40 deletions
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17
verilog/dot11.v
View File

@ -211,7 +211,8 @@ phase phase_inst (
reg sync_short_reset;
reg sync_long_reset;
wire sync_short_enable = state == S_SYNC_SHORT;
// wire sync_short_enable = state == S_SYNC_SHORT;
wire sync_short_enable = 1;
reg sync_long_enable;
wire [15:0] num_ofdm_symbol;
@ -343,6 +344,7 @@ sync_short sync_short_inst (
.phase_out(sync_short_phase_out),
.phase_out_stb(sync_short_phase_out_stb),
.demod_is_ongoing(demod_is_ongoing),
.short_preamble_detected(short_preamble_detected),
.phase_offset(phase_offset)
);
@ -533,6 +535,8 @@ always @(posedge clock) begin
case(state)
S_WAIT_POWER_TRIGGER: begin
sync_short_reset <= 0;
pkt_begin <= 0;
pkt_ht <= 0;
crc_reset <= 0;
@ -551,19 +555,17 @@ always @(posedge clock) begin
`ifdef DEBUG_PRINT
$display("Power triggered.");
`endif
sync_short_reset <= 1;
// sync_short_reset <= 1;
state <= S_SYNC_SHORT;
end
end
S_SYNC_SHORT: begin
if (sync_short_reset) begin
sync_short_reset <= 0;
end
if (~power_trigger) begin
// power level drops before finding STS
state <= S_WAIT_POWER_TRIGGER;
sync_short_reset <= 1;
end
if (short_preamble_detected) begin
@ -588,10 +590,12 @@ always @(posedge clock) begin
end
if (sample_count > 320) begin
state <= S_WAIT_POWER_TRIGGER;
sync_short_reset <= 1;
end
if (~power_trigger) begin
state <= S_WAIT_POWER_TRIGGER;
sync_short_reset <= 1;
end
if (long_preamble_detected) begin
@ -609,10 +613,12 @@ always @(posedge clock) begin
byte_count <= 0;
byte_count_total <= 0;
state <= S_DECODE_SIGNAL;
sync_short_reset <= 1;
end
end
S_DECODE_SIGNAL: begin
sync_short_reset <= 0;
ofdm_reset <= 0;
if (equalizer_reset) begin
@ -677,7 +683,6 @@ always @(posedge clock) begin
end else begin
//num_bits_to_decode <= (legacy_len+3)<<4;
do_descramble <= 1;
ofdm_reset <= 1;
pkt_header_valid <= 1;
pkt_header_valid_strobe <= 1;
pkt_begin <= 1;

42
verilog/sync_short.v
View File

@ -11,6 +11,7 @@ module sync_short (
input [31:0] sample_in,
input sample_in_strobe,
input demod_is_ongoing,
output reg short_preamble_detected,
input [15:0] phase_out,
@ -48,16 +49,9 @@ reg sample_delayed_conj_stb;
wire [63:0] prod;
wire prod_stb;
reg [15:0] delay_i;
reg [15:0] delay_q_neg;
wire [63:0] prod_avg;
wire prod_avg_stb;
wire [31:0] freq_offset_i;
wire [31:0] freq_offset_q;
wire freq_offset_stb;
reg [15:0] phase_out_neg;
reg [15:0] phase_offset_neg;
@ -190,28 +184,6 @@ mv_avg_dual_ch #(.DATA_WIDTH0(32), .DATA_WIDTH1(32), .LOG2_AVG_LEN(WINDOW_SHIFT)
.data_out_valid(prod_avg_stb)
);
// // for fixing freq offset
// moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(6))
// freq_offset_i_inst (
// .clock(clock),
// .enable(enable),
// .reset(reset),
// .data_in(prod[63:32]),
// .input_strobe(prod_stb),
// .data_out(phase_in_i),
// .output_strobe(phase_in_stb)
// );
// moving_avg #(.DATA_WIDTH(32), .WINDOW_SHIFT(6))
// freq_offset_q_inst (
// .clock(clock),
// .enable(enable),
// .reset(reset),
// .data_in(prod[31:0]),
// .input_strobe(prod_stb),
// .data_out(phase_in_q)
// );
mv_avg_dual_ch #(.DATA_WIDTH0(32), .DATA_WIDTH1(32), .LOG2_AVG_LEN(6)) freq_offset_inst (
.clk(clock),
.rstn(~(reset|reset_delay1|reset_delay2|reset_delay3|reset_delay4)),
@ -260,7 +232,7 @@ always @(posedge clock) begin
plateau_count <= 0;
short_preamble_detected <= 0;
phase_offset <= 0;
phase_offset <= phase_offset; // do not clear it. sync short will reset soon after stf detected, but sync long still needs it.
end else if (enable) begin
reset_delay4 <= reset_delay3;
reset_delay3 <= reset_delay2;
@ -293,10 +265,12 @@ always @(posedge clock) begin
pos_count <= 0;
neg_count <= 0;
short_preamble_detected <= has_pos & has_neg;
if(phase_out_neg[3] == 0) // E.g. 131/16 = 8.1875 -> 8, -138/16 = -8.625 -> -9
phase_offset <= {{4{phase_out_neg[15]}}, phase_out_neg[15:4]};
else // E.g. -131/16 = -8.1875 -> -8, 138/16 = 8.625 -> 9
phase_offset <= ~phase_offset_neg + 1;
if (has_pos && has_neg && demod_is_ongoing==0) begin // only update and lock phase_offset to new value when short_preamble_detected and not start demod yet
if(phase_out_neg[3] == 0) // E.g. 131/16 = 8.1875 -> 8, -138/16 = -8.625 -> -9
phase_offset <= {{4{phase_out_neg[15]}}, phase_out_neg[15:4]};
else // E.g. -131/16 = -8.1875 -> -8, 138/16 = 8.625 -> 9
phase_offset <= ~phase_offset_neg + 1;
end
end else begin
plateau_count <= plateau_count + 1;
short_preamble_detected <= 0;