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Add fake random +/-1 input while input are 0s:

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to avoid receiver reset during self-rx-muting (packet sending)
This commit is contained in:
Xianjun Jiao 2023-01-09 15:29:33 +01:00
parent 73475306b7
commit 75979e165a
1 changed files with 11 additions and 2 deletions
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13
verilog/signal_watchdog.v
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@ -24,6 +24,7 @@ module signal_watchdog
);
wire signed [1:0] i_sign;
wire signed [1:0] q_sign;
reg signed [1:0] fake_non_dc_in_case_all_zero;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i_abs;
@ -33,8 +34,8 @@ module signal_watchdog
reg receiver_rst_reg;
wire receiver_rst_pulse;
assign i_sign = (i_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
assign q_sign = (q_data[(IQ_DATA_WIDTH-1)] ? -1 : 1);
assign i_sign = (i_data == 0? fake_non_dc_in_case_all_zero : (i_data[(IQ_DATA_WIDTH-1)] ? -1 : 1) );
assign q_sign = (q_data == 0? fake_non_dc_in_case_all_zero : (q_data[(IQ_DATA_WIDTH-1)] ? -1 : 1) );
assign running_sum_result_i_abs = (running_sum_result_i[LOG2_SUM_LEN+2-1]?(-running_sum_result_i):running_sum_result_i);
assign running_sum_result_q_abs = (running_sum_result_q[LOG2_SUM_LEN+2-1]?(-running_sum_result_q):running_sum_result_q);
@ -48,8 +49,16 @@ module signal_watchdog
always @(posedge clk) begin
if (~rstn) begin
receiver_rst_reg <= 0;
fake_non_dc_in_case_all_zero <= 1;
end else begin
receiver_rst_reg <= receiver_rst_internal;
if (iq_valid) begin
if (fake_non_dc_in_case_all_zero == 1) begin
fake_non_dc_in_case_all_zero <= -1;
end else begin
fake_non_dc_in_case_all_zero <= 1;
end
end
end
end