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Avoid phy_len_calculation out of the watchdog reset scope to have stable value before the next long_preamble_detected

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This commit is contained in:
Xianjun Jiao 2023-01-09 15:33:57 +01:00
parent e83599a85e
commit 1b0354f85d
2 changed files with 3 additions and 1 deletions
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3
verilog/dot11.v
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@ -5,6 +5,7 @@ module dot11 (
input clock,
input enable,
input reset,
input reset_without_watchdog,
// setting registers
//input set_stb,
@ -469,7 +470,7 @@ crc32 fcs_inst (
phy_len_calculation phy_len_calculation_inst(
.clock(clock),
.reset(reset | long_preamble_detected),
.reset(reset_without_watchdog | long_preamble_detected),
.enable(),
.state(state),

1
verilog/openofdm_rx.v
View File

@ -146,6 +146,7 @@
.enable( 1 ),
//.reset ( (~s00_axi_aresetn)|slv_reg0[0]|openofdm_core_rst ),
.reset ( (~s00_axi_aresetn)|slv_reg0[0]|receiver_rst ),
.reset_without_watchdog((~s00_axi_aresetn)|slv_reg0[0]),
.power_thres(slv_reg2[10:0]),
.min_plateau(slv_reg3),