diff --git a/verilog/dot11.v b/verilog/dot11.v
index 9ada520..cebb325 100644
--- a/verilog/dot11.v
+++ b/verilog/dot11.v
@@ -5,6 +5,7 @@ module dot11 (
     input clock,
     input enable,
     input reset,
+    input reset_without_watchdog,
 
     // setting registers
     //input set_stb,
@@ -469,7 +470,7 @@ crc32 fcs_inst (
 
 phy_len_calculation phy_len_calculation_inst(
     .clock(clock),
-    .reset(reset | long_preamble_detected),
+    .reset(reset_without_watchdog | long_preamble_detected),
     .enable(),
 
     .state(state),
diff --git a/verilog/openofdm_rx.v b/verilog/openofdm_rx.v
index ca88c0d..730d8ec 100644
--- a/verilog/openofdm_rx.v
+++ b/verilog/openofdm_rx.v
@@ -146,6 +146,7 @@
 		.enable( 1 ),
 		//.reset ( (~s00_axi_aresetn)|slv_reg0[0]|openofdm_core_rst ),
 		.reset ( (~s00_axi_aresetn)|slv_reg0[0]|receiver_rst ),
+		.reset_without_watchdog((~s00_axi_aresetn)|slv_reg0[0]),
 
 		.power_thres(slv_reg2[10:0]),
 		.min_plateau(slv_reg3),