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Shrink the bits of num_bits_to_decode and deinter_out_count:

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and adapt the verilog/ofdm_decoder.v accordingly
This commit is contained in:
Xianjun Jiao 2023-01-09 15:24:42 +01:00
parent efa844bf0c
commit 8ce830c262
2 changed files with 8 additions and 11 deletions
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13
verilog/dot11.v
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@ -208,7 +208,6 @@ phase phase_inst (
);
////////////////////////////////////////////////////////////////////////////////
reg sync_short_reset;
reg sync_long_reset;
// wire sync_short_enable = state == S_SYNC_SHORT;
@ -239,7 +238,7 @@ reg [15:0] ofdm_in_i;
reg [15:0] ofdm_in_q;
reg do_descramble;
reg [31:0] num_bits_to_decode;
reg [19:0] num_bits_to_decode; //4bits + ht_len: num_bits_to_decode <= (22+(ht_len<<3));
reg short_gi;
reg [4:0] old_state;
@ -257,7 +256,6 @@ assign legacy_sig_parity = signal_bits[17];
assign legacy_sig_tail = signal_bits[23:18];
assign legacy_sig_parity_ok = ~^signal_bits[17:0];
// HT-SIG information
reg [23:0] ht_sig1;
reg [23:0] ht_sig2;
@ -274,7 +272,6 @@ assign ht_fec_coding = ht_sig2[6];
assign ht_sgi = ht_sig2[7];
assign ht_num_ext = ht_sig2[9:8];
wire ht_rsvd = ht_sig2[2];
wire [7:0] crc = ht_sig2[17:10];
wire [5:0] ht_sig_tail = ht_sig2[23:18];
@ -602,7 +599,7 @@ always @(posedge clock) begin
demod_is_ongoing <= 1;
pkt_rate <= {1'b0, 3'b0, 4'b1011};
do_descramble <= 0;
num_bits_to_decode <= 48;
num_bits_to_decode <= 24;
ofdm_reset <= 1;
ofdm_enable <= 1;
@ -644,7 +641,7 @@ always @(posedge clock) begin
"tail = %6b", legacy_sig_tail);
`endif
num_bits_to_decode <= (22+(legacy_len<<3))<<1;
num_bits_to_decode <= (22+(legacy_len<<3));
pkt_rate <= {1'b0, 3'b0, legacy_rate};
pkt_len <= legacy_len;
pkt_len_total <= legacy_len+3;
@ -719,7 +716,7 @@ always @(posedge clock) begin
if (rot_eq_count >= 4) begin
// HT-SIG detected
num_bits_to_decode <= 96;
num_bits_to_decode <= 48;
do_descramble <= 0;
state <= S_HT_SIGNAL;
end else if (normal_eq_count > 4) begin
@ -767,7 +764,7 @@ always @(posedge clock) begin
"tail = %06b", ht_sig_tail);
`endif
num_bits_to_decode <= (22+(ht_len<<3))<<1;
num_bits_to_decode <= (22+(ht_len<<3));
pkt_rate <= {1'b1, ht_mcs};
pkt_len_rem <= ht_len;
pkt_len <= ht_len;

6
verilog/ofdm_decoder.v
View File

@ -11,7 +11,7 @@ module ofdm_decoder
// decode instructions
input [7:0] rate,
input do_descramble,
input [31:0] num_bits_to_decode,
input [19:0] num_bits_to_decode, //4bits + ht_len: num_bits_to_decode <= (22+(ht_len<<3));
output [5:0] demod_out,
output [5:0] demod_soft_bits,
@ -55,7 +55,7 @@ reg [3:0] skip_bit;
reg bit_in;
reg bit_in_stb;
reg [31:0] deinter_out_count;
reg [19:0] deinter_out_count; // bitwidth same as num_bits_to_decode
//reg flush;
assign deinterleave_erase_out = {erase,deinterleave_out};
@ -159,7 +159,7 @@ always @(posedge clock) begin
deinter_out_count <= 0;
end else if (enable) begin
if (deinterleave_out_strobe) begin
deinter_out_count <= deinter_out_count + 2;
deinter_out_count <= deinter_out_count + 1;
end //else begin
// wait for finishing deinterleaving current symbol
// only do flush for non-DATA bits, such as SIG and HT-SIG, which