Change the phase control value to the most safe one

2024-12-18 21:28:07 +00:00 · 2023-01-09 15:57:28 +01:00 · 2023-01-09 15:57:28 +01:00 · 8aa784707a
commit 8aa784707a
parent b2e08ff46e
1 changed files with 1 additions and 1 deletions
--- a/verilog/dot11_tb.v
+++ b/verilog/dot11_tb.v
@ -243,7 +243,7 @@ always @(posedge clock) begin
        end
        
        // for finer sample_in_strobe phase control
-        if (clk_count == 3) begin
+        if (clk_count == 4) begin
            sample_in_strobe <= 1;
        end else begin
            sample_in_strobe <= 0;