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Merge pull request #6 from ytakeuch/dot11zynq

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fix unsigned signals to signed signals
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Jiao Xianjun 2023-01-28 12:00:50 +01:00 committed by GitHub
commit 19acdbe82f
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1 changed files with 2 additions and 2 deletions
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verilog/dot11.v
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@ -19,12 +19,12 @@ module dot11 (
//input [31:0] set_data,
// add ports for register based inputs
input [10:0] power_thres,
input signed [10:0] power_thres,
input [31:0] min_plateau,
input threshold_scale,
// INPUT: RSSI
input [10:0] rssi_half_db,
input signed [10:0] rssi_half_db,
// INPUT: I/Q sample
input [31:0] sample_in,
input sample_in_strobe,