From 7e8b44439ab04d7078965f9c8f24ef97b7136128 Mon Sep 17 00:00:00 2001 From: Yoji Takeuchi Date: Mon, 16 Jan 2023 12:56:24 +0900 Subject: [PATCH] fix unsigned signals to signed signals --- verilog/dot11.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/dot11.v b/verilog/dot11.v index c4fe855..3114dfe 100644 --- a/verilog/dot11.v +++ b/verilog/dot11.v @@ -12,11 +12,11 @@ module dot11 ( //input [31:0] set_data, // add ports for register based inputs - input [10:0] power_thres, + input signed [10:0] power_thres, input [31:0] min_plateau, // INPUT: RSSI - input [10:0] rssi_half_db, + input signed [10:0] rssi_half_db, // INPUT: I/Q sample input [31:0] sample_in, input sample_in_strobe,