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Author SHA1 Message Date
Jinghao Shi
ea638eb2d3
Merge pull request #25 from open-sdr/dot11zynq 
Changes for openwifi coming release
 2023-01-28 21:08:45 -08:00
Jiao Xianjun
19acdbe82f
Merge pull request #6 from ytakeuch/dot11zynq 
fix unsigned signals to signed signals
 2023-01-28 12:00:50 +01:00
Jiao Xianjun
583753829d
Merge pull request #7 from open-sdr/pre-release 
Pre release
 2023-01-28 11:56:19 +01:00
Xianjun Jiao
36c6b0f59a Add neptunesdr to related files 2023-01-16 13:40:22 +01:00
Yoji Takeuchi
7e8b44439a fix unsigned signals to signed signals 2023-01-16 12:56:24 +09:00
Xianjun Jiao
3f645e30f4 Add antsdr/e200 and sdrpi 2023-01-09 16:00:47 +01:00
Xianjun Jiao
8aa784707a Change the phase control value to the most safe one 2023-01-09 15:57:28 +01:00
Xianjun Jiao
b2e08ff46e Add precise sample_in_strobe phase control into dot11_tb.v for debugging the back luck FPGA loopback issue 2023-01-09 15:56:17 +01:00
Xianjun Jiao
db87c8d8a9 Fix the ofdm_symbol_eq_out_pulse according to the new euqalizer states 2023-01-09 15:55:10 +01:00
Xianjun Jiao
b7ba58b60a Add centralized DBG switch 2023-01-09 15:54:20 +01:00
Xianjun Jiao
ec2a5e8105 Update script for vivado 2021.1 2023-01-09 15:50:30 +01:00
Xianjun Jiao
f59c9418a7 Add DEBUG but not enabled 2023-01-09 15:49:23 +01:00
Xianjun Jiao
ad5a5206d3 Remove floating connections 2023-01-09 15:48:23 +01:00
thavinga
95e93cadfd LVPE correction before estimation 
- Add state in equalizer and rename others
- Add new dumper files in testbench to check with MATLAB
 2023-01-09 15:45:05 +01:00
thavinga
b0df85040f Add FFT window shift register 2023-01-09 15:40:42 +01:00
Xianjun Jiao
1b0354f85d Avoid phy_len_calculation out of the watchdog reset scope to have stable value before the next long_preamble_detected 2023-01-09 15:33:57 +01:00
Xianjun Jiao
e83599a85e Enable threshold scale for receiver and disable power trigger for watchdog by default 2023-01-09 15:32:48 +01:00
Xianjun Jiao
1043429762 signal watchdog only work while rssi above threshold: 
power_trigger valid
 2023-01-09 15:31:52 +01:00
Xianjun Jiao
54bdff7348 Make minimum pkt length configurable for signal_watchdog 2023-01-09 15:30:20 +01:00
Xianjun Jiao
75979e165a Add fake random +/-1 input while input are 0s: 
to avoid receiver reset during self-rx-muting (packet sending)
 2023-01-09 15:29:33 +01:00
Xianjun Jiao
73475306b7 Add phy len indication for decoding latency prediciton: 
Add n_ofdm_sym, n_bit_in_last_sym and phy_len_valid to openofdm_rx ip
 2023-01-09 15:28:25 +01:00
Xianjun Jiao
4359e4f96d Add phy len log into dot11_tb 2023-01-09 15:25:29 +01:00
Xianjun Jiao
8ce830c262 Shrink the bits of num_bits_to_decode and deinter_out_count: 
and adapt the verilog/ofdm_decoder.v accordingly
 2023-01-09 15:24:42 +01:00
thavinga
efa844bf0c Adapt CPE/LVPE calculation 2023-01-09 15:20:16 +01:00
Xianjun Jiao
27392f217f Adapt the test bench to align with ... 2023-01-09 14:51:55 +01:00
Xianjun Jiao
e978f30de6 Resolve the cpe/lvpe overflow issue 2023-01-09 14:51:06 +01:00
Xianjun Jiao
f455472288 Feed data to ofdm decoder earlier in case a data is missed (arrive too early for ofdm decoder) 2023-01-09 14:50:22 +01:00
Xianjun Jiao
71c9b42d78 Reset internally equalizer after it is disabled to prepare for next round enable 2023-01-09 14:49:31 +01:00
Xianjun Jiao
8e59685c65 Let sync short restart earlier before the end of current packet decoding, so that the next packet can come earlier (smaller inter packet gap is achieved) 2023-01-09 14:48:34 +01:00
Xianjun Jiao
e65ee43101 Make some basic block simpler and its delay more deterministic 2023-01-09 14:47:34 +01:00
Xianjun Jiao
a1e1e0090b Add threshold_scale and enable it by default: 
sync short works at low SNR and the receiver sensitivity is better
 2023-01-09 14:43:34 +01:00
Xianjun Jiao
6a8818fe5f extend the status_code to more formated style 2023-01-09 14:40:46 +01:00
Wei Liu
2747d431f9 fix viterbi decoder logging issue 2023-01-05 16:47:07 +01:00
Wei Liu
fe93170efc log all header bits, also when error occors 2023-01-05 16:45:43 +01:00
Wei Liu
c9f3d280a3 clean up log file, prolong simulation at the end by 300 sp 2023-01-05 16:38:51 +01:00
black_pigeon
f3bf82a05b add support for antsdr e200 2022-10-21 20:47:56 +02:00
Xianjun Jiao
3d0a40958c Add neptunesdr 2022-10-16 22:09:17 +02:00
Jinghao Shi
0c2c2d7f76
Merge pull request #24 from redfast00/fix-reserved-ht-header 
Fix reserved bit in SIG-HT header
 2022-08-17 23:47:32 -07:00
redfast00
a77a1abd01
Fix reserved bit in SIG-HT header 2022-08-18 08:13:56 +02:00
HexSDR
76986e99d3 Update parse_board_name.tcl 2022-08-15 09:12:08 +02:00
HexSDR
8a74580ad1 Update create_vivado_proj.sh 
add sdrpi
 2022-08-15 09:12:08 +02:00
Xianjun Jiao
707cb99a90 Remove the huge logging thing in dot11_tb.v 2022-07-15 12:10:03 +02:00
Jinghao Shi
864096ac05
Merge pull request #21 from jhshi/dependabot/pip/numpy-1.22.0 
Bump numpy from 1.11.2 to 1.22.0
 2022-06-21 17:34:43 -07:00
dependabot[bot]
f6679c7f18
Bump numpy from 1.11.2 to 1.22.0 
Bumps [numpy](https://github.com/numpy/numpy) from 1.11.2 to 1.22.0.
- [Release notes](https://github.com/numpy/numpy/releases)
- [Changelog](https://github.com/numpy/numpy/blob/main/doc/HOWTO_RELEASE.rst)
- [Commits](https://github.com/numpy/numpy/compare/v1.11.2...v1.22.0)

---
updated-dependencies:
- dependency-name: numpy
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2022-06-21 21:12:55 +00:00
Xianjun Jiao
064bbe4250 Auto stop the simulation at the end of iq sample file 2022-05-16 09:53:07 +02:00
Xianjun Jiao
f6fd0a2a85 Minor cleaning 2022-05-16 09:52:24 +02:00
Xianjun Jiao
7622d7aaa0 Disable signal watch dog for normal simulation in the tb 2022-05-16 09:51:30 +02:00
Xianjun Jiao
55f77bb16b Connect pkt_len from dot11 to signal watch dog in the tb 2022-05-16 09:51:01 +02:00
thavinga
cb6b566d5f Move all signal logging to dot11_tb.v 2022-05-16 09:33:19 +02:00
Xianjun Jiao
1659c01ac7 Add conditional compiling framework 2022-05-13 13:24:41 +02:00