Xianjun Jiao
a7b95b492c
Workaround to supress the error message when the 1st time run simulation
2022-05-13 13:21:19 +02:00
Jiao Xianjun
ac1a75e55a
Change the device/board to 7020 for low-end device friendly (Avoid the license issue in the default case)
2022-05-11 10:30:18 +02:00
Jinghao Shi
0ab83ce223
Merge pull request #19 from open-sdr/dot11zynq
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Improvement for openwifi-1.3.0-wilsele
2022-04-01 15:48:52 -07:00
Jiao Xianjun
5d4e72f66e
Merge pull request #1 from open-sdr/pre-release
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openwifi-1.3.0-wilsele
2022-04-01 11:07:17 +02:00
Xianjun Jiao
4168aa8c7a
Add slv_reg1[4] for option of disabling all smoothing
2022-03-29 12:50:31 +02:00
Xianjun Jiao
39911461ef
Fix the issue of adrv9364z7020: demod_is_ongoing always high. dot11 stuck at state 3
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Seems new viter decoder IP core does not need this complicated CE signal vit_ce in ofdm_decoder.v
Setting the vit-ce to always 1 fixed the issue
2022-03-23 14:26:41 +01:00
Xianjun Jiao
44c8846072
Add more test vectors into testing_inputs/simulated
2022-03-16 15:07:48 +01:00
Xianjun Jiao
f08c76ca3d
Add signal_watchdog module to prevent fake demod in early phase:
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1. If strong DC or low frequency sing wave like signal (suspect it is generated by ad9361 during some self-calibration like operation), put the receiver into reset
2. If the signal/header is valid, but the packet length is abnormal (signal_len<14 || signal_len>max_signal_len_th), reset the receiver
2022-03-15 16:03:40 +01:00
Xianjun Jiao
e77f1ba70b
Add git rev tracking to reg 31
2022-03-15 15:57:57 +01:00
Xianjun Jiao
954bae4e77
Add a test vector fake-demod-0.txt that could cause fake demodulation
2022-03-15 15:53:36 +01:00
Xianjun Jiao
40b3e59958
remove unnecessary atan_lut files
2022-03-15 15:52:05 +01:00
Jinghao Shi
4ad09c44c3
Merge pull request #18 from open-sdr/dot11zynq
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openwifi receiver improvements 2021
2022-01-28 11:11:57 -08:00
Xianjun Jiao
566e82f43e
Add more clock cases into dot11_tb.v
2022-01-28 12:17:16 +01:00
Xianjun Jiao
030cdb34ca
Add force ht smoothing option:
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> 1. Leave the module always enabled, so the slv_reg1 is free
> 2. Use the slv_reg1 to force ht smoothing
> 3. By default, the smoothing option of the receiver is still controlled by the received ht packet
2022-01-28 12:15:49 +01:00
mmehari
23e61e6a29
Avoid equalizer module processing HT_STF symbol
2022-01-04 22:45:47 +01:00
mmehari
0c75a8e8f2
bug fix: remaining packet length calculation
2022-01-04 22:44:31 +01:00
mmehari
8730912d6f
feature update: sampling frequency offset (SFO) compensation
2022-01-04 22:26:57 +01:00
mmehari
b40c221e67
Advance phase correction value by guard interval size
2022-01-04 22:25:38 +01:00
mmehari
85b1adbec7
bug fix: increase phase calculation delay by 1 CLK
2022-01-04 22:22:00 +01:00
mmehari
e257d3373b
storage update: A-MPDU decoding
2022-01-04 22:20:44 +01:00
mmehari
af855d8c10
Save channel gain information of HT-LTF
2022-01-04 22:19:40 +01:00
mmehari
48aade0190
provide demod_soft_bits and demod_soft_bits_pos signals out
2022-01-04 22:18:23 +01:00
mmehari
84039d7368
Don't catagorize IQ modulation as Q-BPSK or BPSK when I and Q components have the same magnitude
2022-01-04 22:17:12 +01:00
mmehari
d2d5494f57
LTF cross-correlation window update: 16->32 complex samples
2022-01-04 22:16:18 +01:00
mmehari
36c738fe98
phase estimation update: quadrant quantization from 256 slices -> 512 slices
2022-01-04 22:15:16 +01:00
mmehari
53679a107f
integer division rounding fix during phase offset calculation
2022-01-04 22:12:45 +01:00
mmehari
82d2d456e5
keep significant bits while performing division during phase calculation
2022-01-04 22:11:50 +01:00
mmehari
d9649eb614
phase register size reduction: 32bit -> 16bit
2022-01-04 22:10:36 +01:00
mmehari
f3e95eaa92
long preamble detection method update: cross-correlation inter-peak gap distance -> 1st peak detection
2022-01-04 22:07:54 +01:00
mmehari
aaa8ef3ce5
HT/non_HT detection requires at most 9 clocks
2022-01-04 22:05:38 +01:00
mmehari
8bc2d7f0a4
channel smoothing update based on HT-SIG field
2022-01-04 22:03:03 +01:00
mmehari
171ef8b27a
A-MPDU decoding support
2022-01-04 22:01:58 +01:00
mmehari
1a9246fd24
Provide ht_aggregation signal out
2022-01-04 22:00:55 +01:00
Jinghao Shi
c3035cf985
Merge pull request #15 from open-sdr/dot11zynq
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Provide ht_sgi signal out (for openwifi 11n release)
2021-01-08 10:37:24 -08:00
mmehari
f83d179cbe
Provide ht_sgi signal out
2020-11-06 13:20:15 +01:00
Jinghao Shi
d0f271bdc8
Merge pull request #14 from open-sdr/dot11zynq
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add necessary port as trigger for iq capture feature in openwifi
2020-10-19 02:01:39 -07:00
Xianjun Jiao
d331e66a31
add necessary port as trigger for iq capture feature in openwifi
2020-10-19 09:22:54 +02:00
Jinghao Shi
2c57c0a096
Merge pull request #13 from f380cedric/patch-1
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Typo
2020-10-12 10:34:43 -07:00
f380cedric
a7efc6cb97
Typo
2020-10-12 15:52:18 +02:00
Jinghao Shi
fb5fa6a744
Merge pull request #12 from open-sdr/dot11zynq
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output information for openwifi side channel feature
2020-10-08 02:17:22 -07:00
Xianjun Jiao
8714c30857
output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux
2020-10-08 10:06:03 +02:00
Jinghao Shi
229da948ae
Merge pull request #11 from open-sdr/dot11zynq
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The latest receiver optimization from openwifi project
2020-09-03 23:49:55 -07:00
Xianjun Jiao
539133f453
make the code more testbench friendly
2020-09-02 21:59:37 +02:00
Xianjun Jiao
2b3a043e8c
turn on soft_decoding in dot11_tb.v
2020-09-02 17:15:11 +02:00
Xianjun Jiao
6d60fceed2
fix the project_name and script_file in openofdm_rx_ultra_scale.tcl
2020-09-02 17:05:18 +02:00
Xianjun Jiao
bf043af712
change the latency of divider from automatic 60 clocks to the original 36 clock
2020-09-02 16:49:59 +02:00
mmehari
b86951097c
802.11n rx performance fix when used different clock rates (i.e. 100MHz vs 200MHz)
2020-08-30 15:23:07 +02:00
Xianjun Jiao
d7f5806790
fix the atan_addr overflow issue (phase.v)
2020-08-29 14:48:38 +02:00
mmehari
8c59d3a8dd
channel estimation update: frequency domain averaging
2020-08-29 11:41:32 +02:00
mmehari
77e201cfa8
course CFO bug fix
2020-08-29 11:38:06 +02:00
