Add CSI fuzzer counter attack paper.

Due to FPGA implementation, there CIR actually is [1, 0, c1, c2], not [1, c1, c2]

CONTRIBUTING.md

@@ -4,6 +4,6 @@ SPDX-FileCopyrightText: 2019 UGent
 SPDX-License-Identifier: AGPL-3.0-or-later
 -->
 
-CLA([Individual](https://users.ugent.be/~xjiao/openwifi-Individual.pdf), [Entity](https://users.ugent.be/~xjiao/openwifi-Entity.pdf)) needs to be signed and sent to Filip.Louagie@UGent.be before you contributing.
+CLA([Individual](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/openwifi-Individual.pdf), [Entity](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/openwifi-Entity.pdf)) needs to be signed and sent to Filip.Louagie@UGent.be before you contributing.
 
 CLA is generated by the [Project Harmony](http://www.harmonyagreements.org/index.html).

README.md

@@ -9,9 +9,10 @@ SPDX-License-Identifier: AGPL-3.0-or-later
 
 **openwifi:** Linux mac80211 compatible full-stack IEEE802.11/Wi-Fi design based on SDR (Software Defined Radio).
 
+[[Download img and Quick start](#Download-img-and-Quick-start)] [[**Tips for Windows users**](https://github.com/open-sdr/openwifi/discussions/341)]
+
 This repository includes Linux driver and software. **openwifi-hw** repository has the FPGA design. It is **YOUR RESPONSIBILITY** to follow your **LOCAL SPECTRUM REGULATION** or use **CABLE** to avoid potential interference over the air.
 
-[[Quick start](#Quick-start)]
 [[Project document](doc/README.md)]
 [[Application notes](doc/app_notes/README.md)]
 [[Videos](doc/videos.md)]
@@ -43,25 +44,29 @@ Openwifi code has dual licenses. [AGPLv3](https://github.com/open-sdr/openwifi/b
 
 **Performance (best case: aggregation/AMPDU on):**
 - iperf: TCP 40~50Mbps; UDP 50Mbps
-- EVM -39dB; MCS0 sensitivity -85dBm; MCS7 sensitivity -73dBm. (Both conducted/cable and radiated/OTA test)
+- EVM -38dB; MCS0 sensitivity -92dBm; MCS7 -73dBm. (FMCOMMS2 2.4GHz; cable and OTA test)
 
-**Supported SDR platforms:** (Check [Porting guide](#Porting-guide) for your new board if it isn't in the list)
+**Supported SDR platforms:**
 
-board_name|board combination|status|SD card img|Vivado license
--------|-------|----|----|-----
-zc706_fmcs2|[Xilinx ZC706 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|Need
-zed_fmcs2|[Xilinx zed board](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|**NO** need
-adrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/adrv9364-z7020.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|**NO** need
-adrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|Need
-zc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|**NO** need
-antsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|**NO** need
-zcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[64bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-64bit.img.xz)|Need
-zcu102_9371|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [ADRV9371](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adrv9371.html)|Future|Future|Need
+board_name|Description|Vivado license
+----------|-----------|--------------
+zc706_fmcs2|[Xilinx ZC706 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Need
+zed_fmcs2|[Xilinx zed board](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|**NO** need
+adrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/adrv9364-z7020.html)|**NO** need
+adrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Need
+zc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|**NO** need
+antsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|**NO** need
+e310v2|[MicroPhase](https://github.com/MicroPhase/) new antsdr [Notes](kernel_boot/boards/e310v2/README.md)|**NO** need
+antsdr_e200|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO (smaller/cheaper) [Notes](kernel_boot/boards/antsdr_e200/README.md)|**NO** need
+sdrpi|[HexSDR](https://github.com/HexSDR/) SDR in Raspberry Pi size [Notes](kernel_boot/boards/sdrpi/notes.md)|**NO** need
+zcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Need
+neptunesdr|Low cost Zynq 7020 + AD9361 board|**NO** need
 
-- board_name is used to identify FPGA design in openwifi-hw/boards/
+- Check [Porting guide](#Porting-guide) for your new board if it isn't in the list.
+- board_name is used to identify FPGA design in openwifi-hw/boards/ and FPGA image in openwifi-hw-img/boards
 - Don't have any boards? Or you like JTAG boot instead of SD card? Check our test bed [w-iLab.t](https://doc.ilabt.imec.be/ilabt/wilab/tutorials/openwifi.html) tutorial.
 
-[[Quick start](#Quick-start)]
+[[Download img and Quick start](#Download-img-and-Quick-start)]
 [[Basic operations](#Basic-operations)]
 [[Update FPGA](#Update-FPGA)]
 [[Update Driver](#Update-Driver)]
@@ -74,25 +79,36 @@ zcu102_9371|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kit
 [[Project document](doc/README.md)]
 [[Application notes](doc/app_notes/README.md)]
 
-## Quick start
-- Restore openwifi board specific img file (from the table) into a SD card. To do this, program "Disks" in Ubuntu can be used (Install: "sudo apt install gnome-disk-utility"). After restoring, the SD card should have two partitions: BOOT and rootfs. You need to config the **correct files in the BOOT partition** according to the **board you have** by operation on your computer: 
-  - Copy files in **openwifi/board_name** to the base directory of BOOT partition.
-  - Copy **openwifi/zynqmp-common/Image** (zcu102 board) or **openwifi/zynq-common/uImage** (other boards) to the base directory of BOOT partition
-- Connect two antennas to RXA/TXA ports. Config the board to SD card boot mode (check the board manual). Insert the SD card to the board. Power on. 
+## Download img and Quick start
+- Download [openwifi img](https://drive.google.com/file/d/12egFLT9TclmY8m3vCMHmUuSne3qK0SWc/view?usp=sharing), unzip and burn it into a SD card (>=16GB). After this operation, the SD card should have two partitions: BOOT and rootfs. To flash the SD card, SD card tool software (such as Startup Disk Creator in Ubuntu) or dd command can be used:
+  ```
+  sudo dd bs=512 count=31116288 if=openwifi-xyz.img of=/dev/your_sdcard_dev
+  (To have correct count value, better to check the .img file actual situation by "fdisk -l img_filename")
+  ```
+- Config the **correct files in the BOOT partition** according to the **board you have** by operation on your computer: 
+  - Copy files in **BOOT/openwifi/board_name** to the base directory of BOOT partition.
+  - Delete the **rootfs/root/kernel_modules** directory (if exist).
+  - Delete the **rootfs/etc/network/interfaces.new** directory (if exist).
+- Insert the SD card to the board. Configure the board in SD booting mode. Connect antennas. Power on. 
 - Login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with password **openwifi**.
   ```
   ssh root@192.168.10.122
   ```
-- On board, run openwifi AP and the on board webserver
+- If not successful, check [known issue](doc/known_issue/notter.md)
+- Then, run openwifi AP and the on board webserver
   ```
-  ~/openwifi/fosdem.sh
-  (Use "./fosdem.sh 1" to enable experimental AMPDU aggregation on top of 11n)
+  raspi-config --expand-rootfs (Only needed when your SD card > 16GB. Run and reboot)
+  ./openwifi/setup_once.sh (Reboot the board. Only need to run once for new board)
+  cd openwifi
+  ./wgd.sh
+  ./fosdem.sh
+  (Use "./wgd.sh 1" to enable experimental AMPDU aggregation on top of 11n)
   (Use "./fosdem-11ag.sh" to force 11a/g mode)
   ```
   **NOTE** adrv9361z7035 has ultra low TX power in 5GHz. Move **CLOSER** when you use that board in 5GHz!!!
-- After you see the "openwifi" SSID on your device (Phone/Laptop/etc), connect it. Browser to 192.168.13.1 on your device, you should see the webpage hosted by the webserver on board.
+- After you see the "openwifi" SSID on your device (Phone/Laptop/etc), connect it (If not get 192.168.13.* IP automatically, check [known issue](doc/known_issue/notter.md)). Browser to 192.168.13.1 on your device, you should see the webpage hosted by the webserver on board.
   - Note 1: If your device doesn't support 5GHz (ch44), please change the **hostapd-openwifi.conf** on board and re-run fosdem.sh.
-  - Note 2: After ~2 hours, the Viterbi decoder will halt (Xilinx Evaluation License). Just power cycle the board if it happens. (If output of "./sdrctl dev sdr0 get reg rx 20" is always the same, it means the decoder halts)
+  - Note 2: After ~2 hours, the Viterbi decoder will halt (Xilinx Evaluation License). Just reload FPGA ([method](doc/app_notes/drv_fpga_dynamic_loading.md)) or simply power cycle the board if it happens. (If output of "./sdrctl dev sdr0 get reg rx 20" is always the same, it means the decoder halts)
 - To give the Wi-Fi client internet access, configure routing/NAT **on the PC**:
   ```
   sudo sysctl -w net.ipv4.ip_forward=1
@@ -117,66 +133,60 @@ The board actually is an Linux/Ubuntu computer which is running **hostapd** to o
   wpa_supplicant -i sdr0 -c wpa-connect.conf &
   dhclient sdr0
   ```
-- Use openwifi in ad-hoc mode: Please check **sdr-ad-hoc-up.sh** and **sdr-ad-hoc-join.sh**.
-- Use openwifi in monitor mode: Please check **monitor_ch.sh**.
+- Use openwifi in ad-hoc mode: Please check **sdr-ad-hoc-up.sh**, **sdr-ad-hoc-join.sh** and [this app note](./doc/app_notes/ad-hoc-two-sdr.md).
+- Use openwifi in monitor mode: Please check **monitor_ch.sh** and [this app note](./doc/app_notes/inject_80211.md).
 - The Linux native Wi-Fi tools/Apps (iwconfig/ifconfig/iwlist/iw/hostapd/wpa_supplicant/etc) can run over openwifi NIC in the same way as commercial Wi-Fi chip. 
-- **sdrctl** is a dedicated tool to access openwifi driver/FPGA, please check doc directory for more information. 
+- **sdrctl** is a dedicated tool to access openwifi driver/FPGA, please check [project document](./doc/README.md) for more information. 
 
 ## Update FPGA
 
-Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to update the fpga bitstream on board.
+Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to always copy the latest files in the [user_space](./user_space) directory on to the board. Then update the FPGA&Driver according to the Quick start of [this app note](doc/app_notes/radar-self-csi.md#quick-start). Following instructions are doing the same thing with extra info for environment setup.
 
-- Install Vivado/SDK 2018.3 (Vivado Design Suite - HLx Editions - 2018.3 Full Product Installation. If you don't need to generate new FPGA bitstream, WebPack version without license is enough)
+(Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for better understanding of updating FPGA and driver files without rebooting/power-cycle)
+
+- Install Vivado 2021.1. Make sure install Vitis as well. You should have this directory: your_Xilinx_install_directory/Vitis (NOT Vitis_HLS!)
+  - If the Vitis is not installed, you can add it by running "Xilinx Design Tools --> Add Design Tools for Devices 2021.1" from Xilinx program group/menu in your OS start menu.
 - Setup environment variables (use absolute path):
   ```
   export XILINX_DIR=your_Xilinx_install_directory
-  (Example: export XILINX_DIR=/opt/Xilinx. The Xilinx directory should include sth like: Downloads, SDK, Vivado, xic)
-  export OPENWIFI_HW_DIR=your_openwifi-hw_directory
-  (The directory where you store the open-sdr/openwifi-hw repo via git clone)
+  (Example: export XILINX_DIR=/opt/Xilinx. The Xilinx directory should include sth like: Downloads, Vitis, etc.)
+  export OPENWIFI_HW_IMG_DIR=your_openwifi-hw-img_directory
+  (The directory where you get the open-sdr/openwifi-hw-img repo via git clone)
   export BOARD_NAME=your_board_name
   ```
-- Pick the FPGA bitstream from openwifi-hw, and generate BOOT.BIN and transfer it on board via ssh channel:
+- Pick the FPGA bitstream from openwifi-hw-img, generate system_top.bit.bin and transfer it on board via ssh channel:
   ```
-  For Zynq 7000:
-  
-  cd openwifi/user_space; ./boot_bin_gen.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME
-  
-  For Zynq MPSoC (like zcu102 board):
-  cd openwifi/user_space; ./boot_bin_gen_zynqmp.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME
-  
-  cd openwifi/kernel_boot/boards/$BOARD_NAME/output_boot_bin; scp ./BOOT.BIN root@192.168.10.122:
+  cd openwifi/user_space; ./boot_bin_gen.sh $XILINX_DIR $BOARD_NAME $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top.xsa
+  scp ./system_top.bit.bin root@192.168.10.122:openwifi/
   ```
-- On board: Put the BOOT.BIN into the BOOT partition.
-  ```
-  mount /dev/mmcblk0p1 /mnt
-  cp ~/BOOT.BIN /mnt
-  cd /mnt
-  sync
-  cd ~
-  umount /mnt
-  ```
-  **Power cycle** the board to load new FPGA bitstream.
+- Now the system_top.bit.bin is onboard in /root/openwifi/ directory. When wgd.sh runs onboard from that directory, it will discover the FPGA img file system_top.bit.bin and load it before loading driver .ko files.
 
 ## Update Driver
 
-Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to update the driver on board.
+Since the pre-built SD card image might not have the latest bug-fixes/updates, it is recommended to always copy the latest files in the [user_space](./user_space) directory on to the board. Then update the FPGA&Driver according to the Quick start of [this app note](doc/app_notes/radar-self-csi.md#quick-start). Following instructions are doing the same thing with extra info for environment setup.
+
+(Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for better understanding of updating FPGA and driver files without rebooting/power-cycle)
+
 - Prepare Analog Devices Linux kernel source code (only need to run once):
   ```
-  cd openwifi/user_space; ./prepare_kernel.sh $XILINX_DIR ARCH_BIT build
+  sudo apt install flex bison libssl-dev device-tree-compiler u-boot-tools -y
+  cd openwifi/user_space; ./prepare_kernel.sh $XILINX_DIR ARCH_BIT
   (For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)
   ```
-  **Note**: In Ubuntu, gcc-10 might have issue ('yylloc' error), so use gcc-9 if you encounter error.
 - Compile the latest openwifi driver
   ```
   cd openwifi/driver; ./make_all.sh $XILINX_DIR ARCH_BIT
   (For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT should be 64)
+  (More arguments (max 5) beyond above two will be converted to "#define argument" in pre_def.h for conditional compiling)
   ```
 - Copy the driver files to the board via ssh channel
   ```
   cd openwifi/driver; scp `find ./ -name \*.ko` root@192.168.10.122:openwifi/
   ```
-  Now you can use **wgd.sh** on board to load the new openwifi driver.
-  **Note**: If you have symbol or version error while loadng the driver, it could be because the kernel in the SD card image is too old. In this case, you need to follow [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to generate your new SD card image.
+  Now you can use **wgd.sh** on board to load the new openwifi driver. **wgd.sh** also tries to reload FPGA img if system_top.bit.bin presents in the same directory. 
+  Find more information in [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md).
+  
+  **Note**: If you have symbol or version error while loadng the driver, it could be because the kernel in the SD card image is too old. In this case, you need put the linux kernel image generated by prepare_kernel.sh (check [[Update Driver](#Update-Driver)]) to the BOOT partition of SD card. The kernel image file name: adi-linux/arch/arm/boot/uImage (32bit); adi-linux-64/arch/arm64/boot/Image (64bit).
 
 ## Update sdrctl
 - Copy the sdrctl source files to the board via ssh channel
@@ -185,10 +195,11 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i
   ```
 - Compile the sdrctl **on board**:
   ```
-  cd ~/openwifi/sdrctl_src/ && make && cp sdrctl ../ && cd ..
+  cd ~/openwifi/sdrctl_src/ && make clean && make && cp sdrctl ../ && cd ..
   ```
 ## Easy Access and etc
 
+- Check [Driver and FPGA dynamic reloading app note](./doc/app_notes/drv_fpga_dynamic_loading.md) for more convenient way of updating FPGA and driver files without rebooting/power-cycle.
 - FPGA and driver on board update scripts
   - Setup [ftp server](https://ubuntu.com/server/docs/service-ftp) on PC, allow anonymous and change ftp root directory to the openwifi directory.
   - On board:
@@ -203,39 +214,7 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i
    - Input password "openwifi"
 
 ## Build openwifi Linux img from scratch
-- Install the devicetree compiler -- dtc. (For Ubuntu: sudo apt install device-tree-compiler)
-- Install the mkimage tool. (For Ubuntu: sudo apt install u-boot-tools)
-- Download [2019_R1-2020_06_22.img.xz](http://swdownloads.analog.com/cse/2019_R1-2020_06_22.img.xz) from [Analog Devices Wiki](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images). Burn it to a SD card.
-- Insert the SD card to your Linux PC. Find out the mount point (that has two sub directories BOOT and rootfs), and setup environment variables (use absolute path):
-  ```
-  export SDCARD_DIR=sdcard_mount_point
-  export XILINX_DIR=your_Xilinx_install_directory
-  export OPENWIFI_HW_DIR=your_openwifi-hw_directory
-  export BOARD_NAME=your_board_name
-  ```
-- Run script to update SD card:
-  ```
-  cd openwifi/user_space; ./update_sdcard.sh $OPENWIFI_HW_DIR $XILINX_DIR $BOARD_NAME $SDCARD_DIR
-  ```
-- Config your board to SD card boot mode (check the board manual). Insert the SD card to the board. Power on.
-- Login to the board from your PC (PC Ethernet should have IP 192.168.10.1) with one time password **analog**.
-  ```
-  ssh root@192.168.10.122
-  ```
-- Setup routing/NAT **on the PC** for your board -- this internet connection is **important** for post installation/config.
-  ```
-  sudo sysctl -w net.ipv4.ip_forward=1
-  sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE
-  sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX
-  ```
-  **ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet).
-  
-  If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC.
-- Run **one time** script on board to complete post installation/config (After this, password becomes **openwifi**)
-  ```
-  cd ~/openwifi && ./post_config.sh
-  ```
-- Now you can start from [Quick start](#Quick-start) (Skip the image download and burn step)
+- For the latest ADI Kuiper image, please check [kuiper.md](./doc/img_build_instruction/kuiper.md)
 
 ## Special note for 11b
 
@@ -252,13 +231,13 @@ cd openwifi/user_space; ./build_wpa_supplicant_wo11b.sh
 ```
 ## Porting guide
 
-This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on 2019_R1 of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl).
+This section explains the porting work by showing the differences between openwifi and Analog Devices reference design. openwifi is based on 2021_r1 of [HDL Reference Designs](https://github.com/analogdevicesinc/hdl).
 - Open the fmcomms2 + zc706 reference design at hdl/projects/fmcomms2/zc706 (Please read Analog Devices help)
 - Open the openwifi design zc706_fmcs2 at openwifi-hw/boards/zc706_fmcs2 (Please read openwifi-hw repository)
 - "Open Block Design", you will see the differences between openwifi and the reference design. Both in "diagram" and in "Address Editor".
 - The address/interrupts of FPGA blocks hooked to the ARM bus should be put/aligned to the devicetree file openwifi/kernel_boot/boards/zc706_fmcs2/devicetree.dts. Linux will parse the devicetree.dtb when booting to know information of attached device (FPGA blocks in our case).
 - We use dtc command to get devicetree.dts converted from devicetree.dtb in [Analog Devices Linux image](https://wiki.analog.com/resources/tools-software/linux-software/zynq_images), then do modification according to what we have added/modified to the reference design.
-- Please learn the script in [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to understand how we generate devicetree.dtb, BOOT.BIN and Linux kernel uImage and put them together to build the full SD card image.
+- Please learn the script in [[Build openwifi Linux img from scratch](#Build-openwifi-Linux-img-from-scratch)] to understand how we generate devicetree.dtb, BOOT.BIN, Linux kernel and put them together to build the full SD card image.
 
 ## License
 

doc/README.md

@@ -14,6 +14,7 @@ Above figure shows software and hardware/FPGA modules that compose the openwifi
 - [sdrctl command](#sdrctl-command)
 - [Rx packet flow and filtering config](#Rx-packet-flow-and-filtering-config)
 - [Tx packet flow and config](#Tx-packet-flow-and-config)
+- [Understand the timestamp of WiFi packet](#Understand-the-timestamp-of-WiFi-packet)
 - [Regulation and channel config](#Regulation-and-channel-config)
 - [Analog and digital frequency design](#Analog-and-digital-frequency-design)
 - [Debug methods](#Debug-methods)
@@ -204,7 +205,7 @@ reg_idx|meaning|comment
 8|RSSI threshold for CCA (channel idle/busy)|set by ad9361_rf_set_channel automatically. the unit is rssi_half_db, check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm
 9|some low MAC time setting|bit31 0:auto, 1:manual. When manual, bit6-0: PHY rx delay, bit13-7: SIFS, bit18-14: slot time, bit23-19: ofdm symbol time, bit30-24: preamble+SIG time. unit us. check xpu.v (search slv_reg9)
 10|BB RF delay setting|unit 0.1us. bit7-0: BB RF delay, bit14-8: RF end extended time on top of the delay. bit22-16: delay between bb tx start to RF tx on (lo or port control via spi). bit30-24: delay between bb tx end to RF tx off. check xpu.v (search slv_reg10)
-11|ACK control and max num retransmission|bit4: 0:normal ACK, 1:disable auto ACK reply in FPGA. bit3-0: if bit3==0, the number of retransmission is decided by Linux. if bit3==1, the max num retransmission is taken from bit2-0
+11|ACK control and max num retransmission|bit4: 0:normal ACK tx/reply, 1:disable auto ACK tx/reply in FPGA. bit5: 0:normal ACK rx from peer, 1:not expecting ACK rx from peer. bit3-0: if bit3==0, the number of retransmission is decided by Linux. if bit3==1, the max num retransmission is taken from bit2-0
 12|AMPDU control|bit0: indicate low MAC start to receive AMPDU. bit4-1: tid. bit31: tid enable (by default, tid is not enabled and we decode AMPDU of all tid)
 13|spi controller config|1: disable spi control and Tx RF is always on; 0: enable spi control and Tx RF only on (lo/port) when pkt sending
 16|setting when wait for ACK in 2.4GHz|unit 0.1us. bit14-0: OFDM decoding timeout (after detect PHY header), bit30-16: timeout for PHY header detection, bit31: 0: FCS valid is not needed for ACK packet, 1: FCS valid is needed for ACK packet
@@ -220,9 +221,9 @@ reg_idx|meaning|comment
 29|BSSID address high 16bit for BSSID filtering|auto set by xpu_api->XPU_REG_BSSID_FILTER_HIGH_write in openwifi_bss_info_changed of sdr.c
 30|MAC address low  32bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c
 31|MAC address high 16bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c
-37|addr2 of rx packet read back|bit31-0 are from bit47-16 of addr2 field in the received packet
 58|TSF runtime value low  32bit|read only
 59|TSF runtime value high 32bit|read only
+62|addr2 of rx packet read back|bit31-0 are from bit47-16 of addr2 field in the received packet
 63|git revision when build the FPGA|returned register value means git revision in hex format
 
 ## Rx packet flow and filtering config
@@ -266,6 +267,18 @@ Each time when FPGA sends a packet, an interrupt will be raised to Linux reporti
     - packet sending result: packet is sent successfully (FPGA receives ACK for this packet) or not. How many retransmissions have been done (in case FPGA doesn't receive ACK in time, FPGA will do retransmission according to CSMA/CA low MAC state)
   - send above information to upper layer (Linux mac80211 subsystem) via ieee80211_tx_status_irqsafe()
 
+## Understand the timestamp of WiFi packet
+
+The TSF timestamp shown in the usual wireshark snapshot is reported by openwifi Linux driver towards Linux mac80211 framework.
+![](https://user-images.githubusercontent.com/5212105/270659135-44a048ae-773f-48a7-bf3f-76ffc3ee399a.jpg)
+
+This TSF timestamp is attached to the DMA of the received packet in FPGA by reading the TSF timier (defined by 802.11 standard and implemented in FPGA) value while PHY header is received: [FPGA code snip](https://github.com/open-sdr/openwifi-hw/blob/14b1e840591f470ee945844cd3bb51a95d7da09f/ip/rx_intf/src/rx_intf_pl_to_m_axis.v#L201).
+
+Then openwifi driver report this timestamp value (together with the corresponding packet) to Linux via:
+https://github.com/open-sdr/openwifi/blob/0ce2e6b86ade2f6164a373b2e98d075eb7eecd9e/driver/sdr.c#L530
+
+To match the openwifi side channel collected data (CSI, IQ sample, etc.) to the TSF timestamp of the packet, please check: https://github.com/open-sdr/openwifi/discussions/344
+
 ## Regulation and channel config
 
 SDR is a powerful tool for research. It is the user's responsibility to align with local spectrum regulation when doing OTA (Over The Air) test, or do the test via cable (conducted test), or in a chamber to avoid any potential interference.
@@ -386,8 +399,8 @@ sdr,sdr openwifi_tx_interrupt: tx_result [nof_retx 1 pass 1] SC20 prio0 q0 wr20
 - prio, q, wr, rd: these fields can be interpreted the same way as the print in openwifi_tx function
 - num_slot: tells how many slots the CSMA/CA state machine waited until the packet is sent in the last tx attempt
 - cw: the exponent of the Contention Window for this packet. 6 means the CW size 64. If the contention phase is never entered, CW is 0
-- hwq len: the current FPGA queue length (number of pkt left in the queue).8bit per queue. see tx_intf register 26 (https://github.com/open-sdr/openwifi/blob/master/doc/README.md)
-- no_room_flag: the DMA room of FPGA queue is almost run out. 1bit per queue. see tx_intf register 21 (https://github.com/open-sdr/openwifi/blob/master/doc/README.md)
+- hwq len: the current FPGA queue length (number of pkt left in the queue).8bit per queue. see tx_intf register 26 in the register table section.
+- no_room_flag: the DMA room of FPGA queue is almost run out. 1bit per queue. see tx_intf register 21 in the register table section.
 
 ### rx printing example
 ```

doc/app_notes/README.md

@@ -13,11 +13,13 @@ Application notes collect many small topics about using openwifi in different sc
 - [WiFi CSI radar via self CSI capturing](radar-self-csi.md)
 - [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md)
 - [Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md)
-- [WiFi packet and IQ sample self loopback test (over-the-air and FPGA internal)](packet-iq-self-loopback-test.md)
+- [WiFi packet, CSI and IQ sample self loopback test (over-the-air and FPGA internal)](packet-iq-self-loopback-test.md)
 - [IEEE 802.11n (Wi-Fi 4)](ieee80211n.md)
 - [802.11 packet injection and fuzzing](inject_80211.md)
 - [CSI fuzzer](csi_fuzzer.md)
 - [Access counter/statistics in FPGA](perf_counter.md)
 - [Access counter/statistics in driver](driver_stat.md)
 - [Frequent/usual trick on controlling Gain/Att/Frequency/CCA/LBT/CSMA/CW/Sensitivity/etc](frequent_trick.md)
-- [owfuzz: a WiFi protocol fuzzing tool using openwifi.](https://github.com/alipay/WiFi-Protocol-Fuzzing-Tool) [[**Vulnerabilities**]](https://github.com/E7mer/Owfuzz)
+- [Driver and FPGA dynamic reloading](drv_fpga_dynamic_loading.md)
+- [owfuzz: a WiFi protocol fuzzing tool using openwifi.](https://github.com/alipay/WiFi-Protocol-Fuzzing-Tool) [[**Vulnerabilities**]](https://github.com/alipay/Owfuzz#discovered-vulnerabilities)
+- [Build FPGA with High-Level Synthesis modules](hls.md)

doc/app_notes/ap-client-two-sdr.md

@@ -35,7 +35,7 @@ SPDX-License-Identifier: AGPL-3.0-or-later
   wpa_supplicant -i sdr0 -c wpa-openwifi.conf
   ("iwconfig sdr0 essid openwifi" could also work. Less info compared to wpa_supplicant)
   ```
-  If wpa-openwifi.conf is not on board, please create it with [this content](https://github.com/open-sdr/openwifi/blob/master/user_space/wpa-openwifi.conf).
+  If wpa-openwifi.conf is not on board, please create it with [this content](../../user_space/wpa-openwifi.conf).
 - Now the client is trying to associate with the AP. You should see like:
   ```
   root@analog:~/openwifi# wpa_supplicant -i sdr0 -c wpa-openwifi.conf 

doc/app_notes/csi.md

@@ -7,6 +7,8 @@ SPDX-License-Identifier: AGPL-3.0-or-later
 
 We extend the **CSI** (Channel State Information) to **CSI** (Chip State Information)!
 
+(This app note shows general CSI collection. To use self-Tx CSI in full duplex mode as **RADAR**, please refer to [WiFi CSI radar via self CSI capturing](radar-self-csi.md))
+
 ## Quick start
 - Power on the SDR board.
 - Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
@@ -128,6 +130,8 @@ We extend the **CSI** (Channel State Information) to **CSI** (Chip State Informa
   The openwifi CSI feature could run with not only monitor mode but also other modes, such as AP-Client or ad-hoc mode. After the communication functionality is fully up in those modes, you can start CSI feature from "**insmod side_ch.ko**" and "**./side_ch_ctl g**" on board as described in the previous sections to extract CSI to your computer.
 
 ## Map the CSI information to the WiFi packet
+  Please check this discussion: https://github.com/open-sdr/openwifi/discussions/344
+  
   If you want to relate the CSI information to the WiFi packet, you need to capture WiFi packets (tcpdump/wireshark/etc) while capturing CSI. Then you can match the timestamp (TSF timer value) between WiFi packet and CSI information, because this is the unique same identity of a Wifi packet and related CSI information.
   
   Please learn the python and Matlab script to extract CSI information per packet according to your requirement.

doc/app_notes/csi_fuzzer.md

@@ -4,7 +4,8 @@ SPDX-FileCopyrightText: 2021 UGent
 SPDX-License-Identifier: AGPL-3.0-or-later
 -->
 
-[ACM WiSec 2021. Openwifi CSI fuzzer for authorized sensing and covert channels](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255)
+- [ACM WiSec 2021. Openwifi CSI fuzzer for authorized sensing and covert channels](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255)
+- [Privacy Protection in WiFi Sensing via CSI Fuzzing](https://ieeexplore.ieee.org/abstract/document/10818006)
 
 CSI (Channel State Information) of WiFi systems is available in some WiFi chips and can be used for sensing the environment (keystrokes, people, object) passively and secretly.
 

doc/app_notes/drv_fpga_dynamic_loading.md

@@ -0,0 +1,70 @@
+The **wgd.sh** (running on board) supports reloading driver and/or FPGA image dynamically without rebooting/power-cycle. It can work in a 
+flexible way. 
+
+The purpose of this feature is to help you easily reload driver and FPGA built from your branch/version/variant/modification, and switch/run different driver and FPGA of different branch/version/variant/modification without rebooting. To enjoy this feature, always ensure your onboard openwifi/files are the latest files in [user_space](../../user_space)).
+
+- [[Reload driver only](#Reload-driver-only)]
+- [[Reload driver and FPGA](#Reload-driver-and-FPGA)]
+- [[Reload driver and FPGA in target directory](#Reload-driver-and-FPGA-in-target-directory)]
+- [[Reload driver and FPGA from a single package file](#Reload-driver-and-FPGA-from-a-single-package-file)] -- **RECOMMENDED!**
+- [[Suggested practice to generate driver FPGA variants](#Suggested-practice-to-generate-driver-FPGA-variants)]
+- [[Detailed full usage info](#Detailed-full-usage-info)]
+
+Note: Make sure you have compiled driver before. Check [Update Driver](../../README.md#update-driver).
+
+## Reload driver only
+This is the original way. To let **wgd.sh** only loads the driver without touching FPGA, please ensure FPGA image file **system_top.bit.bin** is **NOT** 
+present in the directory. If wgd.sh can not find the FPGA image, it will skip reloading it.
+
+## Reload driver and FPGA
+- Generate the reloadable FPGA file **system_top.bit.bin**. In the Linux host computer:
+  ```
+  cd openwifi/user_space
+  ./drv_and_fpga_package_gen.sh $OPENWIFI_HW_IMG_DIR $XILINX_DIR $BOARD_NAME
+  ```
+  Then **system_top.bit.bin** will be generated in openwifi/user_space.
+
+- Put **system_top.bit.bin** on board in the same directory as wgd.sh and other driver files (.ko)
+- Run **wgd.sh** on board as usual
+
+## Reload driver and FPGA in target directory
+Put **system_top.bit.bin** on board together with other driver files (.ko) in a directory ($TARGET_DIR), then run on board:
+```
+./wgd.sh $TARGET_DIR
+```
+In this way, different versions/variants of driver/FPGA can be put in different directories. Then **wgd.sh** can be used to switch 
+between them without rebooting/power-cycle.
+
+## Reload driver and FPGA from a single package file
+The openwifi/user_space/**drv_and_fpga_package_gen.sh** also generates a single package file **drv_and_fpga.tar.gz**, which includes driver files (.ko), 
+FPGA image and many other source files with rich infos that are related.
+
+You can switch to your own branch/version/variant, build the single package file via **drv_and_fpga_package_gen.sh**, rename it with a more meaningful name (such as add version or variant info as postfix), put the renamed **drv_and_fpga_MEANINGFUL_POSTFIX.tar.gz** on board in the same directory as **wgd.sh**, and let **wgd.sh** load it:
+```
+./wgd.sh ./drv_and_fpga_MEANINGFUL_POSTFIX.tar.gz
+```
+In this way, different version/variants of driver/FPGA can be switched by **wgd.sh** without rebooting/power-cycle.
+
+## Suggested practice to generate driver FPGA variants
+There are several ways to generate variants of the single driver-FPGA package file. For example:
+
+- Switch/create another branch for openwifi and openwifi-hw, work/modify there, then generate the single package file via **drv_and_fpga_package_gen.sh**. This package is the branch specific, so renaming the package name to a more meaningful one would be good practice.
+- In the same branch, set different arguments (finally macro definitions in .h and .v files) via conditional compiling to enable/disable different driver and FPGA code blocks/functionalities, then generate the single package file via **drv_and_fpga_package_gen.sh**. Rename the package to remind you which conditions are ON/OFF.
+    - Check "Conditional compile by verilog macro" in openwifi-hw README for FPGA design
+    - Input more arguments (max 5) to driver building script "make_all.sh $XILINX_DIR ARCH_BIT". Those arguments will be converted to "#define argument" in pre_def.h for driver conditional compiling. **Attention:** **drv_and_fpga_package_gen.sh** currently only call **make_all.sh** without extra arguments. If you have conditional compiling arguments, do not forget to put them into **drv_and_fpga_package_gen.sh** as extra arguments of **make_all.sh**.
+
+## Detailed full usage info
+Run the "./wgd.sh -h" on board or open wgd.sh to see full usage info:
+```
+usage:
+  Script for load (or download+load) different driver and FPGA img without rebooting
+  no  argument: Load .ko driver files and FPGA img (if system_top.bit.bin exist) in current dir with test_mode=0.
+  1st argument: If it is a NUMBER, it will be assigned to test_mode. Then load everything from current dir.
+  1st argument: If it is a string called "remote", it will download driver/FPGA and load everything.
+  - 2nd argument (if exist) is the target directory name for downloading and reloading
+  - 3rd argument (if exist) is the value for test_mode
+  1st argument: neither NUMBER nor "remote" nor a .tar.gz file, it is regarded as a directory and load everything from it.
+  - 2nd argument (if exist) is the value for test_mode
+  1st argument: a .tar.gz file, it will be unpacked then load from that unpacked directory
+  - 2nd argument (if exist) is the value for test_mode
+```

doc/app_notes/frequent_trick.md

@@ -1,7 +1,7 @@
 Some usual/frequent control trick over the openwifi FPGA. You need to do these controls on board in the openwifi directory.
 
 [[CCA LBT threshold and disable](#CCA-LBT-threshold-and-disable)]
-[[Retransmission and ACK tx control](#Retransmission-and-ACK-tx-control)]
+[[Retransmission and ACK control](#Retransmission-and-ACK-control)]
 [[NAV DIFS EIFS CW disable and enable](#NAV-DIFS-EIFS-CW-disable-and-enable)]
 [[CW max and min config](#CW-max-and-min-config)]
 
@@ -20,26 +20,30 @@ Some usual/frequent control trick over the openwifi FPGA. You need to do these c
 In normal operation, different threshold is set to FPGA according to the different calibration of different frequency/channel by driver automatically. Show the current LBT threshold in FPGA:
 ```
 ./set_lbt_th.sh
+dmesg
 ```
-"reg  val: 00000086" means the current threshold is 134 (86 in Hex). Its unit is rssi_half_db. Check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm.
+It shows: "sdr,sdr FPGA LBT threshold 166(-62dBm). The last_auto_fpga_lbt_th 166(-62dBm). rssi corr 145". Check rssi_half_db_to_rssi_dbm()/rssi_dbm_to_rssi_half_db() in sdr.c to see the relation to rssi dBm.
 
 Override a new threshold -NNdBm to FPGA, for example -70dBm:
 ```
 ./set_lbt_th.sh 70
+dmesg
 ```
 Above will disable the automatic CCA threshold setting from the openwifi driver.
 
 Recover the driver automatic control on the threshold:
 ```
 ./set_lbt_th.sh 0
+dmesg
 ```
 Disable the CCA by setting a very strong level as threshold, for example -1dBm:
 ```
 ./set_lbt_th.sh 1
+dmesg
 ```
 After above command, the CCA engine will always believe the channel is idle, because the rx signal strength not likely could exceed -1dBm.
   
-## Retransmission and ACK tx control
+## Retransmission and ACK control
 
 The best way of override the maximum number of re-transmission for a Tx packet is doing it in the driver openwifi_tx() function. 
 ```
@@ -51,7 +55,7 @@ The FPGA also has a register to override the re-transmission and ACK behavior. C
 ```
 ./sdrctl dev sdr0 get reg xpu 11
 ```
-When operate this register, make sure you only change the relevant bits and leave other bits untouched, because other bits have other purposes. Also check the xpu register 11 in the document: https://github.com/open-sdr/openwifi/blob/master/doc/README.md
+When operate this register, make sure you only change the relevant bits and leave other bits untouched, because other bits have other purposes. Also check the xpu register 11 in the [project document](../README.md)
 
 To override the maximum number of re-transmission, set bit3 to 1, and set the value (0 ~ 7) to bit2 ~ 0. Example, override the maximum number of re-transmission to 1
 ```
@@ -60,7 +64,7 @@ To override the maximum number of re-transmission, set bit3 to 1, and set the va
 
 9 in binary form is 01001.
 
-To disable the ACK TX after receive a packet, set bit4 to 1. (Assume we want to preserve the above re-transmission overriding setting)
+To disable the ACK TX after receiving a packet, set bit4 to 1. (Assume we want to preserve the above re-transmission overriding setting)
 ```
 ./sdrctl dev sdr0 set reg xpu 11 25
 ```
@@ -68,6 +72,8 @@ To disable the ACK TX after receive a packet, set bit4 to 1. (Assume we want to
 25 in binary form is 11001. the 1001 of bit3 to 1 is untouched.
 
 Disabling ACK TX might be useful for monitor mode and packet injection.
+
+To disable the ACK RX after sending a packet, set bit5 to 1.
   
 ## NAV DIFS EIFS CW disable and enable
 
@@ -162,7 +168,20 @@ insmod sdr.ko init_tx_att=20000
 You can change above driver loading action at the end of **wgd.sh**.
 
 The initial Tx attenuation might be useful when you connect two SDR boards directly by cable. Even though, you shouldn't not connect them during the setup phase (bring up the AP or client), because the initialization/tuning of AD9361 might generate big Tx power and kill the other AD9361's Rx. Only connect two SDR boards by cable after both sides have been setup and the attenuation setting takes effect.
-  
+
+To increase the Tx power, you can consider add external PA like [this](https://github.com/open-sdr/openwifi/issues/53#issuecomment-767621478). Or increase the value of register 13 of tx_intf (check [README](../README.md)).
+
+Read the register value:
+```
+./sdrctl dev sdr0 get reg tx_intf 13
+```
+
+Set the register value to N (a number larger than the value read back above):
+```
+./sdrctl dev sdr0 set reg tx_intf 13 N
+```
+Bigger value in that register could hurt the Tx EVM and long packet signal. You need to fine tune it for your case.
+
 ## Tx Lo and port config
 
 In normal operation, the Tx Lo and RF port are controled by FPGA automatically during signal Tx. To check the current Tx Lo and RF port switch status
@@ -198,7 +217,7 @@ Above command will fix the AD9361 in 5220MHz and let driver ignore frequency tun
 ```
 ./set_restrict_freq.sh 0
 ```
-To let openwifi work at arbitrary frequency, please check "Let openwifi work at arbitrary frequency" in https://github.com/open-sdr/openwifi/blob/master/doc/README.md#Regulation-and-channel-config
+To let openwifi work at arbitrary frequency, please check [Let openwifi work at arbitrary frequency](../README.md#let-openwifi-work-at-arbitrary-frequency)
 
 ## Receiver sensitivity control
 

doc/app_notes/hls.md

@@ -0,0 +1,38 @@
+<!--
+Author: Thijs Havinga
+SPDX-FileCopyrightText: 2019 UGent
+SPDX-License-Identifier: AGPL-3.0-or-later
+-->
+
+FCCM2023 Poster: [Thijs Havinga, et al. Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thijs-FCCM2023-poster.jpg)
+
+[Longer/detailed info about the poster](https://arxiv.org/abs/2305.13351)
+
+In order to speed up or ease FPGA development, it is possible to use High-Level Synthesis (HLS) for creating core baseband processing modules of openwifi. We have already programmed the receiver modules channel estimation and equalization in C++ and converted to Verilog using Vitis HLS. In order to use openwifi with these HLS modules, follow the [build instructions](#build-instructions).
+In order to modify these modules within Vitis HLS, follow [the instructions below](#modify-the-code-using-vitis-hls). 
+
+## Build instructions
+
+Follow the [Build FPGA](https://github.com/open-sdr/openwifi-hw#build-fpga) instructions till before generating ip_repo. In order to switch to the HLS-version of openofdm_rx, use the following commands:
+
+```
+cd ip/openofdm_rx
+git checkout dot11zynq_hls
+```
+
+Now continue with the instructions. Before generating the bitstream, update the openofdm_rx IP by making sure it is selected under "IP Status" and click "Upgrade Selected". Afterwards, continue with the instructions to generate the bitstream.
+
+## Modify the code using Vitis HLS
+When in the `openwifi-hw` folder, make sure to run:
+```
+./get_ip_openofdm_rx.sh
+cd ip/openofdm_rx
+git checkout dot11zynq_hls
+```
+Then start Vitis HLS and create a new project. Import either all source files (except those ending on '_test.cpp') in the [ch_gain_cal](https://github.com/open-sdr/openofdm/tree/dot11zynq_hls/hls/ch_gain_cal) or [equalizer](https://github.com/open-sdr/openofdm/tree/dot11zynq_hls/hls/equalizer) folder to modify the channel estimation or equalizer module, respectively. Choose either 'equalizer' or 'ch_gain_cal' as top-level module. Next, select `equalizer_test.cpp` or `ch_gain_cal_test.cpp` as testbench file. In 'Part selection', select the right part corresponding to your board. 
+
+After modifying the code and making sure C simulation and cosimulation is running fine, select 'Export RTL', which will generate a ZIP file with a folder `hdl/verilog` containing the generated Verilog files. Replace the current folder `openwifi-hw/ip/openofdm_rx/hls/equalizer/hdl/verilog/` (or `.../ch_gain_cal/hdl/verilog`) with this folder and change the `openofdm_rx.tcl` file to include the newly generated Verilog files. See [here](https://github.com/open-sdr/openofdm/blob/dot11zynq_hls/openofdm_rx.tcl#L268) for an example. If you modified the top-level function arguments, you will need to interface them accordingly in [dot11.v](https://github.com/open-sdr/openofdm/blob/dot11zynq_hls/verilog/dot11.v).
+
+Now follow the [Build FPGA](https://github.com/open-sdr/openwifi-hw#build-fpga) instructions, starting at the step "Generate ip_repo for the top level FPGA project". It will then use the modified .tcl file to include the correct files for your modified HLS module and build the FPGA using it.
+
+A similar approach can be followed to create other HLS modules, where you would need to execute these steps in the folder of the IP to be modified and integrate the modules in the corresponding top-level Verilog file.

doc/app_notes/iq.md

@@ -84,7 +84,7 @@ We implement the **IQ sample capture** with interesting extensions: many **trigg
   0 |receiver gives FCS checksum result. no matter pass/fail
   1 |receiver gives FCS checksum result. pass
   2 |receiver gives FCS checksum result. fail
-  3 |receiver gives SIGNAL field checksum result. no matter pass/fail
+  3 |the tx_intf_iq0 becomes non zero (the 1st I/Q out)
   4 |receiver gives SIGNAL field checksum result. pass
   5 |receiver gives SIGNAL field checksum result. fail
   6 |receiver gives SIGNAL field checksum result. no matter pass/fail. HT packet
@@ -166,6 +166,8 @@ We implement the **IQ sample capture** with interesting extensions: many **trigg
   The openwifi IQ capture feature could run with not only monitor mode but also other modes, such as AP-Client or ad-hoc mode. After the communication functionality is fully up in those modes, you can start IQ capture from "**insmod side_ch.ko**" and "**./side_ch_ctl g**" on board as described in the previous sections to extract IQ information to your computer.
 
 ## Map the IQ information to the WiFi packet
+  (See this https://github.com/open-sdr/openwifi/discussions/344 to understand how to map the collected data to the packet via the TSF timestamp)
+  
   If you want to relate the IQ information to the WiFi packet, you need to capture WiFi packets (tcpdump/wireshark/etc) while capturing IQ. Then you can relate the timestamp between WiFi packet and IQ information. Please be noticed that the timestamp in the IQ information is the moment when capture is triggered, which could be different from the timestamp reported in the packet capture program. But since they share the same time base (TSF timer), you can relate them easily by analyzing the WiFi packet and IQ sample sequence.
   
   Please learn the python and Matlab script to extract IQ information per capture according to your requirement.

doc/app_notes/packet-iq-self-loopback-test.md

@@ -5,38 +5,46 @@ SPDX-License-Identifier: AGPL-3.0-or-later
 -->
 
 One super power of the openwifi platform is "**Full Duplex**" which means that openwifi baseband can receive its own TX signal.
-This makes the IQ sample and WiFi packet self loopback test possible. Reading the normal IQ sample capture [app note](iq.md) will help if you have issue or 
-want to understand openwifi side channel (for IQ and CSI) deeper.
+This makes the IQ sample, WiFi packet and CSI self loopback test possible. Reading the normal [IQ sample capture app note](iq.md) and [CSI radar app note](radar-self-csi.md) will help if you have issue or want to understand openwifi side channel (for IQ and CSI) deeper.
 ![](./openwifi-loopback-principle.jpg)
 
 [[IQ self loopback quick start](#IQ-self-loopback-quick-start)]
 [[Check the packet loopback on board](#Check-the-packet-loopback-on-board)]
-[[Self loopback config](#Self-loopback-config)]
+[[IQ self loopback config](#IQ-self-loopback-config)]
+[[CSI FPGA self loopback quick start](#CSI-FPGA-self-loopback-quick-start)]
 
 ## IQ self loopback quick start
-(Please replace the IQ length **8187** by **4095** if you use low end FPGA board: zedboard/adrv9464z7020/antsdr/zc702)
+(Please replace the IQ length **8187** by **4095** if you use low end FPGA board: zedboard/adrv9464z7020/antsdr/zc702/sdrpi)
 - Power on the SDR board.
 - Put the Tx and Rx antenna as close as possible.
 - Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
   ```
+  # ssh into the SDR board, password: openwifi
   ssh root@192.168.10.122
-  (password: openwifi)
   cd openwifi
+  # Bring up the openwifi NIC sdr0
   ./wgd.sh
-  (Bring up the openwifi NIC sdr0)
+
+  # Setup monitor mode in WiFi channel 44. You should find a channel as clean as possible in your location. Note that some channels don't work, so stick to 44 or 48 for now.
   ./monitor_ch.sh sdr0 44
-  (Setup monitor mode in WiFi channel 44. You should find a channel as clean as possible in your location)
+
+  # Turn off CCA by setting a very high threshold that make the CSMA engine always think the channel is idle (no incoming signal is higher than this threshold)
+  ./sdrctl dev sdr0 set reg xpu 8 1000
+  
+  # Load side channel kernel module with buffer lenght of 8187 (replace this with 4095 when using low end FPGA board)
   insmod side_ch.ko iq_len_init=8187
-  ./side_ch_ctl wh11d0
-  (Set 0 to register 11. It means the pre trigger length is 0, so we only capture IQ after trigger condition is met)
+  
+  # Set 100 to register 11. It means the pre trigger length is 100, so we mainly capture IQ after trigger condition is met
+  ./side_ch_ctl wh11d100
+  # Set 16 to register 8 -- set trigger condition to phy_tx_started signal from openofdm tx core
   ./side_ch_ctl wh8d16
-  (Set 16 to register 8 -- set trigger condition to phy_tx_started signal from openofdm tx core)
+  # Unmute the baseband self-receiving to receive openwifi own TX signal/packet -- important for self loopback!
   ./sdrctl dev sdr0 set reg xpu 1 1
-  (Unmute the baseband self-receiving to receive openwifi own TX signal/packet -- important for self loopback!)
+  # Set the loopback mode to over-the-air
   ./side_ch_ctl wh5h0
-  (Set the loopback mode to over-the-air)
+  (./side_ch_ctl wh5h4 for FPGA internal loopback)
+  # Relay the FPGA IQ capture to the host computer that will show the captured IQ later on)
   ./side_ch_ctl g0
-  (Relay the FPGA IQ capture to the host computer that will show the captured IQ later on)
   ```
   You should see on outputs like:
   ```
@@ -50,11 +58,16 @@ want to understand openwifi side channel (for IQ and CSI) deeper.
   ```
   cd openwifi/inject_80211/
   make
-  (Build our example packet injection program)
+  # Build our example packet injection program
   ./inject_80211 -m n -r 5 -n 1 sdr0
-  (Inject one packet to openwifi sdr0 NIC)
+  # Inject one packet to openwifi sdr0 NIC
   ```
   Normally in the previous ssh session, the count becomes 1. It means one packet (of IQ sample) is sent and captured via loopback over the air.
+  
+  If 1 is not seen, you can try to put the receiver into reset state, so it won't block the system in case it runs into dead state
+  ```
+  ./sdrctl dev sdr0 set reg rx 0 1
+  ```
 
 - On your computer (NOT ssh onboard!), run:
   ```
@@ -80,7 +93,10 @@ to do further offline analysis, or feed the IQ sample to the openwifi receiver s
   ```
   tcpdump -i sdr0
   ```
-  Run the packet injection "./inject_80211 -m n -r 5 -n 1 sdr0" in another session, you should see the packet information printed by tcpdump from self over-the-air loopback.
+  Run the packet injection "./inject_80211 -m n -r 5 -n 1 sdr0" in another session, you should see the packet information printed by tcpdump from self over-the-air loopback. In case you put the receiver into reset state in the previous IQ loopback, you should put the receiver back to normal for packet loopback (otherwise the receiver won't decode the IQ signal back to packet):
+  ```
+  ./sdrctl dev sdr0 set reg rx 0 0
+  ```
   
 - You can also see the openwifi printk message of Rx packet (self Tx looped back) while the packet comes to the openwifi Rx interrupt.
   A new ssh session to the board should be opened to do this before running the packet injection:
@@ -88,7 +104,7 @@ to do further offline analysis, or feed the IQ sample to the openwifi receiver s
   cd openwifi
   ./sdrctl dev sdr0 set reg drv_rx 7 7
   ./sdrctl dev sdr0 set reg drv_tx 7 7
-  (Turn on the openwifi Tx/Rx printk logging)
+  # Turn on the openwifi Tx/Rx printk logging
   ```
   Stop the "./side_ch_ctl g0" in the very first ssh session. Run the packet injection, then check the printk message:
   ```
@@ -97,7 +113,7 @@ to do further offline analysis, or feed the IQ sample to the openwifi receiver s
   ```
   You should see the printk message of packet Tx and Rx from the openwifi driver (sdr.c).
 
-## Self loopback config
+## IQ self loopback config
 
 - By default, the loopback is via the air (from Tx antenna to Rx antenna). FPGA inernal loopback option is offered to have IQ sample and packet without 
   any interference. To have FPGA internal loopback, replace the "./side_ch_ctl wh5h0" during setup (the very 1st ssh session) by:
@@ -113,3 +129,34 @@ to do further offline analysis, or feed the IQ sample to the openwifi receiver s
 
 - To understand deeper of all above commands/settings, please refer to [Capture IQ sample, AGC gain, RSSI with many types of trigger condition](iq.md) and
   [Capture dual antenna TX/RX IQ for multi-purpose (capture collision)](iq_2ant.md)
+  
+## CSI FPGA self loopback quick start
+
+This section will show how to connect the WiFi OFDM transmitter to the receiver directly inside FPGA, and show the ideal CSI/constellation/frequency-offset. (For CSI over the air loopback, please refer to [CSI radar app note](radar-self-csi.md))
+
+Command sequence on board:
+```
+cd openwifi
+./wgd.sh
+./monitor_ch.sh sdr0 6
+insmod side_ch.ko
+./side_ch_ctl g
+```
+Open another ssh session on board, then:
+```
+cd openwifi
+./sdrctl dev sdr0 set reg rx_intf 3 256
+(Above command let the FPGA Tx IQ come to receiver directly. Set 256 back to 0 to let receiver back connect to AD9361 RF frontend)
+./sdrctl dev sdr0 set reg rx 5 768
+(Disable the receiver FFT window shift. By default it is 1 (768+1) -- good for multipath, overfitting for direct loopback)
+./inject_80211/inject_80211 -m n -r 7 -n 99999 -s 1400 -d 1000000 sdr0
+(Transmit 802.11n MCS7 1400Byte packet every second)
+```
+
+Command on computer:
+```
+cd openwifi/user_space/side_ch_ctl_src
+python3 side_info_display.py
+```
+Now you should see the following screenshot that shows the CSI/constellation/frequency-offset over this in-FPGA ideal channel.
+![](./openwifi-csi-fpga-loopback.jpg)

doc/app_notes/perf_counter.md

@@ -61,4 +61,4 @@ register idx|meaning               |note
 
 Note: addr2 (source/sender's MAC address) target setting uses only 32bit. For address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
 
-Note: read register 37 of xpu for some addr2 captured by the receiver
+Note: read register 62 of xpu for some addr2 captured by the receiver

doc/app_notes/radar-self-csi.md

@@ -6,6 +6,9 @@ SPDX-License-Identifier: AGPL-3.0-or-later
 
 One super power of the openwifi platform is "**Full Duplex**" which means that openwifi baseband can receive its own TX signal. Just like a radar! This brings a unique capability of "**joint radar and communication**" to openwifi. For instance, put two directional antennas to openwifi TX and RX, and the **CSI** (Channel State Information) of the self-TX signal will refect the change of the target object.
  ![](./openwifi-radar.jpg)
+ ![](./sensing.png)
+
+(See this https://github.com/open-sdr/openwifi/discussions/344 to understand how to map the collected data to the packet via the TSF timestamp)
 
 ## Quick start
 - Power on the SDR board.
@@ -13,42 +16,57 @@ One super power of the openwifi platform is "**Full Duplex**" which means that o
   ```
   ssh root@192.168.10.122
   (password: openwifi)
-  cd openwifi
-  ./fosdem.sh
-  (After the AP started by above command, you can connect a WiFi client to this openwifi AP)
-  (Or setup other scenario according to your requirement)
-  ifconfig
-  (Write down the openwifi AP MAC address. For example 66:55:44:33:22:5a)
-  insmod side_ch.ko num_eq_init=0
+  ```
+- On computer, build the latest driver and FPGA package after clone/update openwifi and openwifi-hw-img repository:
+  ```
+  export XILINX_DIR=your_Xilinx_install_directory
+  (Example: export XILINX_DIR=/opt/Xilinx. The Xilinx directory should include sth like: Downloads, Vitis, etc.)
+  export OPENWIFI_HW_IMG_DIR=your_openwifi-hw-img_directory
+  (The directory where you get the open-sdr/openwifi-hw-img repo via git clone)
+  export BOARD_NAME=your_board_name
+  (Check the BOARD_NAME definitions in README)
+
+  cd openwifi/user_space
+  ./drv_and_fpga_package_gen.sh $OPENWIFI_HW_IMG_DIR $XILINX_DIR $BOARD_NAME
+  scp drv_and_fpga.tar.gz root@192.168.10.122:openwifi/
+  scp ./side_ch_ctl_src/side_ch_ctl.c root@192.168.10.122:openwifi/
+  scp ./inject_80211/* root@192.168.10.122:openwifi/inject_80211/
+  ```
+- On SDR board (/root/openwifi directory):
+  ```
+  cd /root/openwifi/
+  ./wgd.sh drv_and_fpga.tar.gz
+  ./monitor_ch.sh sdr0 1
+  insmod ./drv_and_fpga/side_ch.ko
+  gcc -o side_ch_ctl side_ch_ctl.c
   ./side_ch_ctl wh1h4001
   ./side_ch_ctl wh7h4433225a
-  (Above two commands ensure receiving CSI only from XX:XX:44:33:22:5a. In this case, it is the openwifi self-TX)
+  (Above two commands ensure receiving CSI only from XX:XX:44:33:22:5a, which will be set by our own packet injector later)
   ./sdrctl dev sdr0 set reg xpu 1 1
   (Above unmute the baseband self-receiving to receive openwifi own TX signal/packet)
   ./side_ch_ctl g0
   ```
-  You should see on board outputs like:
+- Open another ssh session on SDR board:
   ```
-  loop 64 side info count 4
-  loop 128 side info count 5
-  ...
+  cd /root/openwifi/inject_80211
+  make
+  ./inject_80211 -m g -r 4 -t d -e 0 -b 5a -n 99999999 -s 20 -d 1000 sdr0
+
+  (Above command injects the 802.11a/g packet, for 802.11n packet please use:
+  ./inject_80211 -m n -r 4 -t d -e 8 -b 5a -n 99999999 -s 20 -d 1000 sdr0)
   ```
-  If the second number (4, 5, ...) keeps increasing, that means the CSI is going to the computer smoothly.
-  
-- On your computer (NOT ssh onboard!), run:
+- Now you should see the increasing numbers in the previous ssh terminal of the SDR board.
+- On your computer (NOT ssh session!), run:
   ```
   cd openwifi/user_space/side_ch_ctl_src
-  python3 side_info_display.py 0
+  python3 side_info_display.py 8 waterfall
   ```
-  The python script needs "matplotlib.pyplot" and "numpy" packages installed. Now you should see figures showing run-time **CSI** and **frequency offset**. Meanwhile the python script prints the **timestamp**.
-  ![](./csi-screen-shot-radar.jpg)
-  
-  While running, all CSI data is also stored into a file **side_info.txt**. A matlab script **test_side_info_file_display.m** is offered to help you do CSI analysis offline. In this case, run **test_side_info_file_display(0)** in Matlab.
-  ![](./csi-screen-shot-radar-matlab.jpg)
-  
-  The following picture is generated by data processing on the captured openwifi CSI while people move in front of two directional antennas (Tx/Rx antenna).
+  The python script needs "matplotlib.pyplot" and "numpy" packages installed. Now you should see figures showing run-time **CSI**, **CSI waterfall**, **Equalizer out** and **frequency offset**. The following photo shows the CSI change in the waterfall plot when I left my seat in front of two directional antennas (Tx/Rx antenna).
   ![](./sensing.png)
   
+  While running, all CSI data is also stored into a file **side_info.txt**. A matlab script **test_side_info_file_display.m** is offered to help you do CSI analysis offline. In this case, run **test_side_info_file_display** in Matlab.
+  ![](./csi-screen-shot-radar-matlab.jpg)
+  
 Please learn the python and Matlab script for CSI data structure per packet according to your requirement.
   
 Do read the [normal CSI app note](csi.md) to understand the basic implementation architecture.

doc/cite-openwifi-github-code.md

@@ -1,8 +1,8 @@
 ```
 @electronic{openwifigithub,
-            author = {Jiao, Xianjun and Liu, Wei and Mehari, Michael},
+            author = {Jiao, Xianjun and Liu, Wei and Mehari, Michael and Thijs, Havinga and Muhammad, Aslam},
             title = {open-source IEEE802.11/Wi-Fi baseband chip/FPGA design},
-            url = {https://github.com/open-sdr/openwifi},
-            year = {2019},
+            url = {https://github.com/open-sdr},
+            year = {2023},
 }
 ```

doc/img_build_instruction/kuiper.md

@@ -0,0 +1,159 @@
+**IMPORTANT pre-conditions**:
+- Install Vivado 2021.1. Make sure install Vitis as well. You should have this directory: your_Xilinx_install_directory/Vitis (NOT Vitis_HLS!)
+  - If the Vitis is not installed, you can add it by running "Xilinx Design Tools --> Add Design Tools for Devices 2021.1" from Xilinx program group/menu in your OS start menu, or Help menu of Vivado.
+- SD card at least with 16GB
+- Install packages: `sudo apt install flex bison libssl-dev device-tree-compiler u-boot-tools -y`
+
+[[Use openwifi prebuilt img](#Use-openwifi-prebuilt-img)]
+[[Build SD card from scratch](#Build-SD-card-from-scratch)]
+[[Use existing SD card on new board](#Use-existing-SD-card-on-new-board)]
+
+## Use openwifi prebuilt img
+
+Download openwifi pre-built img (see [Quick start](../../README.md#quick-start)), and extract it to .img file.
+
+Use dd command to flash the SD card. (Or other software like Startup Disk Creator in Ubuntu)
+```
+sudo dd bs=512 count=31116288 if=openwifi-xyz.img of=/dev/your_sdcard_dev
+```
+To have correct count value, better to check the .img file actual situation by "fdisk -l img_filename".
+
+Then start from the 2nd step of the [Quick start](../../README.md#quick-start) in README.
+
+## Build SD card from scratch
+
+Download image_2022-08-04-ADI-Kuiper-full.zip from https://wiki.analog.com/resources/tools-software/linux-software/kuiper-linux?redirect=1
+
+Extract it to .img file.
+
+Use dd command to flash the SD card. (Or other software like Startup Disk Creator in Ubuntu)
+```
+sudo dd bs=512 count=24018944 if=2022-08-04-ADI-Kuiper-full.img of=/dev/your_sdcard_dev
+```
+
+(To have correct count value, better to check the .img file actual situation by "fdisk -l img_filename". While making .img from SD card, check the SD card dev instead)
+
+Mount the BOOT and rootfs partition of SD card to your computer.
+
+Change the SD card file: Add following into rootfs/etc/network/interfaces
+```
+# The loopback interface
+auto lo
+iface lo inet loopback
+auto eth0
+iface eth0 inet static
+
+#your static IP
+address 192.168.10.122
+
+#your gateway IP
+gateway 192.168.10.1
+netmask 255.255.255.0
+
+#your network address "family"
+network 192.168.10.0
+broadcast 192.168.10.255
+```
+
+Change the SD card file: Add following into rootfs/etc/sysctl.conf
+```
+net.ipv4.ip_forward=1
+```
+
+Change the SD card file: Add following into rootfs/etc/systemd/system.conf
+```
+DefaultTimeoutStopSec=2s
+```
+
+Put the openwifi/kernel_boot/10-network-device.rules into rootfs/etc/udev/rules.d/
+
+Run **update_sdcard.sh** from openwifi/user_space directory to further prepare the SD card. The last argument $SDCARD_DIR of the script is the directory (mounting point) on your computer that has BOOT and rootfs directories/partitions.
+
+The script will build and put following things into the SD card:
+  - Linux kernel image file ([Update Driver](../../README.md#Update-Driver)): 
+    - adi-linux-64/arch/arm64/boot/Image (64bit)
+    - adi-linux/arch/arm/boot/uImage (32bit)
+  - devicetree file:
+    - openwifi/kernel_boot/boards/zcu102_fmcs2/system.dtb (64bit)
+    - openwifi/kernel_boot/boards/$BOARD_NAME/devicetree.dtb (32bit)
+  - BOOT.BIN ([Update FPGA](../../README.md#Update-FPGA)):
+    - openwifi/kernel_boot/boards/$BOARD_NAME/output_boot_bin/BOOT.BIN
+  - openwifi driver ([Update Driver](../../README.md#Update-Driver)).
+  - openwifi/user_space files and openwifi/webserver files
+
+After **update_sdcard.sh** finishes, please do the 2nd step "Config the correct files ..." in [Quick start](../../README.md#quick-start). Then power on the board with the SD card, connect the board to your host PC (static IP 192.168.10.1) via ethernet, and ssh to the board with password **"analog"**
+```
+ssh root@192.168.10.122
+```
+
+Then change password to "openwifi" via "passwd" command onbard.
+
+Enlarge the onboard SD disk space, and reboot (https://github.com/analogdevicesinc/adi-kuiper-gen/releases)
+```
+raspi-config --expand-rootfs
+reboot now
+```
+Setup routing/NAT **on the PC** for your board -- this internet connection is **important** for post installation/config.
+```
+sudo sysctl -w net.ipv4.ip_forward=1
+sudo iptables -t nat -A POSTROUTING -o NICY -j MASQUERADE
+sudo ip route add 192.168.13.0/24 via 192.168.10.122 dev ethX
+```
+**ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet).
+
+If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC.
+
+Test the connectivity. Run on board (in the ssh session):
+```
+route add default gw 192.168.10.1
+ping IP_YOU_KNOW_ON_YOUR_NETWORK
+```
+If there is issue with the connectivity (ping can not reach the target), it needs to be solved before going to the next step.
+
+Do misc configurations/installations in the ssh session onboard:
+```
+sudo apt update
+chmod +x /root/openwifi/*.sh
+
+# install and setup dhcp server
+sudo apt-get -y install isc-dhcp-server
+cp /root/openwifi/dhcpd.conf /etc/dhcp/dhcpd.conf
+
+# install hostapd and other useful tools
+sudo apt-get -y install hostapd
+sudo apt-get -y install tcpdump
+sudo apt-get -y install webfs
+sudo apt-get -y install iperf
+sudo apt-get -y install iperf3
+sudo apt-get -y install libpcap-dev
+sudo apt-get -y install bridge-utils
+
+# build on board tools
+sudo apt-get -y install libnl-3-dev
+sudo apt-get -y install libnl-genl-3-dev
+cd /root/openwifi/sdrctl_src
+make clean
+make
+cp sdrctl ../
+cd /root/openwifi/side_ch_ctl_src/
+gcc -o side_ch_ctl side_ch_ctl.c
+cp side_ch_ctl ../
+cd /root/openwifi/inject_80211/
+make clean
+make
+cd ..
+```
+
+Run openwifi in the ssh session onboard:
+```
+/root/openwifi/setup_once.sh (Only need to run once for new board)
+cd /root/openwifi
+./wgd.sh
+ifconfig sdr0 up
+iwlist sdr0 scan
+./fosdem.sh
+```
+
+## Use existing SD card on new board
+
+Just operate the existing/working SD card of the old board on your computer starting from the 2nd step of the [Quick start](../../README.md#quick-start) in README. Then start using the SD card on the new board.

doc/known_issue/notter.md

@@ -0,0 +1,52 @@
+# Known issue
+
+- [Network issue in quick start](#Network-issue-in-quick-start)
+- [EXT4 fs error rootfs issue](#EXT4-fs-error-rootfs-issue)
+- [antsdr e200 UART console](#antsdr-e200-UART-console)
+- [Client can not get IP](#Client-can-not-get-IP)
+- [No space left on device](#No-space-left-on-device)
+
+## Network issue in quick star
+
+- OS: Ubuntu 22 LTS
+- image: [openwifi img](https://drive.google.com/file/d/1fb8eJGJAntOciCiGFVLfQs7m7ucRtSWD/view?usp=share_link)
+
+If can't ssh to the board via Ethernet for the 1st time, you might need to delete /etc/network/interfaces.new on SD card (on your computer).
+
+If still can't ssh the board via Ethernet, you should use UART console (/dev/ttyUSBx, /dev/ttyCH341USBx, etc.) to monitor what happened during booting.
+
+## EXT4 fs error rootfs issue
+
+Sometimes, the 1st booting after flashing SD card might encounter "EXT4-fs error (device mmcblk0p2): ..." error on neptunesdr, changing SD card flashing tool might solve this issue. Some tool candidates:
+- gnome-disks
+- Startup Disk Creator
+- win32diskimager
+
+## antsdr e200 UART console
+
+If can't see the UART console in Linux (/dev/ttyUSB0 or /dev/ttyCH341USB0), according to https://github.com/juliagoda/CH341SER, you might need to do `sudo apt remove brltty`
+
+## Client can not get IP
+
+If the client can not get IP from the openwifi AP, just re-run "service isc-dhcp-server restart" on board and do re-connect from the client.
+
+## No space left on device
+It might be due to too many dmesg/log/journal, disk becomes full. 
+```
+systemd-journald[5694]: Failed to open system journal: No space left on device
+```
+You can try following operations.
+```
+systemd-tmpfiles --clean
+sudo systemd-tmpfiles --remove
+rm /var/log/* -rf
+apt --autoremove purge rsyslog
+```
+Add followings into `/etc/systemd/journald.conf`
+```
+SystemMaxUse=64M
+Storage=volatile
+RuntimeMaxUse=64M
+ForwardToConsole=no
+ForwardToWall=no
+```

doc/publications.md

@@ -4,27 +4,95 @@ SPDX-FileCopyrightText: 2021 UGent
 SPDX-License-Identifier: AGPL-3.0-or-later
 -->
 
-If your work uses openwifi, please cite the first VTC2020 openwifi paper: [LaTex example](cite-openwifi-vtc-paper.md)
+If openwifi is one of your references, please cite the VTC2020 paper: [LaTex example](cite-openwifi-vtc-paper.md)
 
 You can also cite openwifi github code: [LaTex example](cite-openwifi-github-code.md).
 
-Other openwifi related publications:
+Publications in category:
+- [Feature Functionality and System](#Feature-Functionality-and-System)
+- [TSN Time Sensitive Network and RT Real Time](#TSN-Time-Sensitive-Network-and-RT-Real-Time)
+- [CSI Sensing and Security](#CSI-Sensing-and-Security)
+- [WiFi and Cellular 5G 6G](#WiFi-and-Cellular-5G-6G)
+
+## Feature Functionality and System
 - [Xianjun Jiao, et al. openwifi: a free and open-source IEEE802.11 SDR implementation on SoC. VTC2020 spring Antwerp](https://www.orca-project.eu/wp-content/uploads/sites/4/2020/03/openwifi-vtc-antwerp-PID1249076.pdf)
-- [Marco Cominelli, et al. CSI MURDER. ORCA project opencall 2019](https://ans.unibs.it/projects/csi-murder/)
-- [Marco Cominelli, et al. IEEE 802.11 CSI randomization to preserve location privacy: An empirical evaluation in different scenarios. ELSEVIER Computer Networks, 2021](https://www.sciencedirect.com/science/article/abs/pii/S138912862100102X)
+- [Cedric Den Haese, The initial 802.11n 2*2 MIMO and diversity (CSD/Combining) work. UGent master thesis 2021](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Cedric_Den_Haese_masterproef.pdf)
+- [Paul Zanna, et al. A novel method for utilizing RF information from IEEE 802.11 frames in Software Defined Networks. MethodsX 2021](https://www.sciencedirect.com/science/article/pii/S2215016121003368)
+- [Thijs Havinga, et al. WIP: Achieving Self-Interference-Free Operation on SDR Platform with Critical TDD Turnaround Time. accepted WoWMoM2022 paper](https://arxiv.org/abs/2204.07354)
+- [Yingshuo Xi, Baiming Zhang. High-Throughput Open Source Viterbi Decoder for OpenWiFi. 2022 KU Leuven master thesis](https://github.com/BaimingZhang26213/viterbi_decoder)
+- [Merkebu Girmay, et al. Technology recognition and traffic characterization for wireless technologies in ITS band. Vehicular Communications Volume 39, February 2023, 100563](https://doi.org/10.1016/j.vehcom.2022.100563)
+- [Thijs Havinga, et al. Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis. FCCM2023 Poster](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thijs-FCCM2023-poster.jpg), [[Longer/detailed info about the poster](https://arxiv.org/abs/2305.13351)]
+- [Merkebu Girmay, et al. Intelligent Spectrum Sharing Between LTE and Wi-Fi Networks using Muted MBSFN Subframes. WAMICON 2023](https://ieeexplore.ieee.org/abstract/document/10124903)
+- [Thijs Havinga, et al. Improved TDD operation on Software-Defined Radio platforms towards future wireless standards. Computer Communications, Volume 209, 1 September 2023, Pages 178-187](https://doi.org/10.1016/j.comcom.2023.06.026)
+- [Yuyang Du, et al. The Power of Large Language Models for Wireless Communication System Development: A Case Study on FPGA Platforms. arxiv, Submitted on 14 Jul 2023 (v1), last revised 5 Sep 2023 (this version, v2)](https://arxiv.org/abs/2307.07319)
+- [Muhammad Aslam, et al. A novel hardware efficient design for IEEE 802.11ax compliant OFDMA transceiver](https://www.sciencedirect.com/science/article/pii/S0140366424000926?dgcid=coauthor)
+- [Trio Adiono, et al. FPGA Implementation of SFO for OFDM-based Network Enabled Li-Fi System. IEEE ISCAS 2024](https://ieeexplore.ieee.org/abstract/document/10557957)
+- [Trio Adiono, et al. A Scalable Design of A Full-Stack Real-Time OFDM Baseband Processor for Network-Enabled VLC Systems. IEEE Access 2024](https://ieeexplore.ieee.org/document/10589620)
+- [Roni Fagerholm, FPGA-based DECT-2020 New Radio Packet Detection. Master thesis, Aalto University, 30 September 2024](https://aaltodoc.aalto.fi/server/api/core/bitstreams/a5105c46-f4c6-4034-8024-96ed9e440feb/content)
+- [Hao Zhou, et al. Large Language Model (LLM) for Telecommunications: A Comprehensive Survey on Principles, Key Techniques, and Opportunities. IEEE Communications Surveys & Tutorials 2024](https://ieeexplore.ieee.org/document/10685369)
+- [Thijs Havinga, et al. Wi-Fi 6 Cross-Technology Interference Detection and Mitigation by OFDMA: an Experimental Study. arXiv, Submitted to EuCNC & 6G Summit 2025](https://arxiv.org/abs/2503.05429)
+- [Shyam Krishnan Venkateswaran, et al. Target wake time in IEEE 802.11 WLANs: Survey, challenges, and opportunities. Computer Communications, 2025](https://www.sciencedirect.com/science/article/pii/S0140366425000842)
+
+## TSN Time Sensitive Network and RT Real Time
 - [Jetmir Haxhibeqiri, et al. Enabling TSN over IEEE 802.11: Low-overhead Time Synchronization for Wi-Fi Clients. ICIT2021](https://biblio.ugent.be/publication/8700714/file/8700715.pdf)
-- [Xianjun Jiao, et al. Openwifi CSI fuzzer for authorized sensing and covert channels. ACM WiSec 2021](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255)
 - [Ingrid Moerman, et al. Wireless Time-Sensitive Networks: When Every Microsecond Counts. Microwaves&RF, 2021](https://www.mwrf.com/technologies/systems/article/21164984/wireless-timesensitive-networks-when-every-microsecond-counts)
 - [Muhammad Aslam, et al. High precision time synchronization on Wi-Fi based multi-hop network. CNERT2021](https://biblio.ugent.be/publication/8709058/file/8709060.pdf)
-- [Hongjian Cao, et al. OWFuzz: WiFi Protocol Fuzzing Tool Based on OpenWiFi. Blackhat asia 2021](https://www.blackhat.com/asia-21/arsenal/schedule/#owfuzz-wifi-protocol-fuzzing-tool-based-on-openwifi-22569), [[**code**]](https://github.com/alipay/Owfuzz)
-- [Cedric Den Haese, The initial 802.11n 2*2 MIMO and diversity (CSD/Combining) work. UGent master thesis 2021](https://users.ugent.be/~xjiao/Cedric_Den_Haese_masterproef.pdf)
-- [Steven Heijse, IEEE 802.11 Physical Layer Fuzzing Using OpenWifi. UGent master thesis 2021](https://users.ugent.be/~xjiao/Steven_Heijse_masterproef.pdf)
 - [Ingrid Moerman, et al. Interoperable Time-Sensitive Networking Towards 6G (invited presentation)](https://biblio.ugent.be/publication/8719532/file/8719533.pdf)
-- [Lihao Zhang, et al. A Just-In-Time Networking Framework for Minimizing Request-Response Latency of Wireless Time-Sensitive Applications. Arxiv 2021](https://arxiv.org/abs/2109.03032)
+- [Lihao Zhang, et al. A Just-In-Time Networking Framework for Minimizing Request-Response Latency of Wireless Time-Sensitive Applications. Arxiv 2021. Accepted by IEEE IoT journal 2022.](https://arxiv.org/abs/2109.03032)
+- [Jetmir Haxhibeqiri, et al. Enabling TSN over IEEE 802.11: Low-overhead Time Synchronization for Wi-Fi Clients. 22nd IEEE International Conference on Industrial Technology (ICIT) 2021](https://ieeexplore.ieee.org/document/9453686)
 - [Jetmir Haxhibeqiri, et al. Bringing Time-Sensitive Networking to Wireless Professional Private Networks. Wireless Personal Communications 2021](https://link.springer.com/article/10.1007/s11277-021-09056-0)
-- [Paul Zanna, et al. A novel method for utilizing RF information from IEEE 802.11 frames in Software Defined Networks. MethodsX 2021](https://www.sciencedirect.com/science/article/pii/S2215016121003368)
 - [Muhammad Aslam, et al. Hardware Efficient Clock Synchronization across Wi-Fi and Ethernet Based Network Using PTP. IEEE Transactions on Industrial Informatics 2021](https://ieeexplore.ieee.org/document/9573364)
-- [Luca Baldesi, et al. ChARM: NextG Spectrum Sharing Through Data-Driven Real-Time O-RAN Dynamic Control. INFOCOM 2022](https://ece.northeastern.edu/wineslab/papers/BaldesiInfocom22.pdf)
 - [Zelin Yun, et al. RT-WiFi on Software-Defined Radio: Design and Implementation. accepted RTAS2022 paper and demo](https://arxiv.org/abs/2203.10390)
+- [Pablo Avila-Campos, et al. Beacon-Based Wireless TSN Association. 2022 IEEE INFOCOM](https://imec-publications.be/bitstream/handle/20.500.12860/40111/8126_acc.pdf?sequence=2)
+- [Pablo Avila-Campos, et al. Impactless Beacon-Based Wireless TSN Association Procedure. 2022 IEEE 18th International Conference on Factory Communication Systems (WFCS)](https://ieeexplore.ieee.org/abstract/document/9779186)
+- [Jetmir Haxhibeqiri, et al. Safety-related Applications over Wireless Time-Sensitive Networks. IEEE ETFA 2022](https://biblio.ugent.be/publication/8770625/file/8770627.pdf)
+- [Pablo Avila-Campos, et al. Removing the Wires in Time-Sensitive Networks. 2022 61st FITCE International Congress Future Telecommunications: Infrastructure and Sustainability (FITCE)](https://ieeexplore.ieee.org/abstract/document/9934268)
+- [Pablo Avila-Campos, et al. Periodic Control Traffic Support in a Wireless Time-Sensitive Network. 2022 13th International Conference on Network of the Future (NoF)](https://ieeexplore.ieee.org/document/9942586)
+- [Gilson Miranda, et al. The Quality-Aware and Vertical-Tailored Management of Wireless Time-Sensitive Networks. IEEE Internet of Things Magazine ( Volume: 5, Issue: 4, December 2022)](https://ieeexplore.ieee.org/abstract/document/10012491)
+- [Gilson Miranda, et al. Enabling Time-Sensitive Network Management Over Multi-Domain Wired/Wi-Fi Networks. IEEE Transactions on Network and Service Management, 2023)](https://ieeexplore.ieee.org/document/10121738)
+- [Jetmir Haxhibeqiri, et al. To update or not: Dynamic traffic classification for high priority traffic in wireless TSN. IEEE WFCS2023](http://hdl.handle.net/1854/LU-01GZNGJFAJQRM3NX7FY5VRB4MR)
+- [Pablo Avila-Campos, et al. Residual Service Time Optimization for legacy Wireless-TSN end nodes. 2023 19th International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob). p.466-471](https://ieeexplore.ieee.org/document/10187722)
+- [Dirk Dahlhaus, et al. Towards Functional Safety in Dynamic Distributed Systems. Journal of Mobile Multimedia, Vol. 20 1, 1–24.](https://biblio.ugent.be/publication/01HGD7JAZY0YAQ1T13HQV35JC0/file/01HGD7PD2WRP9QW7J1G964Z6Y7.pdf)
+- [Kouros Zanbour, et al. A Comprehensive Survey of Wireless Time-Sensitive Networking (TSN): Architecture, Technologies, Applications, and Open Issues. arXiv, 2 Dec 2023](https://arxiv.org/abs/2312.01204)
+- [Jetmir Haxhibeqiri, et al. Coordinated Spatial Reuse for WiFi Networks: A Centralized Approach. IEEE 20th International Conference on Factory Communication Systems (WFCS) 2024](https://ieeexplore.ieee.org/document/10540785/)
+- [Jetmir Haxhibeqiri, et al. Coordinated SR and Restricted TWT for Time Sensitive Applications in WiFi 7 Networks. IEEE Communications Magazine 2024](https://ieeexplore.ieee.org/document/10634074/)
+- [Ozgur Ozkaya, et al. Simulating and Validating openwifi W-TSN in ns-3, IEEE 20th International Conference on Factory Communication Systems (WFCS) 2024](https://ieeexplore.ieee.org/document/10540899)
+- [Pablo Avila-Campos, et al. Impactless association methods for wi-fi based time-sensitive networks. Wireless Networks Journal, 2024](https://dl.acm.org/doi/10.1007/s11276-024-03681-w)
+- [Pablo Avila-Campos, et al. Unlocking Mobility for Wi-Fi-based Wireless Time-Sensitive Networks. IEEE Access, 2024](https://ieeexplore.ieee.org/document/10443947)
+- [Analog Devices, AN-2597: An OFDM-Based HDL Reference Modem Using the AD936x RF Transceivers. November, 2024](https://www.analog.com/en/resources/app-notes/an-2597.html)
+- [Tianyu Zhang, et al. A Survey on Industrial Internet of Things (IIoT) Testbeds for Connectivity Research. arXiv 2024](https://arxiv.org/abs/2404.17485)
+- [Louis Adriaens, High-Precision Wireless Synchronization: When Wi-Fi meets UWB. IEEE/SICE International Symposium on System Integration (SII) 2025](https://ieeexplore.ieee.org/document/10870915)
+- [Yongchao Dang, Open Radio Intelligent Controller based Wireless Time Sensitive Networking for Industry 5.0. TechRxiv 2025](https://www.techrxiv.org/doi/full/10.36227/techrxiv.173750009.95972083)
+
+## CSI Sensing and Security
+- [Marco Cominelli, et al. CSI MURDER. ORCA project opencall 2019](https://ans.unibs.it/projects/csi-murder/)
+- [Marco Cominelli, et al. IEEE 802.11 CSI randomization to preserve location privacy: An empirical evaluation in different scenarios. ELSEVIER Computer Networks, 2021](https://www.sciencedirect.com/science/article/abs/pii/S138912862100102X)
+- [Xianjun Jiao, et al. Openwifi CSI fuzzer for authorized sensing and covert channels. ACM WiSec 2021](https://dl.acm.org/doi/pdf/10.1145/3448300.3468255)
+- [Hongjian Cao, et al. OWFuzz: WiFi Protocol Fuzzing Tool Based on OpenWiFi. Blackhat asia 2021](https://www.blackhat.com/asia-21/arsenal/schedule/#owfuzz-wifi-protocol-fuzzing-tool-based-on-openwifi-22569), [[**code**]](https://github.com/alipay/Owfuzz)
+- [Steven Heijse, IEEE 802.11 Physical Layer Fuzzing Using OpenWifi. UGent master thesis 2021](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Steven_Heijse_masterproef.pdf)
+- [Jasper Devreker, Developing IEEE 802.11 PHY fuzzing capabilities using the open source Openwifi project. UGent master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Jasper_Devreker_masterproef.pdf)
+- [Thomas Schuddinck, Cybersecurity: Breaking IEEE 802.11 Devices at the Physical Layer. UGent master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thomas_Schuddinck_masterproef.pdf)
+- [Seppe Dejonckheere, The design of a CSI sensing authorisation mechanism using the open source Openwifi project. UGnet master thesis 2022](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Seppe_Dejonckheere_masterproef.pdf)
+- [Marco Cominelli, et al. On the properties of device-free multi-point CSI localization and its obfuscation. ELSEVIER Computer Communications, 2022](https://www.sciencedirect.com/science/article/pii/S014036642200086X)
+- [Renato Lo Cigno, et al. Integrating CSI Sensing in Wireless Networks: Challenges to Privacy and Countermeasures. IEEE Network, 2022](https://ieeexplore.ieee.org/document/9919763)
+- [Renato Lo Cigno, et al. AntiSense: Standard-compliant CSI obfuscation against unauthorized Wi-Fi sensing. ELSEVIER Computer Communications, 2022](https://www.sciencedirect.com/science/article/pii/S0140366421004916)
+- [Mathy Vanhoef, et al. Testing and Improving the Correctness of Wi-Fi Frame Injection. ACM WiSec 2023](https://papers.mathyvanhoef.com/wisec2023-wifi-injection.pdf)
+- [Wen Liu, et al. A New Paradigm for Device-free Indoor Localization: Deep Learning with Error Vector Spectrum in Wi-Fi Systems. PIMRC 2023](https://arxiv.org/pdf/2304.06490.pdf)
+- [Paul Zanna, et al. Preventing Attacks on Wireless Networks Using SDN Controlled OODA Loops and Cyber Kill Chains. Sensors 2022, 22(23), 9481](https://www.mdpi.com/1986552)
+- [Hayoung Seong, et al. Practical Covert Wireless Unidirectional Communication in IEEE 802.11 Environment, IEEE Internet of Things Journal ( Volume: 10, Issue: 2, 15 January 2023)](https://ieeexplore.ieee.org/abstract/document/9881568)
+- [Fan Qi, et al. Deep Learning-based CSI Feedback in Wi-Fi Systems, arxiv, 2024](https://arxiv.org/pdf/2407.05905)
+- [Lorenzo Ghiro, et al. Wi-Fi Localization Obfuscation: An implementation in openwifi. ELSEVIER Computer Communications, 2023](http://www.sciencedirect.com/science/article/pii/S0140366423001111)
+- [Andreas Toftegaard Kristensen, et al. Monostatic Multi-Target Wi-Fi-Based Breathing Rate Sensing Using Openwifi, IEEE Wireless Communications and Networking Conference (WCNC) 2024](https://ieeexplore.ieee.org/document/10570912)
+- [Andreas Toftegaard Kristensen, et al. An SDR-Based Monostatic Wi-Fi System with Analog Self-Interference Cancellation for Sensing, arXiv, 11 DEC 2024](https://arxiv.org/abs/2412.08612) [[**block diagram**](AnSIC-sensing-correction.png)]
+- [Jesus A. Armenta-Garcia, et al. Wireless sensing applications with Wi-Fi Channel State Information, preprocessing techniques, and detection algorithms: A survey. Computer Communications Volume 224, 1 August 2024](https://www.sciencedirect.com/science/article/abs/pii/S0140366424002214?via%3Dihub)
+- [Tianyang Zhang, et al. Privacy Protection in WiFi Sensing via CSI Fuzzing, 2024 IEEE/ACM Symposium on Edge Computing (SEC), 04-07 December 2024](https://ieeexplore.ieee.org/abstract/document/10818006)
+- [Xianjun Jiao, et al. Single-Input-Multiple-Output Wi-Fi Radar for Vital Signal Sensing and Device Tracking, IEEE 5th International Symposium on Joint Communications & Sensing (JC&S) 2025](https://biblio.ugent.be/publication/01JMVPSR8AR08RRW9MC15FPF58)
+- [Renato Lo Cigno, et al. Communication and Sensing: Wireless PHY-Layer Threats to Security and Privacy for IoT Systems and Possible Countermeasures. information, MDPI, 2025](https://www.mdpi.com/2078-2489/16/1/31)
+- [Zhiming Chu, et al. Defeating CSI obfuscation mechanisms: A study on unauthorized Wi-Fi Sensing in wireless sensor network. Computer Networks, Volume 263, May 2025](https://www.sciencedirect.com/science/article/abs/pii/S1389128625001768)
+
+## WiFi and Cellular 5G 6G
+- [Luca Baldesi, et al. ChARM: NextG Spectrum Sharing Through Data-Driven Real-Time O-RAN Dynamic Control. INFOCOM 2022](https://ece.northeastern.edu/wineslab/papers/BaldesiInfocom22.pdf)
+- [Christian Arendt, et al. Empowering the Convergence of Wi-Fi and 5G for Future Private 6G Networks. Accepted by European Wireless 2023; 28th European Wireless Conference 2023](https://cni.etit.tu-dortmund.de/storages/cni-etit/r/Research/Publications/2023/Arendt_2023_EW/2023_openwifi_ew_cr.pdf)
+- [Liangdong Wei, et al. An Experimental Evaluation of ACK-based Passive Bandwidth Estimation Methods in Ad Hoc Networks, 9th International Conference on Computer and Communications (ICCC) 2023](https://ieeexplore.ieee.org/document/10507541)
 
 **Openwifi was born in ORCA project (EU's Horizon2020 programme under agreement number 732174).**

doc/videos.md

@@ -5,7 +5,11 @@
 - FOSDEM2021 presentation [[Flash back](https://twitter.com/jxjputaoshu/status/1358462741703491584?s=20)], [[link for CHN user](https://www.zhihu.com/zvideo/1340748826311974912)]; [[Presentation](https://video.fosdem.org/2021/D.radio/fsr_openwifi_opensource_wifi_chip.webm)], [[link for CHN user](https://www.zhihu.com/zvideo/1345036055104360448)]
 - FSF Libreplanet 2021 presentation [[Official](https://media.libreplanet.org/u/libreplanet/m/openwifi-project-the-dawn-of-the-free-libre-wifi-chip/)], [[LinuxReviews](https://linuxreviews.org/Openwifi_project:_The_dawn_of_the_free/libre_WiFi_chip)], [[link for CHN user](https://www.zhihu.com/zvideo/1373649688906883072)]
 - Openwifi industrial real-time high reliable low latency applications (EU Horizon 2020 SHOP4CF project) [[Youtube](https://youtu.be/p7zkkdMvPNc)], [[link for CHN user](https://www.zhihu.com/zvideo/1378413483944538113)]
-- CSI fuzzer [[Youtube](https://youtu.be/aOPYwT77Qdw)], [[link for CHN user](https://www.zhihu.com/zvideo/1378409348163506177)]
+- WiFi CSI Radar: Joint communication and sensing [[Youtube](https://youtu.be/PUwpJuHZDhg)], [[link for CHN user](https://www.bilibili.com/video/BV1a94y1W7XL/?share_source=copy_web&vd_source=587e4ed61021396d31fd3a09c077969f)]
+- CSI fuzzer [[Youtube](https://youtu.be/aOPYwT77Qdw)], [[link for CHN user](https://www.zhihu.com/zvideo/1378409348163506177)], and ACM WiSec interview [[Youtube](https://youtu.be/ZOCV78aTaQg)], [[link for CHN user](https://www.bilibili.com/video/BV1Mo4y1C76t?share_source=copy_web)]
 - NGI zero, nlnet online session on future of European open hardware [[Session](https://nlnet.nl/news/2021/20210507-NGI-Zero-workshop-open-hardware.html)], [[Original record](https://archive.org/details/ngiforum-open-hardware-workshop-ngizero)], [[Youtube](https://youtu.be/m9Tw5VuHAfk)], [[link for CHN user](https://www.zhihu.com/zvideo/1379302398096285696)]
 - High Precision Time Synchronization on Wi-Fi based Multi-Hop Network [[Youtube](https://youtu.be/m5ryRArbdC8)], [[link for CHN user](https://www.zhihu.com/zvideo/1418222775224492032)]
 - FOSDEM2022 presentation [[Presentation](https://video.fosdem.org/2022/D.radio/radio_openwifi.webm)], [[link for CHN user](https://www.bilibili.com/video/BV12b4y1j7YK?share_source=copy_web)]
+- [Find the corresponding Wi-Fi packet in wireshark after openwifi CSI/IQ capture](https://github.com/open-sdr/openwifi/discussions/344) [[Youtube](https://youtu.be/iiiINz7XTGA)], [[link for CHN user](https://www.bilibili.com/video/BV13w411Y7GX/?share_source=copy_web&vd_source=587e4ed61021396d31fd3a09c077969f)]
+- CCC GPN22 DanielAW, How a Wifi chip works internally [[link](https://media.ccc.de/v/gpn22-380-how-a-wifi-chip-works-internally)]
+- FSiC2024, An opensource Wi-Fi chip, What, Why and How? [[link](https://wiki.f-si.org/index.php?title=An_opensource_Wi-Fi_chip,_What,_Why_and_How%3F)]

driver/Makefile

@@ -1,6 +1,6 @@
 # Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be
 
-obj-m += sdr.o
+obj-m += sdr.o openofdm_rx/openofdm_rx.o openofdm_tx/openofdm_tx.o tx_intf/tx_intf.o rx_intf/rx_intf.o xpu/xpu.o
 
 all:
 	make -C $(KDIR) M=$(PWD) modules

driver/ad9361/README.md

@@ -1,6 +0,0 @@
-<!--
-Author: Xianjun Jiao
-SPDX-FileCopyrightText: 2021 UGent
-SPDX-License-Identifier: AGPL-3.0-or-later
--->
-We don't maintain our own (modified) ad9361 driver anymore! The original ad9361 driver in the Linux kernel tree can be used with some extra EXPORT_SYMBOL.

driver/ad9361/ad9361_conv.c

@@ -1,821 +0,0 @@
-/*
- * AD9361 Agile RF Transceiver
- *
- * Copyright 2013-2017 Analog Devices Inc.
- *
- * Licensed under the GPL-2.
- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/spi/spi.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/string.h>
-#include <linux/uaccess.h>
-
-#include <linux/iio/iio.h>
-#include <linux/iio/sysfs.h>
-
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-
-#include "ad9361.h"
-
-#if IS_ENABLED(CONFIG_CF_AXI_ADC)
-#include "cf_axi_adc.h"
-
-static void ad9361_set_intf_delay(struct ad9361_rf_phy *phy, bool tx,
-				  unsigned int clock_delay,
-				  unsigned int data_delay, bool clock_changed)
-{
-	if (clock_changed)
-		ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
-	ad9361_spi_write(phy->spi,
-			REG_RX_CLOCK_DATA_DELAY + (tx ? 1 : 0),
-			RX_DATA_DELAY(data_delay) |
-			DATA_CLK_DELAY(clock_delay));
-	if (clock_changed)
-		ad9361_ensm_force_state(phy, ENSM_STATE_FDD);
-}
-
-static unsigned int ad9361_num_phy_chan(struct axiadc_converter *conv)
-{
-	if (conv->chip_info->num_channels > 4)
-		return 4;
-	return conv->chip_info->num_channels;
-}
-
-static int ad9361_check_pn(struct axiadc_converter *conv, bool tx,
-			   unsigned int delay)
-{
-	struct axiadc_state *st = iio_priv(conv->indio_dev);
-	unsigned int num_chan = ad9361_num_phy_chan(conv);
-	unsigned int chan;
-
-	for (chan = 0; chan < num_chan; chan++)
-		axiadc_write(st, ADI_REG_CHAN_STATUS(chan),
-			     ADI_PN_ERR | ADI_PN_OOS);
-	mdelay(delay);
-
-	if (!tx && !(axiadc_read(st, ADI_REG_STATUS) & ADI_STATUS))
-		return 1;
-
-	for (chan = 0; chan < num_chan; chan++) {
-		if (axiadc_read(st, ADI_REG_CHAN_STATUS(chan)))
-			return 1;
-	}
-
-	return 0;
-}
-
-ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
-						   char *buf, unsigned buflen)
-{
-	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
-	struct ad9361_dig_tune_data data;
-	int i, j, len = 0;
-	int ret;
-	u8 field[16][16];
-	u8 rx;
-
-	if (!conv)
-		return -ENODEV;
-
-	ret = ad9361_get_dig_tune_data(phy, &data);
-	if (ret < 0)
-		return ret;
-
-	dev_dbg(&phy->spi->dev, "%s:\n", __func__);
-
-	rx = ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY);
-
-	/* Mute TX, we don't want to transmit the PRBS */
-	ad9361_tx_mute(phy, 1);
-
-	ad9361_ensm_mode_disable_pinctrl(phy);
-
-	ad9361_bist_loopback(phy, 0);
-	ad9361_bist_prbs(phy, BIST_INJ_RX);
-
-	for (i = 0; i < 16; i++) {
-		for (j = 0; j < 16; j++) {
-			ad9361_set_intf_delay(phy, false, i, j, j == 0);
-			field[j][i] = ad9361_check_pn(conv, false, 1);
-		}
-	}
-
-	ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
-	ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY, rx);
-	ad9361_bist_loopback(phy, data.bist_loopback_mode);
-	ad9361_write_bist_reg(phy, data.bist_config);
-
-	ad9361_ensm_mode_restore_pinctrl(phy);
-	ad9361_ensm_restore_state(phy, data.ensm_state);
-
-	ad9361_tx_mute(phy, 0);
-
-	len += snprintf(buf + len, buflen, "CLK: %lu Hz 'o' = PASS\n",
-		       clk_get_rate(phy->clks[RX_SAMPL_CLK]));
-	len += snprintf(buf + len, buflen, "DC");
-	for (i = 0; i < 16; i++)
-		len += snprintf(buf + len, buflen, "%x:", i);
-	len += snprintf(buf + len, buflen, "\n");
-
-	for (i = 0; i < 16; i++) {
-		len += snprintf(buf + len, buflen, "%x:", i);
-		for (j = 0; j < 16; j++) {
-			len += snprintf(buf + len, buflen, "%c ",
-					(field[i][j] ? '.' : 'o'));
-		}
-		len += snprintf(buf + len, buflen, "\n");
-	}
-	len += snprintf(buf + len, buflen, "\n");
-
-	return len;
-}
-EXPORT_SYMBOL(ad9361_dig_interface_timing_analysis);
-
-static ssize_t samples_pps_read(struct iio_dev *indio_dev,
-				    uintptr_t private,
-				    const struct iio_chan_spec *chan, char *buf)
-{
-	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
-	struct axiadc_state *st = iio_priv(conv->indio_dev);
-	u32 config, val, mode;
-
-	config = axiadc_read(st, ADI_REG_CONFIG);
-
-	if (!(config & ADI_PPS_RECEIVER_ENABLE))
-		return -ENODEV;
-
-	val = axiadc_read(st, ADI_REG_CLOCKS_PER_PPS_STATUS);
-	if (val & ADI_CLOCKS_PER_PPS_STAT_INVAL)
-		return -ETIMEDOUT;
-
-	mode = axiadc_read(st, ADI_REG_CNTRL);
-
-	/*
-	 * Counts DATA_CLK cycles therefore needs to be corrected
-	 * for 2rx2tx mode or for LVDS vs. CMOS mode.
-	 */
-
-	val = axiadc_read(st, ADI_REG_CLOCKS_PER_PPS);
-
-	if (!(mode & ADI_R1_MODE))
-		val /= 2;
-
-	if (!(config & ADI_CMOS_OR_LVDS_N))
-		val /= 2;
-
-	return sprintf(buf, "%u\n", val);
-}
-
-/*
- * Returns the number of samples during a 1PPS (Pulse Per Second) interval.
- */
-
-static struct iio_chan_spec_ext_info axiadc_ext_info[] = {
-	{
-		.name = "samples_pps",
-		.read = samples_pps_read,
-		.shared = IIO_SHARED_BY_TYPE,
-	},
-	{},
-};
-
-#define AIM_CHAN(_chan, _si, _bits, _sign)			\
-	{ .type = IIO_VOLTAGE,						\
-	  .indexed = 1,							\
-	  .channel = _chan,						\
-	  .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) |		\
-			BIT(IIO_CHAN_INFO_CALIBBIAS) |			\
-			BIT(IIO_CHAN_INFO_CALIBPHASE),			\
-	  .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
-	  .ext_info = axiadc_ext_info,					\
-	  .scan_index = _si,						\
-	  .scan_type = {						\
-		.sign = _sign,						\
-		.realbits = _bits,					\
-		.storagebits = 16,					\
-		.shift = 0,						\
-	  },								\
-	}
-
-#define AIM_MC_CHAN(_chan, _si, _bits, _sign)			\
-	{ .type = IIO_VOLTAGE,						\
-	  .indexed = 1,							\
-	  .channel = _chan,						\
-	  .scan_index = _si,						\
-	  .scan_type = {						\
-		.sign = _sign,						\
-		.realbits = _bits,					\
-		.storagebits = 16,					\
-		.shift = 0,						\
-	  },								\
-	}
-
-
-static const unsigned long ad9361_2x2_available_scan_masks[] = {
-	0x01, 0x02, 0x04, 0x08, 0x03, 0x0C, /* 1 & 2 chan */
-	0x10, 0x20, 0x40, 0x80, 0x30, 0xC0, /* 1 & 2 chan */
-	0x33, 0xCC, 0xC3, 0x3C, 0x0F, 0xF0, /* 4 chan */
-	0xFF,				   /* 8 chan */
-	0x00,
-};
-
-static const unsigned long ad9361_available_scan_masks[] = {
-	0x01, 0x02, 0x04, 0x08, 0x03, 0x0C, 0x0F,
-	0x00,
-};
-
-static const struct axiadc_chip_info axiadc_chip_info_tbl[] = {
-	[ID_AD9361] = {
-		.name = "AD9361",
-		.max_rate = 61440000UL,
-		.max_testmode = 0,
-		.num_channels = 4,
-		.scan_masks = ad9361_available_scan_masks,
-		.channel[0] = AIM_CHAN(0, 0, 12, 'S'),
-		.channel[1] = AIM_CHAN(1, 1, 12, 'S'),
-		.channel[2] = AIM_CHAN(2, 2, 12, 'S'),
-		.channel[3] = AIM_CHAN(3, 3, 12, 'S'),
-	},
-	[ID_AD9361_2] = { /* MCS/MIMO 2x AD9361 */
-		.name = "AD9361-2",
-		.max_rate = 61440000UL,
-		.max_testmode = 0,
-		.num_channels = 8,
-		.num_shadow_slave_channels = 4,
-		.scan_masks = ad9361_2x2_available_scan_masks,
-		.channel[0] = AIM_CHAN(0, 0, 12, 'S'),
-		.channel[1] = AIM_CHAN(1, 1, 12, 'S'),
-		.channel[2] = AIM_CHAN(2, 2, 12, 'S'),
-		.channel[3] = AIM_CHAN(3, 3, 12, 'S'),
-		.channel[4] = AIM_MC_CHAN(4, 4, 12, 'S'),
-		.channel[5] = AIM_MC_CHAN(5, 5, 12, 'S'),
-		.channel[6] = AIM_MC_CHAN(6, 6, 12, 'S'),
-		.channel[7] = AIM_MC_CHAN(7, 7, 12, 'S'),
-	},
-	[ID_AD9364] = {
-		.name = "AD9364",
-		.max_rate = 61440000UL,
-		.max_testmode = 0,
-		.num_channels = 2,
-		.channel[0] = AIM_CHAN(0, 0, 12, 'S'),
-		.channel[1] = AIM_CHAN(1, 1, 12, 'S'),
-	},
-
-};
-
-static int ad9361_read_raw(struct iio_dev *indio_dev,
-			   struct iio_chan_spec const *chan,
-			   int *val,
-			   int *val2,
-			   long m)
-{
-	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
-
-	switch (m) {
-	case IIO_CHAN_INFO_SAMP_FREQ:
-		if (!conv->clk)
-			return -ENODEV;
-
-		*val = conv->adc_clk = clk_get_rate(conv->clk);
-
-		return IIO_VAL_INT;
-
-	}
-	return -EINVAL;
-}
-
-static int ad9361_write_raw(struct iio_dev *indio_dev,
-			       struct iio_chan_spec const *chan,
-			       int val,
-			       int val2,
-			       long mask)
-{
-	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
-	unsigned long r_clk;
-	int ret;
-
-	switch (mask) {
-	case IIO_CHAN_INFO_SAMP_FREQ:
-		if (!conv->clk)
-			return -ENODEV;
-
-		if (chan->extend_name)
-			return -ENODEV;
-
-		r_clk = clk_round_rate(conv->clk, val);
-		if (r_clk < 0 || r_clk > conv->chip_info->max_rate) {
-			dev_warn(&conv->spi->dev,
-				"Error setting ADC sample rate %ld", r_clk);
-			return -EINVAL;
-		}
-
-		ret = clk_set_rate(conv->clk, r_clk);
-		if (ret < 0)
-			return ret;
-
-		return 0;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
-{
-	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
-	struct axiadc_state *st;
-	unsigned reg, addr, chan, version;
-
-	if (!conv)
-		return -ENODEV;
-
-	st = iio_priv(conv->indio_dev);
-	version = axiadc_read(st, 0x4000);
-
-	/* Still there but implemented a bit different */
-	if (ADI_AXI_PCORE_VER_MAJOR(version) > 7)
-		addr = 0x4418;
-	else
-		addr = 0x4414;
-
-	for (chan = 0; chan < conv->chip_info->num_channels; chan++) {
-		reg = axiadc_read(st, addr + (chan) * 0x40);
-
-		if (ADI_AXI_PCORE_VER_MAJOR(version) > 7) {
-			if (enable) {
-				if (reg != 0x8) {
-					conv->scratch_reg[chan] = reg;
-					reg = 0x8;
-				}
-			} else if (reg == 0x8) {
-				reg = conv->scratch_reg[chan];
-			}
-		} else {
-		/* DAC_LB_ENB If set enables loopback of receive data */
-			if (enable)
-				reg |= BIT(1);
-			else
-				reg &= ~BIT(1);
-		}
-		axiadc_write(st, addr + (chan) * 0x40, reg);
-	}
-
-	return 0;
-}
-EXPORT_SYMBOL(ad9361_hdl_loopback);
-
-static int ad9361_iodelay_set(struct axiadc_state *st, unsigned lane,
-			      unsigned val, bool tx)
-{
-	if (tx) {
-		if (ADI_AXI_PCORE_VER_MAJOR(st->pcore_version) > 8)
-			axiadc_write(st, 0x4000 + ADI_REG_DELAY(lane), val);
-		else
-			return -ENODEV;
-	} else {
-		axiadc_idelay_set(st, lane, val);
-	}
-
-	return 0;
-}
-
-static int ad9361_midscale_iodelay(struct ad9361_rf_phy *phy, bool tx)
-{
-	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
-	struct axiadc_state *st = iio_priv(conv->indio_dev);
-	int ret = 0, i;
-
-	for (i = 0; i < 7; i++)
-		ret |= ad9361_iodelay_set(st, i, 15, tx);
-
-	return 0;
-}
-
-static int ad9361_dig_tune_iodelay(struct ad9361_rf_phy *phy, bool tx)
-{
-	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
-	struct axiadc_state *st = iio_priv(conv->indio_dev);
-	int i, j;
-	u32 s0, c0;
-	u8 field[32];
-
-	for (i = 0; i < 7; i++) {
-		for (j = 0; j < 32; j++) {
-			ad9361_iodelay_set(st, i, j, tx);
-			mdelay(1);
-			field[j] = ad9361_check_pn(conv, tx, 10);
-		}
-
-		c0 = ad9361_find_opt(&field[0], 32, &s0);
-		ad9361_iodelay_set(st, i, s0 + c0 / 2, tx);
-
-		dev_info(&phy->spi->dev,
-			 "%s Lane %d, window cnt %d , start %d, IODELAY set to %d\n",
-			 tx ? "TX" :"RX",  i , c0, s0, s0 + c0 / 2);
-
-	}
-
-	return 0;
-}
-
-static void ad9361_dig_tune_verbose_print(struct ad9361_rf_phy *phy,
-					  u8 field[][16], bool tx,
-					  int sel_clk, int sel_data)
-{
-	int i, j;
-	char c;
-
-	pr_info("SAMPL CLK: %lu tuning: %s\n",
-	        clk_get_rate(phy->clks[RX_SAMPL_CLK]), tx ? "TX" : "RX");
-	pr_info("  ");
-	for (i = 0; i < 16; i++)
-		pr_cont("%x:", i);
-	pr_cont("\n");
-
-	for (i = 0; i < 2; i++) {
-		pr_info("%x:", i);
-		for (j = 0; j < 16; j++) {
-			if (field[i][j])
-			    c = '#';
-			else if ((i == 0 && j == sel_data) ||
-				 (i == 1 && j == sel_clk))
-			    c = 'O';
-			else
-			    c = 'o';
-			pr_cont("%c ", c);
-		}
-		pr_cont("\n");
-	}
-}
-
-static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy,
-				 unsigned long max_freq,
-				 enum dig_tune_flags flags, bool tx)
-{
-	// static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};
-	static const unsigned int rates[3] = {25000000U, 40000000U, 40000000U};
-	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
-	unsigned int s0, s1, c0, c1;
-	unsigned int i, j, r;
-	bool half_data_rate;
-	u8 field[2][16];
-
-	if (ad9361_uses_lvds_mode(phy) || !ad9361_uses_rx2tx2(phy))
-		half_data_rate = false;
-	else
-		half_data_rate = true;
-
-	memset(field, 0, 32);
-	for (r = 0; r < (max_freq ? ARRAY_SIZE(rates) : 1); r++) {
-		if (max_freq)
-			ad9361_set_trx_clock_chain_freq(phy,
-				half_data_rate ? rates[r] / 2 : rates[r]);
-
-		for (i = 0; i < 2; i++) {
-			for (j = 0; j < 16; j++) {
-				/*
-				 * i == 0: clock delay = 0, data delay from 0 to 15
-				 * i == 1: clock delay = 15, data delay from 15 to 0
-				 */
-				ad9361_set_intf_delay(phy, tx, i ? 15 : 0,
-						      i ? 15 - j : j, j == 0);
-				field[i][j] |= ad9361_check_pn(conv, tx, 4);
-			}
-		}
-
-		if ((flags & BE_MOREVERBOSE) && max_freq) {
-			ad9361_dig_tune_verbose_print(phy, field, tx, -1, -1);
-		}
-	}
-
-	c0 = ad9361_find_opt(&field[0][0], 16, &s0);
-	c1 = ad9361_find_opt(&field[1][0], 16, &s1);
-
-	if (!c0 && !c1) {
-		ad9361_dig_tune_verbose_print(phy, field, tx, -1, -1);
-		dev_err(&phy->spi->dev, "%s: Tuning %s FAILED!", __func__,
-			tx ? "TX" : "RX");
-		return -EIO;
-	} else if (flags & BE_VERBOSE) {
-		ad9361_dig_tune_verbose_print(phy, field, tx,
-					      c1 > c0 ? (s1 + c1 / 2) : -1,
-					      c1 > c0 ? -1 : (s0 + c0 / 2));
-	}
-
-	if (c1 > c0)
-		ad9361_set_intf_delay(phy, tx, s1 + c1 / 2, 0, true);
-	else
-		ad9361_set_intf_delay(phy, tx, 0, s0 + c0 / 2, true);
-
-	return 0;
-}
-
-static int ad9361_dig_tune_rx(struct ad9361_rf_phy *phy, unsigned long max_freq,
-			      enum dig_tune_flags flags)
-{
-	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
-	struct axiadc_state *st = iio_priv(conv->indio_dev);
-	int ret;
-
-	ad9361_bist_loopback(phy, 0);
-	ad9361_bist_prbs(phy, BIST_INJ_RX);
-
-	ret = ad9361_dig_tune_delay(phy, max_freq, flags, false);
-	if (flags & DO_IDELAY)
-		ad9361_dig_tune_iodelay(phy, false);
-
-	axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN);
-	axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
-
-	return ret;
-}
-
-static int ad9361_dig_tune_tx(struct ad9361_rf_phy *phy, unsigned long max_freq,
-			      enum dig_tune_flags flags)
-{
-	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
-	struct axiadc_state *st = iio_priv(conv->indio_dev);
-	u32 saved_dsel[4], saved_chan_ctrl6[4], saved_chan_ctrl0[4];
-	unsigned int chan, num_chan;
-	unsigned int hdl_dac_version;
-	u32 tmp, saved = 0;
-	int ret;
-
-	num_chan = ad9361_num_phy_chan(conv);
-	hdl_dac_version = axiadc_read(st, 0x4000);
-
-	ad9361_bist_prbs(phy, BIST_DISABLE);
-	ad9361_bist_loopback(phy, 1);
-	axiadc_write(st, 0x4000 + ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
-
-	for (chan = 0; chan < num_chan; chan++) {
-		saved_chan_ctrl0[chan] = axiadc_read(st, ADI_REG_CHAN_CNTRL(chan));
-		axiadc_write(st, ADI_REG_CHAN_CNTRL(chan),
-			ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |
-			ADI_ENABLE | ADI_IQCOR_ENB);
-		axiadc_set_pnsel(st, chan, ADC_PN_CUSTOM);
-		saved_chan_ctrl6[chan] = axiadc_read(st, 0x4414 + (chan) * 0x40);
-		if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) > 7) {
-			saved_dsel[chan] = axiadc_read(st, 0x4418 + (chan) * 0x40);
-			axiadc_write(st, 0x4418 + (chan) * 0x40, 9);
-			axiadc_write(st, 0x4414 + (chan) * 0x40, 0); /* !IQCOR_ENB */
-			axiadc_write(st, 0x4044, 1);
-		} else {
-			axiadc_write(st, 0x4414 + (chan) * 0x40, 1); /* DAC_PN_ENB */
-		}
-	}
-	if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) < 8) {
-		saved = tmp = axiadc_read(st, 0x4048);
-		tmp &= ~0xF;
-		tmp |= 1;
-		axiadc_write(st, 0x4048, tmp);
-	}
-
-	ret = ad9361_dig_tune_delay(phy, max_freq, flags, true);
-	if (flags & DO_ODELAY)
-		ad9361_dig_tune_iodelay(phy, true);
-
-	if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) < 8)
-		axiadc_write(st, 0x4048, saved);
-
-	for (chan = 0; chan < num_chan; chan++) {
-		axiadc_write(st, ADI_REG_CHAN_CNTRL(chan),
-			     saved_chan_ctrl0[chan]);
-		axiadc_set_pnsel(st, chan, ADC_PN9);
-		if (ADI_AXI_PCORE_VER_MAJOR(hdl_dac_version) > 7) {
-			axiadc_write(st, 0x4418 + chan * 0x40,
-				     saved_dsel[chan]);
-			axiadc_write(st, 0x4044, 1);
-		}
-
-		axiadc_write(st, 0x4414 + chan * 0x40, saved_chan_ctrl6[chan]);
-	}
-
-	return ret;
-}
-
-int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq,
-		    enum dig_tune_flags flags)
-{
-	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
-	struct ad9361_dig_tune_data data;
-	struct axiadc_state *st;
-	bool restore = false;
-	int ret = 0;
-
-	if (!conv)
-		return -ENODEV;
-
-	ret = ad9361_get_dig_tune_data(phy, &data);
-	if (ret < 0)
-		return ret;
-
-	dev_dbg(&phy->spi->dev, "%s: freq %lu flags 0x%X\n", __func__,
-		max_freq, flags);
-
-	st = iio_priv(conv->indio_dev);
-
-	if ((data.skip_mode == SKIP_ALL) ||
-	    (flags & RESTORE_DEFAULT)) {
-		/* skip completely and use defaults */
-		restore = true;
-	} else {
-		/* Mute TX, we don't want to transmit the PRBS */
-		ad9361_tx_mute(phy, 1);
-
-		ad9361_ensm_mode_disable_pinctrl(phy);
-
-		if (flags & DO_IDELAY)
-			ad9361_midscale_iodelay(phy, false);
-
-		if (flags & DO_ODELAY)
-			ad9361_midscale_iodelay(phy, true);
-
-		ret = ad9361_dig_tune_rx(phy, max_freq, flags);
-		if (ret == 0 && (data.skip_mode == TUNE_RX_TX))
-			ret = ad9361_dig_tune_tx(phy, max_freq, flags);
-
-		ad9361_bist_loopback(phy, data.bist_loopback_mode);
-		ad9361_write_bist_reg(phy, data.bist_config);
-
-		if (ret == -EIO)
-			restore = true;
-		if (!max_freq)
-			ret = 0;
-	}
-
-	if (restore) {
-		ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
-		ad9361_write_clock_data_delays(phy);
-	} else if (!(flags & SKIP_STORE_RESULT)) {
-		ad9361_read_clock_data_delays(phy);
-	}
-
-	ad9361_ensm_mode_restore_pinctrl(phy);
-	ad9361_ensm_restore_state(phy, data.ensm_state);
-
-	axiadc_write(st, ADI_REG_RSTN, ADI_MMCM_RSTN);
-	axiadc_write(st, ADI_REG_RSTN, ADI_RSTN | ADI_MMCM_RSTN);
-
-	ad9361_tx_mute(phy, 0);
-
-	return ret;
-}
-EXPORT_SYMBOL(ad9361_dig_tune);
-
-static int ad9361_post_setup(struct iio_dev *indio_dev)
-{
-	struct axiadc_state *st = iio_priv(indio_dev);
-	struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev);
-	struct ad9361_rf_phy *phy = conv->phy;
-	bool rx2tx2 = ad9361_uses_rx2tx2(phy);
-	unsigned tmp, num_chan, flags;
-	int i, ret;
-
-	num_chan = ad9361_num_phy_chan(conv);
-
-	conv->indio_dev = indio_dev;
-	axiadc_write(st, ADI_REG_CNTRL, rx2tx2 ? 0 : ADI_R1_MODE);
-	tmp = axiadc_read(st, 0x4048);
-
-	if (!rx2tx2) {
-		axiadc_write(st, 0x4048, tmp | BIT(5)); /* R1_MODE */
-		axiadc_write(st, 0x404c,
-			     ad9361_uses_lvds_mode(phy) ? 1 : 0); /* RATE */
-	} else {
-		tmp &= ~BIT(5);
-		axiadc_write(st, 0x4048, tmp);
-		axiadc_write(st, 0x404c,
-			     ad9361_uses_lvds_mode(phy) ? 3 : 1); /* RATE */
-	}
-
-	for (i = 0; i < num_chan; i++) {
-		axiadc_write(st, ADI_REG_CHAN_CNTRL_1(i),
-			     ADI_DCFILT_OFFSET(0));
-		axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i),
-			     (i & 1) ? 0x00004000 : 0x40000000);
-		axiadc_write(st, ADI_REG_CHAN_CNTRL(i),
-			     ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |
-			     ADI_ENABLE | ADI_IQCOR_ENB);
-	}
-
-	flags = 0;
-
-	ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_AXI_REG_ID)) ?
-		0 : 61440000, flags);
-	if (ret < 0)
-		goto error;
-
-	if (flags & (DO_IDELAY | DO_ODELAY)) {
-		ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_AXI_REG_ID)) ?
-			0 : 61440000, flags & BE_VERBOSE);
-		if (ret < 0)
-			goto error;
-	}
-
-	ret = ad9361_set_trx_clock_chain_default(phy);
-
-	ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
-	ad9361_ensm_restore_prev_state(phy);
-
-	return 0;
-
-error:
-	spi_set_drvdata(phy->spi, NULL);
-	return ret;
-}
-
-int ad9361_register_axi_converter(struct ad9361_rf_phy *phy)
-{
-	struct axiadc_converter *conv;
-	struct spi_device *spi = phy->spi;
-	int ret;
-
-	conv = devm_kzalloc(&spi->dev, sizeof(*conv), GFP_KERNEL);
-	if (conv == NULL)
-		return -ENOMEM;
-
-	conv->id = ad9361_spi_read(spi, REG_PRODUCT_ID) & PRODUCT_ID_MASK;
-	if (conv->id != PRODUCT_ID_9361) {
-		dev_err(&spi->dev, "Unrecognized CHIP_ID 0x%X\n", conv->id);
-  		ret = -ENODEV;
-  		goto out;
-	}
-
-	conv->chip_info = &axiadc_chip_info_tbl[
-		(spi_get_device_id(spi)->driver_data == ID_AD9361_2) ?
-		ID_AD9361_2 : ad9361_uses_rx2tx2(phy) ? ID_AD9361 : ID_AD9364];
-	conv->write_raw = ad9361_write_raw;
-	conv->read_raw = ad9361_read_raw;
-	conv->post_setup = ad9361_post_setup;
-	conv->spi = spi;
-	conv->phy = phy;
-
-	conv->clk = phy->clks[RX_SAMPL_CLK];
-	conv->adc_clk = clk_get_rate(conv->clk);
-
-	spi_set_drvdata(spi, conv); /* Take care here */
-
-	return 0;
-out:
-	spi_set_drvdata(spi, NULL);
-	return ret;
-}
-EXPORT_SYMBOL(ad9361_register_axi_converter);
-
-struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi)
-{
-	struct axiadc_converter *conv = spi_get_drvdata(spi);
-	return conv->phy;
-}
-EXPORT_SYMBOL(ad9361_spi_to_phy);
-
-#else  /* CONFIG_CF_AXI_ADC */
-
-int ad9361_dig_tune(struct ad9361_rf_phy *phy, unsigned long max_freq,
-			   enum dig_tune_flags flags)
-{
-	return -ENODEV;
-}
-EXPORT_SYMBOL(ad9361_dig_tune);
-
-ssize_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
-						   char *buf, unsigned buflen)
-{
-	return 0;
-}
-EXPORT_SYMBOL(ad9361_dig_interface_timing_analysis);
-
-int ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
-{
-	return -ENODEV;
-}
-EXPORT_SYMBOL(ad9361_hdl_loopback);
-
-int ad9361_register_axi_converter(struct ad9361_rf_phy *phy)
-{
-	struct spi_device *spi = phy->spi;
-	spi_set_drvdata(spi, phy); /* Take care here */
-
-	return 0;
-}
-EXPORT_SYMBOL(ad9361_register_axi_converter);
-
-struct ad9361_rf_phy* ad9361_spi_to_phy(struct spi_device *spi)
-{
-	return spi_get_drvdata(spi);
-}
-EXPORT_SYMBOL(ad9361_spi_to_phy);
-
-#endif /* CONFIG_CF_AXI_ADC */

driver/hw_def.h

@@ -205,6 +205,7 @@ const char *openofdm_rx_compatible_str = "sdr,openofdm_rx";
 #define OPENOFDM_RX_REG_POWER_THRES_ADDR   (2*4)
 #define OPENOFDM_RX_REG_MIN_PLATEAU_ADDR   (3*4)
 #define OPENOFDM_RX_REG_SOFT_DECODING_ADDR (4*4)
+#define OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR (5*4)
 #define OPENOFDM_RX_REG_STATE_HISTORY_ADDR (20*4)
 
 enum openofdm_rx_mode {
@@ -236,11 +237,16 @@ enum openofdm_rx_mode {
 // 11a/g BPSK 6m, Rx sensitivity level dmesg report -86dBm
 // priv->rssi_correction = 148; rssi_half_db/2 = 148-86=62; rssi_half_db = 124
 
-#define OPENOFDM_RX_RSSI_DBM_TH_DEFAULT (-84)
+#define OPENOFDM_RX_RSSI_DBM_TH_DEFAULT (-85) //-85 will remove lots of false alarm. the best openwifi reported sensitivity is like -90/-92 (set it manually if conductive test with wifi tester)
 #define OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT 64
 #define OPENOFDM_RX_MIN_PLATEAU_INIT 100
+#define OPENOFDM_RX_FFT_WIN_SHIFT_INIT 1
+#define OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH 48
 
-#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf
+#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer  than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf
+
+#define OPENWIFI_MIN_SIGNAL_LEN_TH 14   //Packet shorter than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf
+                                        //due to CRC32, at least 4 bytes needed to push out expected CRC result
 
 struct openofdm_rx_driver_api {
 	u32 (*hw_init)(enum openofdm_rx_mode mode);
@@ -255,6 +261,7 @@ struct openofdm_rx_driver_api {
 	void (*OPENOFDM_RX_REG_POWER_THRES_write)(u32 value);
 	void (*OPENOFDM_RX_REG_MIN_PLATEAU_write)(u32 value);
 	void (*OPENOFDM_RX_REG_SOFT_DECODING_write)(u32 value);
+	void (*OPENOFDM_RX_REG_FFT_WIN_SHIFT_write)(u32 value);
 };
 
 // ---------------------------------------openofdm tx-------------------------------
@@ -310,9 +317,9 @@ const char *xpu_compatible_str = "sdr,xpu";
 #define XPU_REG_SEND_ACK_WAIT_TOP_ADDR    		(18*4)
 #define XPU_REG_CSMA_CFG_ADDR             		(19*4)
 
-#define XPU_REG_SLICE_COUNT_TOTAL_ADDR   (20*4)
-#define XPU_REG_SLICE_COUNT_START_ADDR   (21*4)
-#define XPU_REG_SLICE_COUNT_END_ADDR     (22*4)
+#define XPU_REG_SLICE_COUNT_TOTAL_ADDR    (20*4)
+#define XPU_REG_SLICE_COUNT_START_ADDR    (21*4)
+#define XPU_REG_SLICE_COUNT_END_ADDR      (22*4)
 
 #define XPU_REG_CTS_TO_RTS_CONFIG_ADDR    (26*4)
 #define XPU_REG_FILTER_FLAG_ADDR          (27*4)
@@ -321,26 +328,11 @@ const char *xpu_compatible_str = "sdr,xpu";
 #define XPU_REG_MAC_ADDR_LOW_ADDR         (30*4)
 #define XPU_REG_MAC_ADDR_HIGH_ADDR        (31*4)
 
-#define XPU_REG_FC_DI_ADDR                (34*4)
-#define XPU_REG_ADDR1_LOW_ADDR            (35*4)
-#define XPU_REG_ADDR1_HIGH_ADDR           (36*4)
-#define XPU_REG_ADDR2_LOW_ADDR            (37*4)
-#define XPU_REG_ADDR2_HIGH_ADDR           (38*4)
-#define XPU_REG_ADDR3_LOW_ADDR            (39*4)
-#define XPU_REG_ADDR3_HIGH_ADDR           (40*4)
-
-#define XPU_REG_SC_LOW_ADDR               (41*4)
-#define XPU_REG_ADDR4_HIGH_ADDR           (42*4)
-#define XPU_REG_ADDR4_LOW_ADDR            (43*4)
-
-#define XPU_REG_TRX_STATUS_ADDR           (50*4)
-#define XPU_REG_TX_RESULT_ADDR            (51*4)
-
 #define XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR  (58*4)
 #define XPU_REG_TSF_RUNTIME_VAL_HIGH_ADDR (59*4)
 
-#define XPU_REG_RSSI_HALF_DB_ADDR         (60*4)
-#define XPU_REG_IQ_RSSI_HALF_DB_ADDR      (61*4)
+#define XPU_REG_MAC_ADDR_READ_BACK_ADDR   (62*4)
+#define XPU_REG_FPGA_GIT_REV_ADDR         (63*4)
 
 enum xpu_mode {
 	XPU_TEST = 0,

driver/make_all.sh

@@ -4,8 +4,15 @@
 # SPDX-FileCopyrightText: 2019 UGent
 # SPDX-License-Identifier: AGPL-3.0-or-later
 
-if [ "$#" -ne 2 ]; then
-    echo "You must enter exactly 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)"
+print_usage () {
+    echo "You must enter at least 2 arguments: \$XILINX_DIR ARCH_BIT(32 or 64)"
+    echo "Further arguments (maximum 5) will be converted to #define argument in pre_def.h"
+    echo " "
+}
+
+print_usage
+
+if [ "$#" -lt 2 ]; then
     exit 1
 fi
 
@@ -13,6 +20,10 @@ OPENWIFI_DIR=$(pwd)/../
 XILINX_DIR=$1
 ARCH_OPTION=$2
 
+echo OPENWIFI_DIR $OPENWIFI_DIR
+echo XILINX_DIR $XILINX_DIR
+echo ARCH_OPTION $ARCH_OPTION
+
 if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
     echo "\$OPENWIFI_DIR is found!"
 else
@@ -20,7 +31,7 @@ else
     exit 1
 fi
 
-if [ -d "$XILINX_DIR/SDK" ]; then
+if [ -d "$XILINX_DIR/Vitis" ]; then
     echo "\$XILINX_DIR is found!"
 else
     echo "\$XILINX_DIR is not correct. Please check!"
@@ -34,22 +45,47 @@ else
     echo "\$ARCH_OPTION is valid!"
 fi
 
-source $XILINX_DIR/SDK/2018.3/settings64.sh
+echo "#define USE_NEW_RX_INTERRUPT 1" > pre_def.h
+if [[ -n $3 ]]; then
+    DEFINE1=$3
+    echo DEFINE1 $DEFINE1
+    echo "#define $DEFINE1" >> pre_def.h
+fi
+if [[ -n $4 ]]; then
+    DEFINE2=$4
+    echo DEFINE2 $DEFINE2
+    echo "#define $DEFINE2" >> pre_def.h
+fi
+if [[ -n $5 ]]; then
+    DEFINE3=$5
+    echo DEFINE3 $DEFINE3
+    echo "#define $DEFINE3" >> pre_def.h
+fi
+if [[ -n $6 ]]; then
+    DEFINE4=$6
+    echo DEFINE4 $DEFINE4
+    echo "#define $DEFINE4" >> pre_def.h
+fi
+if [[ -n $7 ]]; then
+    DEFINE5=$7
+    echo DEFINE5 $DEFINE5
+    echo "#define $DEFINE5" >> pre_def.h
+fi
+
+source $XILINX_DIR/Vitis/2021.1/settings64.sh
 if [ "$ARCH_OPTION" == "64" ]; then
     LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/
     ARCH="arm64"
     CROSS_COMPILE="aarch64-linux-gnu-"
-    echo "#define USE_NEW_RX_INTERRUPT 1" > pre_def.h
 else
     LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux/
     ARCH="arm"
     CROSS_COMPILE="arm-linux-gnueabihf-"
-    echo "#define USE_NEW_RX_INTERRUPT 1" > pre_def.h
 fi
 
 # check if user entered the right path to analog device linux
 if [ -d "$LINUX_KERNEL_SRC_DIR" ]; then
-    echo " setup linux kernel path ${LINUX_KERNEL_SRC_DIR}"
+    echo "setup linux kernel path ${LINUX_KERNEL_SRC_DIR}"
 else
     echo "Error: path to adi linux: ${LINUX_KERNEL_SRC_DIR} not found. Can not continue."
     exit 1
@@ -65,7 +101,6 @@ if git log -1; then
 else
     echo "#define GIT_REV 0xFFFFFFFF" > git_rev.h
 fi
-make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 cd $OPENWIFI_DIR/driver/openofdm_tx
 make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 cd $OPENWIFI_DIR/driver/openofdm_rx
@@ -79,4 +114,10 @@ make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 # cd $OPENWIFI_DIR/driver/ad9361
 # make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
 
+cd $OPENWIFI_DIR/driver/side_ch
+./make_driver.sh $XILINX_DIR $ARCH_OPTION
+
+cd $OPENWIFI_DIR/driver/
+make KDIR=$LINUX_KERNEL_SRC_DIR ARCH=$ARCH CROSS_COMPILE=$CROSS_COMPILE
+
 cd $home_dir

driver/openofdm_rx/openofdm_rx.c

@@ -55,6 +55,9 @@ static inline void OPENOFDM_RX_REG_MIN_PLATEAU_write(u32 Data) {
 static inline void OPENOFDM_RX_REG_SOFT_DECODING_write(u32 Data) {
 	reg_write(OPENOFDM_RX_REG_SOFT_DECODING_ADDR, Data);
 }
+static inline void OPENOFDM_RX_REG_FFT_WIN_SHIFT_write(u32 Data) {
+	reg_write(OPENOFDM_RX_REG_FFT_WIN_SHIFT_ADDR, Data);
+}
 static const struct of_device_id dev_of_ids[] = {
 	{ .compatible = "sdr,openofdm_rx", },
 	{}
@@ -62,7 +65,7 @@ static const struct of_device_id dev_of_ids[] = {
 MODULE_DEVICE_TABLE(of, dev_of_ids);
 
 static struct openofdm_rx_driver_api openofdm_rx_driver_api_inst;
-static struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst;
+struct openofdm_rx_driver_api *openofdm_rx_api = &openofdm_rx_driver_api_inst;
 EXPORT_SYMBOL(openofdm_rx_api);
 
 static inline u32 hw_init(enum openofdm_rx_mode mode){
@@ -93,7 +96,8 @@ static inline u32 hw_init(enum openofdm_rx_mode mode){
 	// 1) power threshold configuration and reset
 	openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default
 	openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT);
-	openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|1); //bit1 enable soft decoding; bit31~16 max pkt length threshold
+	openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|(OPENWIFI_MIN_SIGNAL_LEN_TH<<12)|1); //bit1 enable soft decoding; bit15~12 min pkt length threshold; bit31~16 max pkt length threshold
+	openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write((OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH<<4)|OPENOFDM_RX_FFT_WIN_SHIFT_INIT);
 
 	//rst
 	for (i=0;i<8;i++)
@@ -139,6 +143,7 @@ static int dev_probe(struct platform_device *pdev)
 	openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write=OPENOFDM_RX_REG_POWER_THRES_write;
 	openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write=OPENOFDM_RX_REG_MIN_PLATEAU_write;
 	openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write=OPENOFDM_RX_REG_SOFT_DECODING_write;
+	openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write=OPENOFDM_RX_REG_FFT_WIN_SHIFT_write;
 
 	/* Request and map I/O memory */
 	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);

driver/openofdm_tx/openofdm_tx.c

@@ -56,7 +56,7 @@ static const struct of_device_id dev_of_ids[] = {
 MODULE_DEVICE_TABLE(of, dev_of_ids);
 
 static struct openofdm_tx_driver_api openofdm_tx_driver_api_inst;
-static struct openofdm_tx_driver_api *openofdm_tx_api = &openofdm_tx_driver_api_inst;
+struct openofdm_tx_driver_api *openofdm_tx_api = &openofdm_tx_driver_api_inst;
 EXPORT_SYMBOL(openofdm_tx_api);
 
 static inline u32 hw_init(enum openofdm_tx_mode mode){

driver/rx_intf/rx_intf.c

@@ -165,7 +165,7 @@ static const struct of_device_id dev_of_ids[] = {
 MODULE_DEVICE_TABLE(of, dev_of_ids);
 
 static struct rx_intf_driver_api rx_intf_driver_api_inst;
-static struct rx_intf_driver_api *rx_intf_api = &rx_intf_driver_api_inst;
+struct rx_intf_driver_api *rx_intf_api = &rx_intf_driver_api_inst;
 EXPORT_SYMBOL(rx_intf_api);
 
 static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32 num_dma_symbol_to_ps){
@@ -292,10 +292,6 @@ static inline u32 hw_init(enum rx_intf_mode mode, u32 num_dma_symbol_to_pl, u32
 		//0x000-normal; 0x100-sig and fcs valid are controlled by bit4 and bit0;
 		//0x111-sig and fcs high; 0x110-sig high fcs low; 0x101-sig low fcs high; 0x100-sig and fcs low
 
-		rx_intf_api->RX_INTF_REG_IQ_SRC_SEL_write(0);
-		// 0-bw20-ch0; 1-bw2-ch0;  2-bw2-ch2;  3-bw2-ch4;  4-bw2-ch6;  5-s_axis-ch0
-		// 8-bw20-ch1; 9-bw2-ch1; 10-bw2-ch3; 11-bw2-ch5; 12-bw2-ch7; 13-s_axis-ch1
-
 		rx_intf_api->RX_INTF_REG_S2MM_INTR_DELAY_COUNT_write(30*10); // delayed interrupt, counter clock 10MHz is assumed
 		
 		rx_intf_api->RX_INTF_REG_IQ_CTRL_write(0);

driver/sdr.c

@@ -44,6 +44,8 @@
 #include <linux/gpio.h>
 #include <linux/leds.h>
 
+// #include <linux/time.h>
+
 #define IIO_AD9361_USE_PRIVATE_H_
 #include <../../drivers/iio/adc/ad9361_regs.h>
 #include <../../drivers/iio/adc/ad9361.h>
@@ -110,7 +112,8 @@ static bool openwifi_is_radio_enabled(struct openwifi_priv *priv)
 	else
 		reg = ad9361_get_tx_atten(priv->ad9361_phy, 2);
 
-	if (reg == (AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]))
+	// if (reg == (AD9361_RADIO_ON_TX_ATT+priv->rf_reg_val[RF_TX_REG_IDX_ATT]))
+  if (reg < AD9361_RADIO_OFF_TX_ATT)
 		return true;// 0 off, 1 on
 	return false;
 }
@@ -164,9 +167,9 @@ inline int rssi_correction_lookup_table(u32 freq_MHz)
 	} else if (freq_MHz<=5240) {
 		rssi_correction = 145;
 	} else if (freq_MHz<=5320) {
-		rssi_correction = 148;
+		rssi_correction = 145;
 	} else {
-		rssi_correction = 148;
+		rssi_correction = 145;
 	}
 
 	return rssi_correction;
@@ -174,22 +177,23 @@ inline int rssi_correction_lookup_table(u32 freq_MHz)
 
 inline void ad9361_tx_calibration(struct openwifi_priv *priv, u32 actual_tx_lo)
 {
-	struct timeval tv;
-	unsigned long time_before = 0; 
-	unsigned long time_after = 0;
+	// struct timespec64 tv;
+	// unsigned long time_before = 0; 
+	// unsigned long time_after = 0;
 	u32 spi_disable; 
 
 	priv->last_tx_quad_cal_lo = actual_tx_lo; 
-	do_gettimeofday(&tv);
-	time_before = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec );
+	// do_gettimeofday(&tv);
+	// time_before = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec );
 	spi_disable = xpu_api->XPU_REG_SPI_DISABLE_read(); // backup current fpga spi disable state
 	xpu_api->XPU_REG_SPI_DISABLE_write(1); // disable FPGA SPI module
 	ad9361_do_calib_run(priv->ad9361_phy, TX_QUAD_CAL, (int)priv->ad9361_phy->state->last_tx_quad_cal_phase); 
 	xpu_api->XPU_REG_SPI_DISABLE_write(spi_disable); // restore original SPI disable state 
-	do_gettimeofday(&tv);
-	time_after = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec );
+	// do_gettimeofday(&tv);
+	// time_after = tv.tv_usec + ((u64)1000000ull)*((u64)tv.tv_sec );
 
-	printk("%s ad9361_tx_calibration %dMHz tx_quad_cal duration %lu us\n", sdr_compatible_str, actual_tx_lo, time_after-time_before);
+	// printk("%s ad9361_tx_calibration %dMHz tx_quad_cal duration %lu us\n", sdr_compatible_str, actual_tx_lo, time_after-time_before);
+	printk("%s ad9361_tx_calibration %dMHz tx_quad_cal duration unknown us\n", sdr_compatible_str, actual_tx_lo);
 }
 
 inline void openwifi_rf_rx_update_after_tuning(struct openwifi_priv *priv, u32 actual_rx_lo)
@@ -200,10 +204,7 @@ inline void openwifi_rf_rx_update_after_tuning(struct openwifi_priv *priv, u32 a
 	priv->rssi_correction = rssi_correction_lookup_table(actual_rx_lo);
 
 	// set appropriate lbt threshold
-	// xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62)<<1); // -62dBm
-	// xpu_api->XPU_REG_LBT_TH_write((priv->rssi_correction-62-16)<<1); // wei's magic value is 135, here is 134 @ ch 44
-	// auto_lbt_th = ((priv->rssi_correction-62-16)<<1);
-	auto_lbt_th = rssi_dbm_to_rssi_half_db(-78, priv->rssi_correction); // -78dBm, the same as above ((priv->rssi_correction-62-16)<<1)
+	auto_lbt_th = rssi_dbm_to_rssi_half_db(-62, priv->rssi_correction); // -62dBm
 	static_lbt_th = rssi_dbm_to_rssi_half_db(-(priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_LBT_TH]), priv->rssi_correction);
 	fpga_lbt_th = (priv->drv_xpu_reg_val[DRV_XPU_REG_IDX_LBT_TH]==0?auto_lbt_th:static_lbt_th);
 	xpu_api->XPU_REG_LBT_TH_write(fpga_lbt_th);
@@ -692,7 +693,7 @@ static irqreturn_t openwifi_tx_interrupt(int irq, void *dev_id)
 				seq_no = ring->bds[ring->bd_rd_idx].seq_no;
 
 				if (seq_no == 0xffff) {// it has been forced cleared by the openwifi_tx (due to out-of-order Tx of different queues to the air?)
-					printk("%s openwifi_tx_interrupt: WARNING wr%d rd%d last_bd_rd_idx%d i%d pkt_cnt%d prio%d fpga q%d hwq len%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%llu\n", sdr_compatible_str,
+					printk("%s openwifi_tx_interrupt: WARNING wr%d rd%d last_bd_rd_idx%d i%d pkt_cnt%d prio%d fpga q%d hwq len%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%u\n", sdr_compatible_str,
 					ring->bd_wr_idx, ring->bd_rd_idx, last_bd_rd_idx, i, pkt_cnt, prio, queue_idx, hw_queue_len, ring->bds[ring->bd_rd_idx].prio, ring->bds[ring->bd_rd_idx].len_mpdu, seq_no, ring->bds[ring->bd_rd_idx].skb_linked, ring->bds[ring->bd_rd_idx].dma_mapping_addr);
 					continue;
 				}
@@ -1011,7 +1012,7 @@ static void openwifi_tx(struct ieee80211_hw *dev,
 			}
 			for (i=0; i<empty_bd_idx; i++) {
 				j = ( (ring->bd_wr_idx+i)&(NUM_TX_BD-1) );
-				printk("%s openwifi_tx: WARNING fake stop queue empty_bd_idx%d i%d lnx prio%d map to q%d stop%d hwq len%d wr%d rd%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%llu\n", sdr_compatible_str,
+				printk("%s openwifi_tx: WARNING fake stop queue empty_bd_idx%d i%d lnx prio%d map to q%d stop%d hwq len%d wr%d rd%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%u\n", sdr_compatible_str,
 				empty_bd_idx, i, prio, drv_ring_idx, ring->stop_flag, hw_queue_len, ring->bd_wr_idx, ring->bd_rd_idx, ring->bds[j].prio, ring->bds[j].len_mpdu, ring->bds[j].seq_no, ring->bds[j].skb_linked, ring->bds[j].dma_mapping_addr);
 				// tell Linux this skb failed
 				skb_new = ring->bds[j].skb_linked;
@@ -1037,7 +1038,7 @@ static void openwifi_tx(struct ieee80211_hw *dev,
 			}
 		} else {
 			j = ring->bd_wr_idx;
-			printk("%s openwifi_tx: WARNING real stop queue lnx prio%d map to q%d stop%d hwq len%d wr%d rd%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%llu\n", sdr_compatible_str,
+			printk("%s openwifi_tx: WARNING real stop queue lnx prio%d map to q%d stop%d hwq len%d wr%d rd%d bd prio%d len_mpdu%d seq_no%d skb_linked%p dma_mapping_addr%u\n", sdr_compatible_str,
 			prio, drv_ring_idx, ring->stop_flag, hw_queue_len, ring->bd_wr_idx, ring->bd_rd_idx, ring->bds[j].prio, ring->bds[j].len_mpdu, ring->bds[j].seq_no, ring->bds[j].skb_linked, ring->bds[j].dma_mapping_addr);
 	
 			ieee80211_stop_queue(dev, prio); // here we should stop those prio related to the queue idx flag set in TX_INTF_REG_S_AXIS_FIFO_NO_ROOM_read
@@ -1097,7 +1098,8 @@ static void openwifi_tx(struct ieee80211_hw *dev,
 	if (use_ht_aggr && rate_hw_value==0)
 		rate_hw_value = 1;
 
-	sifs = (priv->actual_rx_lo<2500?10:16);
+	// sifs = (priv->actual_rx_lo<2500?10:16);
+	sifs = 16; // for ofdm, sifs is always 16
 
 	if (use_ht_rate) {
 		// printk("%s openwifi_tx: rate_hw_value %d aggr %d sifs %d\n", sdr_compatible_str, rate_hw_value, use_ht_aggr, sifs);
@@ -1569,18 +1571,24 @@ static int openwifi_start(struct ieee80211_hw *dev)
 	rx_intf_api->RX_INTF_REG_INTERRUPT_TEST_write(0x100); // disable rx interrupt by interrupt test mode
 	rx_intf_api->RX_INTF_REG_M_AXIS_RST_write(1); // hold M AXIS in reset status
 
-	priv->rx_chan = dma_request_slave_channel(&(priv->pdev->dev), "rx_dma_s2mm");
+	// priv->rx_chan = dma_request_slave_channel(&(priv->pdev->dev), "rx_dma_s2mm");
+	priv->rx_chan = dma_request_chan(&(priv->pdev->dev), "rx_dma_s2mm");
 	if (IS_ERR(priv->rx_chan) || priv->rx_chan==NULL) {
 		ret = PTR_ERR(priv->rx_chan);
-		pr_err("%s openwifi_start: No Rx channel ret %d priv->rx_chan 0x%p\n",sdr_compatible_str, ret, priv->rx_chan);
-		goto err_dma;
+		if (ret != -EPROBE_DEFER) {
+			pr_err("%s openwifi_start: No Rx channel ret %d priv->rx_chan 0x%p\n",sdr_compatible_str, ret, priv->rx_chan);
+			goto err_dma;
+		}
 	}
 
-	priv->tx_chan = dma_request_slave_channel(&(priv->pdev->dev), "tx_dma_mm2s");
+	// priv->tx_chan = dma_request_slave_channel(&(priv->pdev->dev), "tx_dma_mm2s");
+	priv->tx_chan = dma_request_chan(&(priv->pdev->dev), "tx_dma_mm2s");
 	if (IS_ERR(priv->tx_chan) || priv->tx_chan==NULL) {
 		ret = PTR_ERR(priv->tx_chan);
-		pr_err("%s openwifi_start: No Tx channel ret %d priv->tx_chan 0x%p\n",sdr_compatible_str, ret, priv->tx_chan);
-		goto err_dma;
+		if (ret != -EPROBE_DEFER) {
+			pr_err("%s openwifi_start: No Tx channel ret %d priv->tx_chan 0x%p\n",sdr_compatible_str, ret, priv->tx_chan);
+			goto err_dma;
+		}
 	}
 	printk("%s openwifi_start: DMA channel setup successfully. priv->rx_chan 0x%p priv->tx_chan 0x%p\n",sdr_compatible_str, priv->rx_chan, priv->tx_chan);
 
@@ -2085,16 +2093,16 @@ static const struct of_device_id openwifi_dev_of_ids[] = {
 };
 MODULE_DEVICE_TABLE(of, openwifi_dev_of_ids);
 
-static int custom_match_spi_dev(struct device *dev, void *data)
+static int custom_match_spi_dev(struct device *dev, const void *data)
 {
-    const char *name = data;
+  const char *name = data;
 
 	bool ret = sysfs_streq(name, dev->of_node->name);
 	printk("%s custom_match_spi_dev %s %s %d\n", sdr_compatible_str,name, dev->of_node->name, ret);
 	return ret;
 }
 
-static int custom_match_platform_dev(struct device *dev, void *data)
+static int custom_match_platform_dev(struct device *dev, const void *data)
 {
 	struct platform_device *plat_dev = to_platform_device(dev);
 	const char *name = data;
@@ -2440,7 +2448,6 @@ static int openwifi_dev_probe(struct platform_device *pdev)
 	 * is mapped on the highst tx ring IDX.
 	 */
 	dev->queues = MAX_NUM_HW_QUEUE;
-	//dev->queues = 1;
 
 	ieee80211_hw_set(dev, SIGNAL_DBM);
 

driver/sdr.h

@@ -120,16 +120,17 @@ enum sdrctl_reg_cat {
 #define DMESG_LOG_BROADCAST (1<<2)
 #define DMESG_LOG_NORMAL_QUEUE_STOP (1<<3)
 #define DMESG_LOG_ANY (0xF)
-
 // ------end of dmesg printk control flag------------------
 
 #define MAX_NUM_VIF 4
 
-//#define LEN_PHY_HEADER 16
 #define LEN_PHY_CRC 4
 #define LEN_MPDU_DELIM 4
 
-#define RING_ROOM_THRESHOLD 2
+#define MAX_NUM_HW_QUEUE 4 // number of queue in FPGA
+#define MAX_NUM_SW_QUEUE 4 // number of queue in Linux, depends on the number we report by dev->queues in openwifi_dev_probe
+
+#define RING_ROOM_THRESHOLD (2+MAX_NUM_SW_QUEUE) // MAX_NUM_SW_QUEUE is for the room of MAX_NUM_SW_QUEUE last packets from MAX_NUM_SW_QUEUE queue before stop
 #define NUM_BIT_NUM_TX_BD 6
 #define NUM_TX_BD (1<<NUM_BIT_NUM_TX_BD) // !!! should align to the fifo size in tx_bit_intf.v
 
@@ -143,8 +144,6 @@ enum sdrctl_reg_cat {
 #define RX_BD_BUF_SIZE (2048)
 
 #define NUM_BIT_MAX_NUM_HW_QUEUE 2
-#define MAX_NUM_HW_QUEUE 4 // number of queue in FPGA
-#define MAX_NUM_SW_QUEUE 4 // number of queue in Linux, depends on the number we report by dev->queues in openwifi_dev_probe
 #define NUM_BIT_MAX_PHY_TX_SN 10 // decrease 12 to 10 to reserve 2 bits storing related linux prio idx
 #define MAX_PHY_TX_SN ((1<<NUM_BIT_MAX_PHY_TX_SN)-1)
 
@@ -259,12 +258,12 @@ static const struct ieee80211_channel openwifi_2GHz_channels[] = {
 	CHAN2G(11, 2462, 0),
 	CHAN2G(12, 2467, 0),
 	CHAN2G(13, 2472, 0),
-	CHAN2G(14, 2484, 0),
+	// CHAN2G(14, 2484, 0),
 };
 
 static const struct ieee80211_channel openwifi_5GHz_channels[] = {
-	CHAN5G(32, 5160, 0),
-	CHAN5G(34, 5170, 0),
+	// CHAN5G(32, 5160, 0),
+	// CHAN5G(34, 5170, 0),
 	CHAN5G(36, 5180, 0),
 	CHAN5G(38, 5190, 0),
 	CHAN5G(40, 5200, 0),
@@ -272,51 +271,51 @@ static const struct ieee80211_channel openwifi_5GHz_channels[] = {
 	CHAN5G(44, 5220, 0),
 	CHAN5G(46, 5230, 0),
 	CHAN5G(48, 5240, 0),
-	CHAN5G( 50, 5250, IEEE80211_CHAN_RADAR),
+	// CHAN5G( 50, 5250, IEEE80211_CHAN_RADAR),
 	CHAN5G( 52, 5260, IEEE80211_CHAN_RADAR),
-	CHAN5G( 54, 5270, IEEE80211_CHAN_RADAR),
+	// CHAN5G( 54, 5270, IEEE80211_CHAN_RADAR),
 	CHAN5G( 56, 5280, IEEE80211_CHAN_RADAR),
-	CHAN5G( 58, 5290, IEEE80211_CHAN_RADAR),
+	// CHAN5G( 58, 5290, IEEE80211_CHAN_RADAR),
 	CHAN5G( 60, 5300, IEEE80211_CHAN_RADAR),
-	CHAN5G( 62, 5310, IEEE80211_CHAN_RADAR),
+	// CHAN5G( 62, 5310, IEEE80211_CHAN_RADAR),
 	CHAN5G( 64, 5320, IEEE80211_CHAN_RADAR),
-	CHAN5G( 68, 5340, IEEE80211_CHAN_RADAR),
-	CHAN5G( 96, 5480, IEEE80211_CHAN_RADAR),
-	CHAN5G(100, 5500, IEEE80211_CHAN_RADAR),
-	CHAN5G(102, 5510, IEEE80211_CHAN_RADAR),
-	CHAN5G(104, 5520, IEEE80211_CHAN_RADAR),
-	CHAN5G(106, 5530, IEEE80211_CHAN_RADAR),
-	CHAN5G(108, 5540, IEEE80211_CHAN_RADAR),
-	CHAN5G(110, 5550, IEEE80211_CHAN_RADAR),
-	CHAN5G(112, 5560, IEEE80211_CHAN_RADAR),
-	CHAN5G(114, 5570, IEEE80211_CHAN_RADAR),
-	CHAN5G(116, 5580, IEEE80211_CHAN_RADAR),
-	CHAN5G(118, 5590, IEEE80211_CHAN_RADAR),
-	CHAN5G(120, 5600, IEEE80211_CHAN_RADAR),
-	CHAN5G(122, 5610, IEEE80211_CHAN_RADAR),
-	CHAN5G(124, 5620, IEEE80211_CHAN_RADAR),
-	CHAN5G(126, 5630, IEEE80211_CHAN_RADAR),
-	CHAN5G(128, 5640, IEEE80211_CHAN_RADAR),
-	CHAN5G(132, 5660, IEEE80211_CHAN_RADAR),
-	CHAN5G(134, 5670, IEEE80211_CHAN_RADAR),
-	CHAN5G(136, 5680, IEEE80211_CHAN_RADAR),
-	CHAN5G(138, 5690, IEEE80211_CHAN_RADAR),
-	CHAN5G(140, 5700, IEEE80211_CHAN_RADAR),
-	CHAN5G(142, 5710, IEEE80211_CHAN_RADAR),
-	CHAN5G(144, 5720, IEEE80211_CHAN_RADAR),
-	CHAN5G(149, 5745, IEEE80211_CHAN_RADAR),
-	CHAN5G(151, 5755, IEEE80211_CHAN_RADAR),
-	CHAN5G(153, 5765, IEEE80211_CHAN_RADAR),
-	CHAN5G(155, 5775, IEEE80211_CHAN_RADAR),
-	CHAN5G(157, 5785, IEEE80211_CHAN_RADAR),
-	CHAN5G(159, 5795, IEEE80211_CHAN_RADAR),
-	CHAN5G(161, 5805, IEEE80211_CHAN_RADAR),
-	// CHAN5G(163, 5815, IEEE80211_CHAN_RADAR),
-	CHAN5G(165, 5825, IEEE80211_CHAN_RADAR),
-	CHAN5G(167, 5835, IEEE80211_CHAN_RADAR),
-	CHAN5G(169, 5845, IEEE80211_CHAN_RADAR),
-	CHAN5G(171, 5855, IEEE80211_CHAN_RADAR),
-	CHAN5G(173, 5865, IEEE80211_CHAN_RADAR),
+	// CHAN5G( 68, 5340, IEEE80211_CHAN_RADAR),
+	// CHAN5G( 96, 5480, IEEE80211_CHAN_RADAR),
+	// CHAN5G(100, 5500, IEEE80211_CHAN_RADAR),
+	// CHAN5G(102, 5510, IEEE80211_CHAN_RADAR),
+	// CHAN5G(104, 5520, IEEE80211_CHAN_RADAR),
+	// CHAN5G(106, 5530, IEEE80211_CHAN_RADAR),
+	// CHAN5G(108, 5540, IEEE80211_CHAN_RADAR),
+	// CHAN5G(110, 5550, IEEE80211_CHAN_RADAR),
+	// CHAN5G(112, 5560, IEEE80211_CHAN_RADAR),
+	// CHAN5G(114, 5570, IEEE80211_CHAN_RADAR),
+	// CHAN5G(116, 5580, IEEE80211_CHAN_RADAR),
+	// CHAN5G(118, 5590, IEEE80211_CHAN_RADAR),
+	// CHAN5G(120, 5600, IEEE80211_CHAN_RADAR),
+	// CHAN5G(122, 5610, IEEE80211_CHAN_RADAR),
+	// CHAN5G(124, 5620, IEEE80211_CHAN_RADAR),
+	// CHAN5G(126, 5630, IEEE80211_CHAN_RADAR),
+	// CHAN5G(128, 5640, IEEE80211_CHAN_RADAR),
+	// CHAN5G(132, 5660, IEEE80211_CHAN_RADAR),
+	// CHAN5G(134, 5670, IEEE80211_CHAN_RADAR),
+	// CHAN5G(136, 5680, IEEE80211_CHAN_RADAR),
+	// CHAN5G(138, 5690, IEEE80211_CHAN_RADAR),
+	// CHAN5G(140, 5700, IEEE80211_CHAN_RADAR),
+	// CHAN5G(142, 5710, IEEE80211_CHAN_RADAR),
+	// CHAN5G(144, 5720, IEEE80211_CHAN_RADAR),
+	// CHAN5G(149, 5745, IEEE80211_CHAN_RADAR),
+	// CHAN5G(151, 5755, IEEE80211_CHAN_RADAR),
+	// CHAN5G(153, 5765, IEEE80211_CHAN_RADAR),
+	// CHAN5G(155, 5775, IEEE80211_CHAN_RADAR),
+	// CHAN5G(157, 5785, IEEE80211_CHAN_RADAR),
+	// CHAN5G(159, 5795, IEEE80211_CHAN_RADAR),
+	// CHAN5G(161, 5805, IEEE80211_CHAN_RADAR),
+	// // CHAN5G(163, 5815, IEEE80211_CHAN_RADAR),
+	// CHAN5G(165, 5825, IEEE80211_CHAN_RADAR),
+	// CHAN5G(167, 5835, IEEE80211_CHAN_RADAR),
+	// CHAN5G(169, 5845, IEEE80211_CHAN_RADAR),
+	// CHAN5G(171, 5855, IEEE80211_CHAN_RADAR),
+	// CHAN5G(173, 5865, IEEE80211_CHAN_RADAR),
 };
 
 static const struct ieee80211_iface_limit openwifi_if_limits[] = {
@@ -350,30 +349,30 @@ static const u16 wifi_n_dbps_ht_table[16] =        {26, 26, 26,  26, 26, 52,  78
 
 // ===== copy from adi-linux/drivers/iio/frequency/cf_axi_dds.c =====
 struct cf_axi_dds_state {
-	struct device			*dev_spi;
-	struct clk			*clk;
+	struct device			          *dev_spi;
+	struct clk			            *clk;
 	struct cf_axi_dds_chip_info	*chip_info;
-	struct gpio_desc		*plddrbypass_gpio;
-	struct gpio_desc		*interpolation_gpio;
+  struct gpio_desc		        *plddrbypass_gpio;
+  struct gpio_desc		        *interpolation_gpio;
 
-	bool				standalone;
-	bool				dp_disable;
-	bool				enable;
-	bool				pl_dma_fifo_en;
-	enum fifo_ctrl			gpio_dma_fifo_ctrl;
+	bool				                standalone;
+	bool				                dp_disable;
+	bool				                enable;
+	bool				                pl_dma_fifo_en;
+	enum fifo_ctrl	            gpio_dma_fifo_ctrl;
 
-	struct iio_info			iio_info;
-	size_t				regs_size;
-	void __iomem			*regs;
-	void __iomem			*slave_regs;
-	void __iomem			*master_regs;
-	u64				dac_clk;
-	unsigned int			ddr_dds_interp_en;
-	unsigned int			cached_freq[16];
-	unsigned int			version;
-	unsigned int			have_slave_channels;
-	unsigned int			interpolation_factor;
-	struct notifier_block		clk_nb;
+	struct iio_info	            iio_info;
+	size_t				              regs_size;
+	void __iomem		            *regs;
+	void __iomem		            *slave_regs;
+	void __iomem		            *master_regs;
+	u64				                  dac_clk;
+	unsigned int		            ddr_dds_interp_en;
+	unsigned int		            cached_freq[16];
+	unsigned int		            version;
+	unsigned int		            have_slave_channels;
+	unsigned int		            interpolation_factor;
+	struct notifier_block		    clk_nb;
 };
 // ===== end of copy from adi-linux/drivers/iio/frequency/cf_axi_dds.c =====
 
@@ -445,16 +444,16 @@ struct openwifi_stat {
 
 #define RX_DMA_CYCLIC_MODE
 struct openwifi_priv {
-	struct platform_device *pdev;
-	struct ieee80211_vif *vif[MAX_NUM_VIF];
+	struct platform_device       *pdev;
+	struct ieee80211_vif         *vif[MAX_NUM_VIF];
 
 	const struct openwifi_rf_ops *rf;
-	enum openwifi_fpga_type fpga_type;
+	enum openwifi_fpga_type      fpga_type;
 
-	struct cf_axi_dds_state *dds_st;  //axi_ad9361 hdl ref design module, dac channel
-	struct axiadc_state *adc_st;      //axi_ad9361 hdl ref design module, adc channel
-	struct ad9361_rf_phy *ad9361_phy; //ad9361 chip
-	struct ctrl_outs_control ctrl_out;
+	struct cf_axi_dds_state      *dds_st;  //axi_ad9361 hdl ref design module, dac channel
+	struct axiadc_state          *adc_st;      //axi_ad9361 hdl ref design module, adc channel
+	struct ad9361_rf_phy         *ad9361_phy; //ad9361 chip
+	struct ctrl_outs_control     ctrl_out;
 
 	int rx_freq_offset_to_lo_MHz;
 	int tx_freq_offset_to_lo_MHz;
@@ -463,51 +462,51 @@ struct openwifi_priv {
 	u32 actual_tx_lo;
 	u32 last_tx_quad_cal_lo;
 
-	struct ieee80211_rate rates_2GHz[12];
-	struct ieee80211_rate rates_5GHz[12];
-	struct ieee80211_channel channels_2GHz[14];
-	struct ieee80211_channel channels_5GHz[53];
+	struct ieee80211_rate           rates_2GHz[12];
+	struct ieee80211_rate           rates_5GHz[12];
+	struct ieee80211_channel        channels_2GHz[13];
+	struct ieee80211_channel        channels_5GHz[11];
 	struct ieee80211_supported_band band_2GHz;
 	struct ieee80211_supported_band band_5GHz;
 	bool rfkill_off;
-	u8 runtime_tx_ant_cfg;
-	u8 runtime_rx_ant_cfg;
+	u8   runtime_tx_ant_cfg;
+	u8   runtime_rx_ant_cfg;
 
-	int rssi_correction; // dynamic RSSI correction according to current channel in _rf_set_channel()
+	int  rssi_correction; // dynamic RSSI correction according to current channel in _rf_set_channel()
 	
-	enum rx_intf_mode rx_intf_cfg;
-	enum tx_intf_mode tx_intf_cfg;
+	enum rx_intf_mode     rx_intf_cfg;
+	enum tx_intf_mode     tx_intf_cfg;
 	enum openofdm_rx_mode openofdm_rx_cfg;
 	enum openofdm_tx_mode openofdm_tx_cfg;
-	enum xpu_mode xpu_cfg;
+	enum xpu_mode         xpu_cfg;
 
 	int irq_rx;
 	int irq_tx;
 
 	// u32 call_counter;
-	u8 *rx_cyclic_buf;
-	dma_addr_t rx_cyclic_buf_dma_mapping_addr;
-	struct dma_chan *rx_chan;
+	u8                             *rx_cyclic_buf;
+	dma_addr_t                     rx_cyclic_buf_dma_mapping_addr;
+	struct dma_chan                *rx_chan;
 	struct dma_async_tx_descriptor *rxd;
-	dma_cookie_t rx_cookie;
+	dma_cookie_t                   rx_cookie;
 
-	struct openwifi_ring tx_ring[MAX_NUM_SW_QUEUE];
-	struct scatterlist tx_sg;
-	struct dma_chan *tx_chan;
+	struct openwifi_ring           tx_ring[MAX_NUM_SW_QUEUE];
+	struct scatterlist             tx_sg;
+	struct dma_chan                *tx_chan;
 	struct dma_async_tx_descriptor *txd;
-	dma_cookie_t tx_cookie;
+	dma_cookie_t                   tx_cookie;
 	// struct completion tx_dma_complete;
 	// bool openwifi_tx_first_time_run;
 
 	// int phy_tx_sn;
 	u32 slice_idx;
 	u32 dest_mac_addr_queue_map[MAX_NUM_HW_QUEUE];
-	u8 mac_addr[ETH_ALEN];
+	u8  mac_addr[ETH_ALEN];
 	u16 seqno;
 
 	bool use_short_slot;
-	u8 band;
-	u16 channel;
+	u8   band;
+	u16  channel;
 
 	u32 ampdu_reference;
 
@@ -518,9 +517,9 @@ struct openwifi_priv {
 	int last_auto_fpga_lbt_th;
 
 	struct bin_attribute bin_iq;
-	u32 tx_intf_arbitrary_iq[512];
-	u16 tx_intf_arbitrary_iq_num;
-	u8  tx_intf_iq_ctl;
+	u32                  tx_intf_arbitrary_iq[512];
+	u16                  tx_intf_arbitrary_iq_num;
+	u8                   tx_intf_iq_ctl;
 
 	struct openwifi_stat stat;
 	// u8 num_led;

driver/sdrctl_intf.c

@@ -27,7 +27,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
 		xpu_api->XPU_REG_CSMA_CFG_write(tmp); // unit us
 		return 0;
 	case OPENWIFI_CMD_GET_GAP:
-		skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
+		skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
 		if (!skb)
 			return -ENOMEM;
 		tmp = xpu_api->XPU_REG_CSMA_CFG_read();
@@ -48,7 +48,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
 		}
 		return 0;
 	case OPENWIFI_CMD_GET_SLICE_IDX:
-		skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
+		skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
 		if (!skb)
 			return -ENOMEM;
 		tmp = priv->slice_idx;
@@ -69,7 +69,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
 		}
 		return 0;
 	case OPENWIFI_CMD_GET_ADDR:
-		skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
+		skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
 		if (!skb)
 			return -ENOMEM;
 		if (priv->slice_idx>=MAX_NUM_HW_QUEUE) {
@@ -95,7 +95,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
 		}
 		return 0;
 	case OPENWIFI_CMD_GET_SLICE_TOTAL:
-		skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
+		skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
 		if (!skb)
 			return -ENOMEM;
 		tmp = (xpu_api->XPU_REG_SLICE_COUNT_TOTAL_read());
@@ -117,7 +117,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
 		}
 		return 0;
 	case OPENWIFI_CMD_GET_SLICE_START:
-		skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
+		skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
 		if (!skb)
 			return -ENOMEM;
 		tmp = (xpu_api->XPU_REG_SLICE_COUNT_START_read());
@@ -139,7 +139,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
 		}
 		return 0;
 	case OPENWIFI_CMD_GET_SLICE_END:
-		skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
+		skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
 		if (!skb)
 			return -ENOMEM;
 		tmp = (xpu_api->XPU_REG_SLICE_COUNT_END_read());
@@ -206,7 +206,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
 		printk("%s WARNING Please use command: sdrctl dev sdr0 set reg drv_xpu 0 reg_value! (1~2047, 0 means AUTO)!\n", sdr_compatible_str);
 		return -EOPNOTSUPP;
 	case OPENWIFI_CMD_GET_RSSI_TH:
-		skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
+		skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
 		if (!skb)
 			return -ENOMEM;
 		tmp_int = rssi_half_db_to_rssi_dbm(xpu_api->XPU_REG_LBT_TH_read(), priv->rssi_correction); //rssi_dbm
@@ -340,10 +340,10 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
 						tmp_int = (-reg_val); // rssi_dbm
 						tmp = rssi_dbm_to_rssi_half_db(tmp_int, priv->rssi_correction);
 						xpu_api->XPU_REG_LBT_TH_write( tmp );
-						printk("%s override FPGA LBT threshold to %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm)\n", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction));
+						printk("%s override FPGA LBT threshold to %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm). rssi corr %d (%d/%dMHz)\n", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo);
 					} else {
 						xpu_api->XPU_REG_LBT_TH_write(priv->last_auto_fpga_lbt_th);
-						printk("%s Restore last_auto_fpga_lbt_th %d(%ddBm) to FPGA. ad9361_rf_set_channel will take control\n", sdr_compatible_str, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction));
+						printk("%s Restore last_auto_fpga_lbt_th %d(%ddBm) to FPGA. ad9361_rf_set_channel will take control. rssi corr %d (%d/%dMHz)\n", sdr_compatible_str, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo);
 					}
 				}
 			} else {
@@ -358,7 +358,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
 		
 		return 0;
 	case REG_CMD_GET:
-		skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
+		skb = (struct sk_buff *)cfg80211_testmode_alloc_reply_skb(hw->wiphy, nla_total_size(sizeof(u32)));
 		if (!skb)
 			return -ENOMEM;
 		reg_addr = nla_get_u32(tb[REG_ATTR_ADDR]);
@@ -412,7 +412,7 @@ static int openwifi_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *
 				if (reg_addr_idx==DRV_XPU_REG_IDX_LBT_TH) {
 					tmp = xpu_api->XPU_REG_LBT_TH_read();//rssi_half_db
 					tmp_int = rssi_half_db_to_rssi_dbm(tmp, priv->rssi_correction); //rssi_dbm
-					printk("%s FPGA LBT threshold %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm)\n", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction));
+					printk("%s FPGA LBT threshold %d(%ddBm). The last_auto_fpga_lbt_th %d(%ddBm). rssi corr %d (%d/%dMHz)\n", sdr_compatible_str, tmp, tmp_int, priv->last_auto_fpga_lbt_th, rssi_half_db_to_rssi_dbm(priv->last_auto_fpga_lbt_th, priv->rssi_correction), priv->rssi_correction, priv->actual_tx_lo, priv->actual_rx_lo);
 				}
 				tmp = priv->drv_xpu_reg_val[reg_addr_idx];
 			} else {

driver/side_ch/make_driver.sh

@@ -20,7 +20,7 @@ else
     exit 1
 fi
 
-if [ -d "$XILINX_DIR/SDK" ]; then
+if [ -d "$XILINX_DIR/Vitis" ]; then
     echo "\$XILINX_DIR is found!"
 else
     echo "\$XILINX_DIR is not correct. Please check!"
@@ -34,7 +34,7 @@ else
     echo "\$ARCH_OPTION is valid!"
 fi
 
-source $XILINX_DIR/SDK/2018.3/settings64.sh
+source $XILINX_DIR/Vitis/2021.1/settings64.sh
 if [ "$ARCH_OPTION" == "64" ]; then
     LINUX_KERNEL_SRC_DIR=$OPENWIFI_DIR/adi-linux-64/
     ARCH="arm64"

driver/side_ch/side_ch.c

@@ -375,9 +375,9 @@ static int get_side_info(int num_eq, int iq_len) {
 		num_dma_symbol_per_trans = HEADER_LEN + CSI_LEN + num_eq*EQUALIZER_LEN;
 	//set number of dma symbols expected to ps
 	num_dma_symbol = SIDE_CH_REG_M_AXIS_DATA_COUNT_read();
-	printk("%s get_side_info m axis data count %d per trans %d\n", side_ch_compatible_str, num_dma_symbol, num_dma_symbol_per_trans);
+	// printk("%s get_side_info m axis data count %d per trans %d\n", side_ch_compatible_str, num_dma_symbol, num_dma_symbol_per_trans);
 	num_dma_symbol = num_dma_symbol_per_trans*(num_dma_symbol/num_dma_symbol_per_trans);
-	printk("%s get_side_info actual num dma symbol %d\n", side_ch_compatible_str, num_dma_symbol);
+	// printk("%s get_side_info actual num dma symbol %d\n", side_ch_compatible_str, num_dma_symbol);
 	if (num_dma_symbol == 0)
 		return(-2);
 
@@ -464,13 +464,13 @@ static void side_ch_nl_recv_msg(struct sk_buff *skb) {
     reg_type = cmd_buf[1];
     reg_idx = cmd_buf[2];
     reg_val = cmd_buf[3];
-	printk("%s recv msg: len %d action_flag %d reg_type %d reg_idx %d reg_val %u\n", side_ch_compatible_str, nlmsg_len(nlh), action_flag, reg_type, reg_idx, reg_val);
+	// printk("%s recv msg: len %d action_flag %d reg_type %d reg_idx %d reg_val %u\n", side_ch_compatible_str, nlmsg_len(nlh), action_flag, reg_type, reg_idx, reg_val);
 
 	pid = nlh->nlmsg_pid; /*pid of sending process */
 
 	if (action_flag==ACTION_SIDE_INFO_GET) {
 		res = get_side_info(num_eq_init, iq_len_init);
-		printk(KERN_INFO "%s recv msg: get_side_info(%d,%d) res %d\n", side_ch_compatible_str, num_eq_init, iq_len_init, res);
+		// printk(KERN_INFO "%s recv msg: get_side_info(%d,%d) res %d\n", side_ch_compatible_str, num_eq_init, iq_len_init, res);
 		if (res>0) {
 			msg_size = res;
 			// printk("%s recv msg: %d %d %d %d %d %d %d %d\n", side_ch_compatible_str, msg[0], msg[1], msg[2], msg[3], msg[4], msg[5], msg[6], msg[7]);
@@ -599,11 +599,13 @@ static int dev_probe(struct platform_device *pdev) {
 	// 	goto free_chan_to_pl;
 	// }
 
-	chan_to_ps = dma_request_slave_channel(&(pdev->dev), "tx_dma_s2mm");
-	if (IS_ERR(chan_to_ps)) {
+	chan_to_ps = dma_request_chan(&(pdev->dev), "tx_dma_s2mm");
+	if (IS_ERR(chan_to_ps) || chan_to_ps==NULL) {
 		err = PTR_ERR(chan_to_ps);
-		pr_err("%s dev_probe: No channel to PS. %d\n",side_ch_compatible_str,err);
-		goto free_chan_to_ps;
+		if (err != -EPROBE_DEFER) {
+			pr_err("%s dev_probe: No chan_to_ps ret %d chan_to_ps 0x%p\n",side_ch_compatible_str, err, chan_to_ps);
+			goto free_chan_to_ps;
+		}
 	}
 
 	printk("%s dev_probe: DMA channel setup successfully. chan_to_pl 0x%p chan_to_ps 0x%p\n",side_ch_compatible_str, chan_to_pl, chan_to_ps);

driver/sysfs_intf.c

@@ -990,10 +990,12 @@ static ssize_t csma_cfg0_show(struct device *input_dev, struct device_attribute
 	reg_val = xpu_api->XPU_REG_FORCE_IDLE_MISC_read();
 	priv->stat.csma_cfg0 = reg_val;
 	
-	return sprintf(buf, "nav_disable %d difs_disable %d eifs_disable %d cw_override %d cw override val %d wait_after_decode_top %d\n", 
+	return sprintf(buf, "nav_disable %d difs_disable %d eifs_disable %d eifs_by_rx_fail_disable %d eifs_by_tx_fail_disable %d cw_override %d cw override val %d wait_after_decode_top %d\n", 
 					(reg_val>>31)&1, 
 					(reg_val>>30)&1, 
 					(reg_val>>29)&1, 
+          (reg_val>>27)&1, 
+          (reg_val>>26)&1, 
 					(reg_val>>28)&1, 
 					(reg_val>>16)&0xf, 
 					(reg_val>>0)&0xff);

driver/tx_intf/tx_intf.c

@@ -225,7 +225,7 @@ static const struct of_device_id dev_of_ids[] = {
 MODULE_DEVICE_TABLE(of, dev_of_ids);
 
 static struct tx_intf_driver_api tx_intf_driver_api_inst;
-static struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst;
+struct tx_intf_driver_api *tx_intf_api = &tx_intf_driver_api_inst;
 EXPORT_SYMBOL(tx_intf_api);
 
 static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_symbol_to_ps, enum openwifi_fpga_type fpga_type){
@@ -262,7 +262,7 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_sym
 			break;
 
 		case TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH:
-			printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT0\n", tx_intf_compatible_str);
+			printk("%s hw_init mode TX_INTF_BW_20MHZ_AT_0MHZ_ANT_BOTH\n", tx_intf_compatible_str);
 			mixer_cfg = 0x2001F400;
 			ant_sel=0x11;
 			break;
@@ -311,7 +311,7 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_sym
 	if (mode!=TX_INTF_AXIS_LOOP_BACK) {
 		tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
 		tx_intf_api->TX_INTF_REG_CSI_FUZZER_write(0);
-		tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed
+		tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(16*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed
 	
 		tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config);
 		tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);
@@ -350,9 +350,9 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_sym
 		tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
 	}
 
-	if (mode == TX_INTF_BYPASS) {
-		tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8]
-	}
+	// if (mode == TX_INTF_BYPASS) {
+	// 	tx_intf_api->TX_INTF_REG_CFG_DATA_TO_ANT_write(0x100); //slv_reg10[8] -- bit 8 not used anymore. only bit0/1 are still reserved. 
+	// }
 
 	printk("%s hw_init err %d\n", tx_intf_compatible_str, err);
 	return(err);
@@ -437,7 +437,7 @@ static int dev_probe(struct platform_device *pdev)
 	if (IS_ERR(base_addr))
 		return PTR_ERR(base_addr);
 
-	printk("%s dev_probe io start 0x%08llx end 0x%08llx name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
+	printk("%s dev_probe io start 0x%08x end 0x%08x name %s flags 0x%08x desc 0x%08x\n", tx_intf_compatible_str,io->start,io->end,io->name,(u32)io->flags,(u32)io->desc);
 	printk("%s dev_probe base_addr 0x%p\n", tx_intf_compatible_str,(void*)base_addr);
 	printk("%s dev_probe tx_intf_driver_api_inst 0x%p\n", tx_intf_compatible_str, (void*)(&tx_intf_driver_api_inst) );
 	printk("%s dev_probe             tx_intf_api 0x%p\n", tx_intf_compatible_str, (void*)tx_intf_api);

driver/xpu/xpu.c

@@ -150,14 +150,6 @@ static inline u32 XPU_REG_FORCE_IDLE_MISC_read(void){
 	return reg_read(XPU_REG_FORCE_IDLE_MISC_ADDR);
 }
 
-static inline u32 XPU_REG_TRX_STATUS_read(void){
-	return reg_read(XPU_REG_TRX_STATUS_ADDR);
-}
-
-static inline u32 XPU_REG_TX_RESULT_read(void){
-	return reg_read(XPU_REG_TX_RESULT_ADDR);
-}
-
 static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){
 	return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR);
 }
@@ -180,34 +172,6 @@ static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){
 	XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low
 }
 
-static inline u32 XPU_REG_FC_DI_read(void){
-	return reg_read(XPU_REG_FC_DI_ADDR);
-}
-
-static inline u32 XPU_REG_ADDR1_LOW_read(void){
-	return reg_read(XPU_REG_ADDR1_LOW_ADDR);
-}
-
-static inline u32 XPU_REG_ADDR1_HIGH_read(void){
-	return reg_read(XPU_REG_ADDR1_HIGH_ADDR);
-}
-
-static inline u32 XPU_REG_ADDR2_LOW_read(void){
-	return reg_read(XPU_REG_ADDR2_LOW_ADDR);
-}
-
-static inline u32 XPU_REG_ADDR2_HIGH_read(void){
-	return reg_read(XPU_REG_ADDR2_HIGH_ADDR);
-}
-
-// static inline void XPU_REG_LBT_TH_write(u32 value, u32 en_flag) {
-// 	if (en_flag) {
-// 		reg_write(XPU_REG_LBT_TH_ADDR, value&0x7FFFFFFF);
-// 	} else {
-// 		reg_write(XPU_REG_LBT_TH_ADDR, value|0x80000000);
-// 	}
-// }
-
 static inline void XPU_REG_LBT_TH_write(u32 value) {
 	reg_write(XPU_REG_LBT_TH_ADDR, value);
 }
@@ -307,7 +271,7 @@ static const struct of_device_id dev_of_ids[] = {
 MODULE_DEVICE_TABLE(of, dev_of_ids);
 
 static struct xpu_driver_api xpu_driver_api_inst;
-static struct xpu_driver_api *xpu_api = &xpu_driver_api_inst;
+struct xpu_driver_api *xpu_api = &xpu_driver_api_inst;
 EXPORT_SYMBOL(xpu_api);
 
 static inline u32 hw_init(enum xpu_mode mode){
@@ -370,31 +334,12 @@ static inline u32 hw_init(enum xpu_mode mode){
 	// From CMW measurement: lo up 1us before the packet; lo down 0.4us after the packet/RF port switches 1.2us before and 0.2us after
 	xpu_api->XPU_REG_BB_RF_DELAY_write((16<<24)|(0<<16)|(26<<8)|9); // calibrated by ila and spectrum analyzer (trigger mode)
 
-	// setup time schedule of 4 slices
-	// slice 0
-	xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms
-	xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms
-	xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms
-
-	// slice 1
-	xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms
-	xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms
-	//xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms
-	xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms
-
-	// slice 2
-	xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms
-	//xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms
-	xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms
-	//xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms
-	xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms
-
-	// slice 3
-	xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms
-	//xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms
-	xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms
-	//xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms
-	xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms
+	// setup time schedule of all queues. all time open.
+	for (i=0; i<4; i++) {
+		xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((i<<20)|16);//total 16us
+		xpu_api->XPU_REG_SLICE_COUNT_START_write((i<<20)|0); //start 0us
+		xpu_api->XPU_REG_SLICE_COUNT_END_write((i<<20)|16);  //end   16us
+	}
 
 	// all slice sync rest
 	xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time
@@ -425,7 +370,9 @@ static inline u32 hw_init(enum xpu_mode mode){
 	rssi_half_db_th = 87<<1; // -62dBm
 	xpu_api->XPU_REG_LBT_TH_write(rssi_half_db_th); // set IQ rssi th step .5dB to xxx and enable it
 
-	xpu_api->XPU_REG_FORCE_IDLE_MISC_write(75); //control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals
+  // control the duration to force ch_idle after decoding a packet due to imperfection of agc and signals
+  // (1<<26) to disable eifs_trigger_by_last_tx_fail by default (standard does not ask so)
+	xpu_api->XPU_REG_FORCE_IDLE_MISC_write((1<<26)|75);
 
 	//xpu_api->XPU_REG_CSMA_DEBUG_write((1<<31)|(20<<24)|(4<<19)|(3<<14)|(10<<7)|(5));
 	xpu_api->XPU_REG_CSMA_DEBUG_write(0);
@@ -433,43 +380,17 @@ static inline u32 hw_init(enum xpu_mode mode){
 	// xpu_api->XPU_REG_CSMA_CFG_write(268435459);  // Linux will do config for each queue via openwifi_conf_tx
 	// xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); // Linux will do config for each queue via openwifi_conf_tx
 
-	xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+23)<<16)|(0+23) );
-
-	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
+//	// ------- assume 2.4 and 5GHz have the same SIFS (6us signal extension) --------
+	xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+25)<<16)|((16+25)<<0) );
+	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
 	xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
+//	// ------- assume 2.4 and 5GHz have different SIFS --------
+	// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+23)<<16)|(0+23) );
+	// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
+	// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
 
 	xpu_api->XPU_REG_DIFS_ADVANCE_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|2); //us. bit31~16 max pkt length threshold
 
-	// setup time schedule of 4 slices
-	// slice 0
-	xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write(50000-1); // total 50ms
-	xpu_api->XPU_REG_SLICE_COUNT_START_write(0); //start 0ms
-	xpu_api->XPU_REG_SLICE_COUNT_END_write(50000-1); //end 50ms
-
-	// slice 1
-	xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((1<<20)|(50000-1)); // total 50ms
-	xpu_api->XPU_REG_SLICE_COUNT_START_write((1<<20)|(0)); //start 0ms
-	//xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(20000-1)); //end 20ms
-	xpu_api->XPU_REG_SLICE_COUNT_END_write((1<<20)|(50000-1)); //end 20ms
-
-	// slice 2
-	xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((2<<20)|(50000-1)); // total 50ms
-	//xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(20000)); //start 20ms
-	xpu_api->XPU_REG_SLICE_COUNT_START_write((2<<20)|(0)); //start 20ms
-	//xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(40000-1)); //end 20ms
-	xpu_api->XPU_REG_SLICE_COUNT_END_write((2<<20)|(50000-1)); //end 20ms
-
-	// slice 3
-	xpu_api->XPU_REG_SLICE_COUNT_TOTAL_write((3<<20)|(50000-1)); // total 50ms
-	//xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(40000)); //start 40ms
-	xpu_api->XPU_REG_SLICE_COUNT_START_write((3<<20)|(0)); //start 40ms
-	//xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms
-	xpu_api->XPU_REG_SLICE_COUNT_END_write((3<<20)|(50000-1)); //end 20ms
-
-	// all slice sync rest
-	xpu_api->XPU_REG_MULTI_RST_write(1<<7); //bit7 reset the counter for all queues at the same time
-	xpu_api->XPU_REG_MULTI_RST_write(0<<7); 
-
 	printk("%s hw_init err %d\n", xpu_compatible_str, err);
 	return(err);
 }
@@ -535,21 +456,12 @@ static int dev_probe(struct platform_device *pdev)
 	xpu_api->XPU_REG_FORCE_IDLE_MISC_write=XPU_REG_FORCE_IDLE_MISC_write;
 	xpu_api->XPU_REG_FORCE_IDLE_MISC_read=XPU_REG_FORCE_IDLE_MISC_read;
 
-	xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read;
-	xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read;
-
 	xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read;
 	xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read;
 	xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write;
 	xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write;
 	xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write;
 	
-	xpu_api->XPU_REG_FC_DI_read=XPU_REG_FC_DI_read;
-	xpu_api->XPU_REG_ADDR1_LOW_read=XPU_REG_ADDR1_LOW_read;
-	xpu_api->XPU_REG_ADDR1_HIGH_read=XPU_REG_ADDR1_HIGH_read;
-	xpu_api->XPU_REG_ADDR2_LOW_read=XPU_REG_ADDR2_LOW_read;
-	xpu_api->XPU_REG_ADDR2_HIGH_read=XPU_REG_ADDR2_HIGH_read;
-
 	xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write;
 	xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read;
 

kernel_boot/10-network-device.rules

@@ -0,0 +1 @@
+SUBSYSTEM=="net", ACTION=="add", ATTR{address}=="66:55:44:33:22:*", NAME="sdr0"

kernel_boot/ad9361.patch

@@ -0,0 +1,68 @@
+diff --git a/drivers/iio/adc/ad9361.c b/drivers/iio/adc/ad9361.c
+index b21e2129e27c..b53d7b7ab20d 100644
+--- a/drivers/iio/adc/ad9361.c
++++ b/drivers/iio/adc/ad9361.c
+@@ -1234,7 +1234,7 @@ static int ad9361_load_mixer_gm_subtable(struct ad9361_rf_phy *phy)
+ 	return 0;
+ }
+ 
+-static int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
++int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
+ 			       bool tx1, bool tx2, bool immed)
+ {
+ 	u8 buf[2];
+@@ -1266,8 +1266,8 @@ static int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
+ 
+ 	return ret;
+ }
+-
+-static int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)
++EXPORT_SYMBOL(ad9361_set_tx_atten);
++int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)
+ {
+ 	u8 buf[2];
+ 	int ret = 0;
+@@ -1285,7 +1285,7 @@ static int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)
+ 
+ 	return code;
+ }
+-
++EXPORT_SYMBOL(ad9361_get_tx_atten);
+ int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state)
+ {
+ 	struct ad9361_rf_phy_state *st = phy->state;
+@@ -3744,7 +3744,7 @@ static int ad9361_get_auxadc(struct ad9361_rf_phy *phy)
+   // Setup Control Outs
+   //************************************************************
+ 
+-static int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
++int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
+ 				  struct ctrl_outs_control *ctrl)
+ {
+ 	struct spi_device *spi = phy->spi;
+@@ -3754,6 +3754,7 @@ static int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
+ 	ad9361_spi_write(spi, REG_CTRL_OUTPUT_POINTER, ctrl->index); // Ctrl Out index
+ 	return ad9361_spi_write(spi, REG_CTRL_OUTPUT_ENABLE, ctrl->en_mask); // Ctrl Out [7:0] output enable
+ }
++EXPORT_SYMBOL(ad9361_ctrl_outs_setup);
+   //************************************************************
+   // Setup GPO
+   //************************************************************
+@@ -5235,7 +5236,7 @@ static int ad9361_setup(struct ad9361_rf_phy *phy)
+ 
+ }
+ 
+-static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)
++int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)
+ {
+ 	struct ad9361_rf_phy_state *st = phy->state;
+ 	int ret;
+@@ -5268,7 +5269,7 @@ static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)
+ 
+ 	return ret;
+ }
+-
++EXPORT_SYMBOL(ad9361_do_calib_run);
+ static int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,
+ 				     u32 rf_rx_bw, u32 rf_tx_bw)
+ {

kernel_boot/ad9361_conv.patch

@@ -0,0 +1,14 @@
+diff --git a/drivers/iio/adc/ad9361_conv.c b/drivers/iio/adc/ad9361_conv.c
+index 1902e7d07501..ef421dbd5e70 100644
+--- a/drivers/iio/adc/ad9361_conv.c
++++ b/drivers/iio/adc/ad9361_conv.c
+@@ -449,7 +449,8 @@ static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy,
+ 				 unsigned long max_freq,
+ 				 enum dig_tune_flags flags, bool tx)
+ {
+-	static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};
++	// static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};
++	static const unsigned int rates[3] = {25000000U, 40000000U, 40000000U};
+ 	struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
+ 	unsigned int s0, s1, c0, c1;
+ 	unsigned int i, j, r;

kernel_boot/axi_hdmi_crtc.patch

@@ -0,0 +1,13 @@
+diff --git a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c
+index f24669f623d6..70c5769019fa 100644
+--- a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c
++++ b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c
+@@ -54,7 +54,7 @@ static struct dma_async_tx_descriptor *axi_hdmi_vdma_prep_interleaved_desc(
+ 		memset(&vdma_config, 0, sizeof(vdma_config));
+ 		vdma_config.park = 1;
+ 		vdma_config.coalesc = 0xff;
+-		xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config);
++		// xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config);
+ 	}
+ #endif
+ 

kernel_boot/boards/antsdr_e200/README.md

@@ -0,0 +1,14 @@
+# ANTSDR-E200
+
+ANTSDR-E200 is similar to MicroPhase ANTSDR-E310 device. 
+
+ANTSDR-E200 has a smaller size and some differences in hardware structure. The ethernet is placed at the PL side.
+
+![e200_struct](README.assets/e200_struct.svg)
+
+Since the performance of the zynq processor is not very strong, the Ethernet cannot run at a very high bandwidth. For some SDR applications, the Ethernet may be required to transmit baseband signals above 20MSPS sample rate. In this case, the bandwidth of the Ethernet  will reach 80MB/s. If the Ethernet on the PS side wants to run at this bandwidth, it will take up a lot of CPU resources and the bandwidth is still difficult to meet. For this reason, we moved the network port to the PL side.
+
+But this has no effect on IIO-based SDR drivers, because we still use ZYNQ's GEM controller. O(∩_∩)O
+
+When we moved the ethernet to PL, the ANTSDR-E200 could support UHD driver, If anyone is interested in this, you can refer to our project [antsdr_uhd](https://github.com/MicroPhase/antsdr_uhd). 
+

kernel_boot/boards/antsdr_e200/devicetree.dts

@@ -0,0 +1,876 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+	compatible = "xlnx,zynq-7000";
+	interrupt-parent = <0x1>;
+	model = "ANTSDR-E200";
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0x0>;
+			clocks = <0x2 0x3>;
+			clock-latency = <0x3e8>;
+			cpu0-supply = <0x3>;
+			operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0x1>;
+			clocks = <0x2 0x3>;
+		};
+	};
+
+	fpga-full {
+		compatible = "fpga-region";
+		fpga-mgr = <0x4>;
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		ranges;
+	};
+
+	pmu@f8891000 {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
+		interrupt-parent = <0x1>;
+		reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
+	};
+
+	fixedregulator {
+		compatible = "regulator-fixed";
+		regulator-name = "VCCPINT";
+		regulator-min-microvolt = <0xf4240>;
+		regulator-max-microvolt = <0xf4240>;
+		regulator-boot-on;
+		regulator-always-on;
+		linux,phandle = <0x3>;
+		phandle = <0x3>;
+	};
+
+	amba {
+		u-boot,dm-pre-reloc;
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		interrupt-parent = <0x1>;
+		ranges;
+
+		adc@f8007100 {
+			compatible = "xlnx,zynq-xadc-1.00.a";
+			reg = <0xf8007100 0x20>;
+			interrupts = <0x0 0x7 0x4>;
+			interrupt-parent = <0x1>;
+			clocks = <0x2 0xc>;
+		};
+
+		can@e0008000 {
+			compatible = "xlnx,zynq-can-1.0";
+			status = "disabled";
+			clocks = <0x2 0x13 0x2 0x24>;
+			clock-names = "can_clk", "pclk";
+			reg = <0xe0008000 0x1000>;
+			interrupts = <0x0 0x1c 0x4>;
+			interrupt-parent = <0x1>;
+			tx-fifo-depth = <0x40>;
+			rx-fifo-depth = <0x40>;
+		};
+
+		can@e0009000 {
+			compatible = "xlnx,zynq-can-1.0";
+			status = "disabled";
+			clocks = <0x2 0x14 0x2 0x25>;
+			clock-names = "can_clk", "pclk";
+			reg = <0xe0009000 0x1000>;
+			interrupts = <0x0 0x33 0x4>;
+			interrupt-parent = <0x1>;
+			tx-fifo-depth = <0x40>;
+			rx-fifo-depth = <0x40>;
+		};
+
+		gpio@e000a000 {
+			compatible = "xlnx,zynq-gpio-1.0";
+			#gpio-cells = <0x2>;
+			clocks = <0x2 0x2a>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x14 0x4>;
+			reg = <0xe000a000 0x1000>;
+			linux,phandle = <0x6>;
+			phandle = <0x6>;
+		};
+
+		i2c@e0004000 {
+			compatible = "cdns,i2c-r1p10";
+			status = "disabled";
+			clocks = <0x2 0x26>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x19 0x4>;
+			reg = <0xe0004000 0x1000>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+		};
+
+		i2c@e0005000 {
+			compatible = "cdns,i2c-r1p10";
+			status = "disabled";
+			clocks = <0x2 0x27>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x30 0x4>;
+			reg = <0xe0005000 0x1000>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+		};
+
+		interrupt-controller@f8f01000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <0x3>;
+			interrupt-controller;
+			reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
+			linux,phandle = <0x1>;
+			phandle = <0x1>;
+		};
+
+		cache-controller@f8f02000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xf8f02000 0x1000>;
+			interrupts = <0x0 0x2 0x4>;
+			arm,data-latency = <0x3 0x2 0x2>;
+			arm,tag-latency = <0x2 0x2 0x2>;
+			cache-unified;
+			cache-level = <0x2>;
+		};
+
+		memory-controller@f8006000 {
+			compatible = "xlnx,zynq-ddrc-a05";
+			reg = <0xf8006000 0x1000>;
+		};
+
+		ocmc@f800c000 {
+			compatible = "xlnx,zynq-ocmc-1.0";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x3 0x4>;
+			reg = <0xf800c000 0x1000>;
+		};
+
+		serial@e0000000 {
+			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
+			status = "okay";
+			clocks = <0x2 0x17 0x2 0x28>;
+			clock-names = "uart_clk", "pclk";
+			reg = <0xe0000000 0x1000>;
+			interrupts = <0x0 0x1b 0x4>;
+		};
+
+		serial@e0001000 {
+			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
+			status = "okay";
+			clocks = <0x2 0x18 0x2 0x29>;
+			clock-names = "uart_clk", "pclk";
+			reg = <0xe0001000 0x1000>;
+			interrupts = <0x0 0x32 0x4>;
+		};
+
+		spi@e0006000 {
+			compatible = "xlnx,zynq-spi-r1p6";
+			reg = <0xe0006000 0x1000>;
+			status = "okay";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x1a 0x4>;
+			clocks = <0x2 0x19 0x2 0x22>;
+			clock-names = "ref_clk", "pclk";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+
+			ad9361-phy@0 {
+				#address-cells = <0x1>;
+				#size-cells = <0x0>;
+				#clock-cells = <0x1>;
+				compatible = "adi,ad9361";
+				reg = <0x0>;
+				spi-cpha;
+				spi-max-frequency = <0x989680>;
+				clocks = <0x5 0x0>;
+				clock-names = "ad9364_ext_refclk";
+				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
+				adi,digital-interface-tune-skip-mode = <0x0>;
+				adi,pp-tx-swap-enable;
+				adi,pp-rx-swap-enable;
+				adi,rx-frame-pulse-mode-enable;
+				adi,lvds-mode-enable;
+				adi,lvds-bias-mV = <0x96>;
+				adi,lvds-rx-onchip-termination-enable;
+				adi,rx-data-delay = <0x4>;
+				adi,tx-fb-clock-delay = <0x7>;
+				adi,xo-disable-use-ext-refclk-enable;
+				adi,2rx-2tx-mode-enable;
+				adi,frequency-division-duplex-mode-enable;
+				adi,rx-rf-port-input-select = <0x0>;
+				adi,tx-rf-port-input-select = <0x0>;
+				adi,tx-attenuation-mdB = <0x2710>;
+				adi,tx-lo-powerdown-managed-enable;
+				adi,rf-rx-bandwidth-hz = <0x112a880>;
+				adi,rf-tx-bandwidth-hz = <0x112a880>;
+				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
+				adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
+				adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
+				adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
+				adi,gc-rx1-mode = <0x2>;
+				adi,gc-rx2-mode = <0x2>;
+				adi,gc-adc-ovr-sample-size = <0x4>;
+				adi,gc-adc-small-overload-thresh = <0x2f>;
+				adi,gc-adc-large-overload-thresh = <0x3a>;
+				adi,gc-lmt-overload-high-thresh = <0x320>;
+				adi,gc-lmt-overload-low-thresh = <0x2c0>;
+				adi,gc-dec-pow-measurement-duration = <0x2000>;
+				adi,gc-low-power-thresh = <0x18>;
+				adi,mgc-inc-gain-step = <0x2>;
+				adi,mgc-dec-gain-step = <0x2>;
+				adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
+				adi,agc-attack-delay-extra-margin-us = <0x1>;
+				adi,agc-outer-thresh-high = <0x5>;
+				adi,agc-outer-thresh-high-dec-steps = <0x2>;
+				adi,agc-inner-thresh-high = <0xa>;
+				adi,agc-inner-thresh-high-dec-steps = <0x1>;
+				adi,agc-inner-thresh-low = <0xc>;
+				adi,agc-inner-thresh-low-inc-steps = <0x1>;
+				adi,agc-outer-thresh-low = <0x12>;
+				adi,agc-outer-thresh-low-inc-steps = <0x2>;
+				adi,agc-adc-small-overload-exceed-counter = <0xa>;
+				adi,agc-adc-large-overload-exceed-counter = <0xa>;
+				adi,agc-adc-large-overload-inc-steps = <0x2>;
+				adi,agc-lmt-overload-large-exceed-counter = <0xa>;
+				adi,agc-lmt-overload-small-exceed-counter = <0xa>;
+				adi,agc-lmt-overload-large-inc-steps = <0x2>;
+				adi,agc-gain-update-interval-us = <0x3e8>;
+				adi,fagc-dec-pow-measurement-duration = <0x40>;
+				adi,fagc-lp-thresh-increment-steps = <0x1>;
+				adi,fagc-lp-thresh-increment-time = <0x5>;
+				adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
+				adi,fagc-final-overrange-count = <0x3>;
+				adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
+				adi,fagc-lmt-final-settling-steps = <0x1>;
+				adi,fagc-lock-level = <0xa>;
+				adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
+				adi,fagc-lock-level-lmt-gain-increase-enable;
+				adi,fagc-lpf-final-settling-steps = <0x1>;
+				adi,fagc-optimized-gain-offset = <0x5>;
+				adi,fagc-power-measurement-duration-in-state5 = <0x40>;
+				adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
+				adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
+				adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
+				adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
+				adi,fagc-rst-gla-large-adc-overload-enable;
+				adi,fagc-rst-gla-large-lmt-overload-enable;
+				adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
+				adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
+				adi,fagc-state-wait-time-ns = <0x104>;
+				adi,fagc-use-last-lock-level-for-set-gain-enable;
+				adi,rssi-restart-mode = <0x3>;
+				adi,rssi-delay = <0x1>;
+				adi,rssi-wait = <0x1>;
+				adi,rssi-duration = <0x3e8>;
+				adi,ctrl-outs-index = <0x0>;
+				adi,ctrl-outs-enable-mask = <0xff>;
+				adi,temp-sense-measurement-interval-ms = <0x3e8>;
+				adi,temp-sense-offset-signed = <0xce>;
+				adi,temp-sense-periodic-measurement-enable;
+				adi,aux-dac-manual-mode-enable;
+				adi,aux-dac1-default-value-mV = <0x0>;
+				adi,aux-dac1-rx-delay-us = <0x0>;
+				adi,aux-dac1-tx-delay-us = <0x0>;
+				adi,aux-dac2-default-value-mV = <0x0>;
+				adi,aux-dac2-rx-delay-us = <0x0>;
+				adi,aux-dac2-tx-delay-us = <0x0>;
+				en_agc-gpios = <0x6 0x62 0x0>;
+				sync-gpios = <0x6 0x63 0x0>;
+				reset-gpios = <0x6 0x64 0x0>;
+				enable-gpios = <0x6 0x65 0x0>;
+				txnrx-gpios = <0x6 0x66 0x0>;
+				linux,phandle = <0xb>;
+				phandle = <0xb>;
+			};
+		};
+
+		spi@e0007000 {
+			compatible = "xlnx,zynq-spi-r1p6";
+			reg = <0xe0007000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x31 0x4>;
+			clocks = <0x2 0x1a 0x2 0x23>;
+			clock-names = "ref_clk", "pclk";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+		};
+
+		spi@e000d000 {
+			clock-names = "ref_clk", "pclk";
+			clocks = <0x2 0xa 0x2 0x2b>;
+			compatible = "xlnx,zynq-qspi-1.0";
+			status = "okay";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x13 0x4>;
+			reg = <0xe000d000 0x1000>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			is-dual = <0x0>;
+			num-cs = <0x1>;
+
+			ps7-qspi@0 {
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+				spi-tx-bus-width = <0x1>;
+				spi-rx-bus-width = <0x4>;
+				compatible = "n25q256a", "jedec,spi-nor";
+				reg = <0x0>;
+				spi-max-frequency = <0x2faf080>;
+
+				partition@qspi-fsbl-uboot {
+					label = "qspi-fsbl-uboot";
+					reg = <0x0 0xe0000>;
+				};
+
+				partition@qspi-uboot-env {
+					label = "qspi-uboot-env";
+					reg = <0xe0000 0x20000>;
+				};
+
+				partition@qspi-linux {
+					label = "qspi-linux";
+					reg = <0x100000 0x500000>;
+				};
+
+				partition@qspi-device-tree {
+					label = "qspi-device-tree";
+					reg = <0x600000 0x20000>;
+				};
+
+				partition@qspi-rootfs {
+					label = "qspi-rootfs";
+					reg = <0x620000 0xce0000>;
+				};
+
+				partition@qspi-bitstream {
+					label = "qspi-bitstream";
+					reg = <0x1300000 0xd00000>;
+				};
+			};
+		};
+
+		memory-controller@e000e000 {
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			status = "disabled";
+			clock-names = "memclk", "aclk";
+			clocks = <0x2 0xb 0x2 0x2c>;
+			compatible = "arm,pl353-smc-r2p1";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x12 0x4>;
+			ranges;
+			reg = <0xe000e000 0x1000>;
+
+			flash@e1000000 {
+				status = "disabled";
+				compatible = "arm,pl353-nand-r2p1";
+				reg = <0xe1000000 0x1000000>;
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+			};
+
+			flash@e2000000 {
+				status = "disabled";
+				compatible = "cfi-flash";
+				reg = <0xe2000000 0x2000000>;
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+			};
+		};
+
+		ethernet@e000b000 {
+			compatible = "cdns,zynq-gem", "cdns,gem";
+			reg = <0xe000b000 0x1000>;
+			status = "okay";
+			interrupts = <0x0 0x16 0x4>;
+			clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			phy-handle = <&phy0>;
+			phy-mode = "rgmii-id";
+			xlnx,has-mdio = <0x1>;
+			gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;
+
+			phy0: phy@1 {
+				compatible = "ethernet-phy-id011c.c916";
+				device_type = "ethernet-phy";
+				reg = <0x1>;
+			};
+
+			gmii_to_rgmii_0:  gmiitorgmii@8 {
+				compatible = "xlnx,gmii-to-rgmii-1.0";
+				reg = <0x8>;
+				phy-handle = <&phy0>;
+			};
+		};
+
+		ethernet@e000c000 {
+			compatible = "cdns,zynq-gem", "cdns,gem";
+			reg = <0xe000c000 0x1000>;
+			status = "disabled";
+			interrupts = <0x0 0x2d 0x4>;
+			clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+		};
+
+		mmc@e0100000 {
+			compatible = "arasan,sdhci-8.9a";
+			status = "okay";
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <0x2 0x15 0x2 0x20>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x18 0x4>;
+			reg = <0xe0100000 0x1000>;
+			disable-wp;
+		};
+
+		mmc@e0101000 {
+			compatible = "arasan,sdhci-8.9a";
+			status = "disabled";
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <0x2 0x16 0x2 0x21>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x2f 0x4>;
+			reg = <0xe0101000 0x1000>;
+		};
+
+		slcr@f8000000 {
+			u-boot,dm-pre-reloc;
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
+			reg = <0xf8000000 0x1000>;
+			ranges;
+			linux,phandle = <0x8>;
+			phandle = <0x8>;
+
+			clkc@100 {
+				u-boot,dm-pre-reloc;
+				#clock-cells = <0x1>;
+				compatible = "xlnx,ps7-clkc";
+				fclk-enable = <0xf>;
+				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
+				reg = <0x100 0x100>;
+				ps-clk-frequency = <0x1fca055>;
+				linux,phandle = <0x2>;
+				phandle = <0x2>;
+			};
+
+			rstc@200 {
+				compatible = "xlnx,zynq-reset";
+				reg = <0x200 0x48>;
+				#reset-cells = <0x1>;
+				syscon = <0x8>;
+			};
+
+			pinctrl@700 {
+				compatible = "xlnx,pinctrl-zynq";
+				reg = <0x700 0x200>;
+				syscon = <0x8>;
+			};
+		};
+
+		dmac@f8003000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0xf8003000 0x1000>;
+			interrupt-parent = <0x1>;
+			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
+			interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
+			#dma-cells = <0x1>;
+			#dma-channels = <0x8>;
+			#dma-requests = <0x4>;
+			clocks = <0x2 0x1b>;
+			clock-names = "apb_pclk";
+		};
+
+		devcfg@f8007000 {
+			compatible = "xlnx,zynq-devcfg-1.0";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x8 0x4>;
+			reg = <0xf8007000 0x100>;
+			clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
+			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
+			syscon = <0x8>;
+			linux,phandle = <0x4>;
+			phandle = <0x4>;
+		};
+
+		efuse@f800d000 {
+			compatible = "xlnx,zynq-efuse";
+			reg = <0xf800d000 0x20>;
+		};
+
+		timer@f8f00200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0xf8f00200 0x20>;
+			interrupts = <0x1 0xb 0x301>;
+			interrupt-parent = <0x1>;
+			clocks = <0x2 0x4>;
+		};
+
+		timer@f8001000 {
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
+			compatible = "cdns,ttc";
+			clocks = <0x2 0x6>;
+			reg = <0xf8001000 0x1000>;
+		};
+
+		timer@f8002000 {
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
+			compatible = "cdns,ttc";
+			clocks = <0x2 0x6>;
+			reg = <0xf8002000 0x1000>;
+		};
+
+		timer@f8f00600 {
+			interrupt-parent = <0x1>;
+			interrupts = <0x1 0xd 0x301>;
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xf8f00600 0x20>;
+			clocks = <0x2 0x4>;
+		};
+
+		usb@e0002000 {
+			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
+			status = "disabled";
+			clocks = <0x2 0x1c>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x15 0x4>;
+			reg = <0xe0002000 0x1000>;
+			phy_type = "ulpi";
+			dr_mode = "host";
+			xlnx,phy-reset-gpio = <0x6 0x7 0x0>;
+		};
+
+		usb@e0003000 {
+			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
+			status = "disabled";
+			clocks = <0x2 0x1d>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x2c 0x4>;
+			reg = <0xe0003000 0x1000>;
+			phy_type = "ulpi";
+		};
+
+		watchdog@f8005000 {
+			clocks = <0x2 0x2d>;
+			compatible = "cdns,wdt-r1p2";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x9 0x1>;
+			reg = <0xf8005000 0x1000>;
+			timeout-sec = <0xa>;
+		};
+	};
+
+	aliases {
+		ethernet0 = "/amba/ethernet@e000b000";
+		serial0 = "/amba/serial@e0000000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x20000000>;
+	};
+
+	chosen {
+		linux,stdout-path = "/amba@0/uart@E0000000";
+	};
+
+	clocks {
+
+		clock@0 {
+			#clock-cells = <0x0>;
+			compatible = "adjustable-clock";
+			clock-frequency = <0x2625a00>;
+			clock-accuracy = <0x30d40>;
+			clock-output-names = "ad9364_ext_refclk";
+			linux,phandle = <0x5>;
+			phandle = <0x5>;
+		};
+
+		clock@1 {
+			#clock-cells = <0x0>;
+			compatible = "fixed-clock";
+			clock-frequency = <0x16e3600>;
+			clock-output-names = "24MHz";
+			linux,phandle = <0x9>;
+			phandle = <0x9>;
+		};
+	};
+
+	usb-ulpi-gpio-gate@0 {
+		compatible = "gpio-gate-clock";
+		clocks = <0x9>;
+		#clock-cells = <0x0>;
+		enable-gpios = <0x6 0x9 0x1>;
+	};
+
+	fpga-axi@0 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		ranges;
+
+		i2c@41600000 {
+			compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
+			reg = <0x41600000 0x10000>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x3a 0x4>;
+			clocks = <0x2 0xf>;
+			clock-names = "pclk";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+
+			ad7291@20 {
+				compatible = "adi,ad7291";
+				reg = <0x20>;
+			};
+
+			ad7291-bob@2C {
+				compatible = "adi,ad7291";
+				reg = <0x2c>;
+			};
+
+			eeprom@50 {
+				compatible = "at24,24c32";
+				reg = <0x50>;
+			};
+		};
+
+		// dma@7c400000 {
+		// 	compatible = "adi,axi-dmac-1.00.a";
+		// 	reg = <0x7c400000 0x10000>;
+		// 	#dma-cells = <0x1>;
+		// 	interrupts = <0x0 0x39 0x0>;
+		// 	clocks = <0x2 0x10>;
+		// 	linux,phandle = <0xa>;
+		// 	phandle = <0xa>;
+
+		// 	adi,channels {
+		// 		#size-cells = <0x0>;
+		// 		#address-cells = <0x1>;
+
+		// 		dma-channel@0 {
+		// 			reg = <0x0>;
+		// 			adi,source-bus-width = <0x40>;
+		// 			adi,source-bus-type = <0x2>;
+		// 			adi,destination-bus-width = <0x40>;
+		// 			adi,destination-bus-type = <0x0>;
+		// 		};
+		// 	};
+		// };
+
+		// dma@7c420000 {
+		// 	compatible = "adi,axi-dmac-1.00.a";
+		// 	reg = <0x7c420000 0x10000>;
+		// 	#dma-cells = <0x1>;
+		// 	interrupts = <0x0 0x38 0x0>;
+		// 	clocks = <0x2 0x10>;
+		// 	linux,phandle = <0xc>;
+		// 	phandle = <0xc>;
+
+		// 	adi,channels {
+		// 		#size-cells = <0x0>;
+		// 		#address-cells = <0x1>;
+
+		// 		dma-channel@0 {
+		// 			reg = <0x0>;
+		// 			adi,source-bus-width = <0x40>;
+		// 			adi,source-bus-type = <0x0>;
+		// 			adi,destination-bus-width = <0x40>;
+		// 			adi,destination-bus-type = <0x2>;
+		// 		};
+		// 	};
+		// };
+
+		sdr: sdr {
+			compatible ="sdr,sdr";
+			dmas = <&rx_dma 1
+					&tx_dma 0>;
+			dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
+			interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
+			interrupt-parent = <1>;
+			interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
+		} ;
+
+		axidmatest_1: axidmatest@1 {
+			compatible ="xlnx,axi-dma-test-1.00.a";
+			dmas = <&rx_dma 0
+				&rx_dma 1>;
+			dma-names = "axidma0", "axidma1";
+		} ;
+
+		tx_dma: dma@80400000 {
+			#dma-cells = <1>;
+			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
+			clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
+			compatible = "xlnx,axi-dma-1.00.a";
+			interrupt-names = "mm2s_introut", "s2mm_introut";
+			interrupt-parent = <1>;
+			interrupts = <0 35 4 0 36 4>;
+			reg = <0x80400000 0x10000>;
+			xlnx,addrwidth = <0x20>;
+			xlnx,include-sg ;
+			xlnx,sg-length-width = <0xe>;
+			dma-channel@80400000 {
+				compatible = "xlnx,axi-dma-mm2s-channel";
+				dma-channels = <0x1>;
+				interrupts = <0 35 4>;
+				xlnx,datawidth = <0x40>;
+				xlnx,device-id = <0x0>;
+			};
+			dma-channel@80400030 {
+				compatible = "xlnx,axi-dma-s2mm-channel";
+				dma-channels = <0x1>;
+				interrupts = <0 36 4>;
+				xlnx,datawidth = <0x40>;
+				xlnx,device-id = <0x0>;
+			};
+		};
+		
+		rx_dma: dma@80410000 {
+			#dma-cells = <1>;
+			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
+			clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
+			compatible = "xlnx,axi-dma-1.00.a";
+			//dma-coherent ;
+			interrupt-names = "mm2s_introut", "s2mm_introut";
+			interrupt-parent = <1>;
+			interrupts = <0 31 4 0 32 4>;
+			reg = <0x80410000 0x10000>;
+			xlnx,addrwidth = <0x20>;
+			xlnx,include-sg ;
+			xlnx,sg-length-width = <0xe>;
+			dma-channel@80410000 {
+				compatible = "xlnx,axi-dma-mm2s-channel";
+				dma-channels = <0x1>;
+				interrupts = <0 31 4>;
+				xlnx,datawidth = <0x40>;
+				xlnx,device-id = <0x1>;
+			};
+			dma-channel@80410030 {
+				compatible = "xlnx,axi-dma-s2mm-channel";
+				dma-channels = <0x1>;
+				interrupts = <0 32 4>;
+				xlnx,datawidth = <0x40>;
+				xlnx,device-id = <0x1>;
+			};
+		};
+
+		tx_intf_0: tx_intf@83c00000 {
+			clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
+			clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
+			compatible = "sdr,tx_intf";
+			interrupt-names = "tx_itrpt";
+			interrupt-parent = <1>;
+			interrupts = <0 34 1>;
+			reg = <0x83c00000 0x10000>;
+			xlnx,s00-axi-addr-width = <0x7>;
+			xlnx,s00-axi-data-width = <0x20>;
+		};
+
+		rx_intf_0: rx_intf@83c20000 {
+			clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
+			clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
+			compatible = "sdr,rx_intf";
+			interrupt-names = "not_valid_anymore", "rx_pkt_intr";
+			interrupt-parent = <1>;
+			interrupts = <0 29 1 0 30 1>;
+			reg = <0x83c20000 0x10000>;
+			xlnx,s00-axi-addr-width = <0x7>;
+			xlnx,s00-axi-data-width = <0x20>;
+		};
+
+		openofdm_tx_0: openofdm_tx@83c10000 {
+			clock-names = "clk";
+			clocks = <0x2 0x11>;
+			compatible = "sdr,openofdm_tx";
+			reg = <0x83c10000 0x10000>;
+		};
+
+		openofdm_rx_0: openofdm_rx@83c30000 {
+			clock-names = "clk";
+			clocks = <0x2 0x11>;
+			compatible = "sdr,openofdm_rx";
+			reg = <0x83c30000 0x10000>;
+		};
+
+		xpu_0: xpu@83c40000 {
+			clock-names = "s00_axi_aclk";
+			clocks = <0x2 0x11>;
+			compatible = "sdr,xpu";
+			reg = <0x83c40000 0x10000>;
+		};
+
+		side_ch_0: side_ch@83c50000 {
+			clock-names = "s00_axi_aclk";
+			clocks = <0x2 0x11>;
+			compatible = "sdr,side_ch";
+			reg = <0x83c50000 0x10000>;
+			dmas = <&rx_dma 0
+					&tx_dma 1>;
+			dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
+		};
+
+		cf-ad9361-lpc@79020000 {
+			compatible = "adi,axi-ad9361-6.00.a";
+			reg = <0x79020000 0x6000>;
+			// dmas = <0xa 0x0>;
+			// dma-names = "rx";
+			spibus-connected = <0xb>;
+		};
+
+		cf-ad9361-dds-core-lpc@79024000 {
+			compatible = "adi,axi-ad9361-dds-6.00.a";
+			reg = <0x79024000 0x1000>;
+			clocks = <0xb 0xd>;
+			clock-names = "sampl_clk";
+			// dmas = <0xc 0x0>;
+			// dma-names = "tx";
+		};
+
+		mwipcore@43c00000 {
+			compatible = "mathworks,mwipcore-axi4lite-v1.00";
+			reg = <0x43c00000 0xffff>;
+		};
+
+		/*axi-sysid-0@45000000 {
+			compatible = "adi,axi-sysid-1.00.a";
+			reg = <0x45000000 0x10000>;
+		};*/
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0 {
+			label = "led0:green";
+			gpios = <0x6 0x0 0>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+};

kernel_boot/boards/e310v2/README.md

@@ -0,0 +1,10 @@
+# ANTSDR-E310V2
+
+**AntSDR E310V2** is a powerful and versatile  software-defined radio (SDR) platform. It is a low-cost, easy-to-use  system for developing, testing, and deploying wireless communication  solutions such as LTE, GSM, and Wi-Fi. With its wide range of supported  frequencies and modulation schemes, it’s possible to easily experiment  with various wireless technologies.
+
+![struct](README.assets/struct.png)
+
+Based on the  original version, we have optimized the RF performance, added a GPS  module, increased an external 10M/PPS input interface, and used a VCXO.  The combination of VCXO and external reference input with DAC can  generate a more accurate and stable clock. In addition, the Ethernet on  the PL makes it possible for E310V2 to be compatible with UHD for higher bandwidth transmission.
+
+ If you are interested in using UHD with E310V2, you can find more information in our [repository](https://github.com/MicroPhase/antsdr_uhd).
+

kernel_boot/boards/sdrpi/devicetree.dts

@@ -0,0 +1,891 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x1>;
+	#size-cells = <0x1>;
+	compatible = "xlnx,zynq-7000";
+	interrupt-parent = <0x1>;
+	model = "HexSDR sdrpi (7z020+ad9361 SDR smart platform with GPSTCXO and RF AP)";
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0x0>;
+			clocks = <0x2 0x3>;
+			clock-latency = <0x3e8>;
+			cpu0-supply = <0x3>;
+			operating-points = <0xa2c2b 0xf4240 0x51616 0xf4240>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0x1>;
+			clocks = <0x2 0x3>;
+		};
+	};
+
+	fpga-full {
+		compatible = "fpga-region";
+		fpga-mgr = <0x4>;
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		ranges;
+	};
+
+	pmu@f8891000 {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
+		interrupt-parent = <0x1>;
+		reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
+	};
+
+	fixedregulator {
+		compatible = "regulator-fixed";
+		regulator-name = "VCCPINT";
+		regulator-min-microvolt = <0xf4240>;
+		regulator-max-microvolt = <0xf4240>;
+		regulator-boot-on;
+		regulator-always-on;
+		linux,phandle = <0x3>;
+		phandle = <0x3>;
+	};
+
+	amba {
+		u-boot,dm-pre-reloc;
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		interrupt-parent = <0x1>;
+		ranges;
+
+		adc@f8007100 {
+			compatible = "xlnx,zynq-xadc-1.00.a";
+			reg = <0xf8007100 0x20>;
+			interrupts = <0x0 0x7 0x4>;
+			interrupt-parent = <0x1>;
+			clocks = <0x2 0xc>;
+		};
+
+		can@e0008000 {
+			compatible = "xlnx,zynq-can-1.0";
+			status = "disabled";
+			clocks = <0x2 0x13 0x2 0x24>;
+			clock-names = "can_clk", "pclk";
+			reg = <0xe0008000 0x1000>;
+			interrupts = <0x0 0x1c 0x4>;
+			interrupt-parent = <0x1>;
+			tx-fifo-depth = <0x40>;
+			rx-fifo-depth = <0x40>;
+		};
+
+		can@e0009000 {
+			compatible = "xlnx,zynq-can-1.0";
+			status = "disabled";
+			clocks = <0x2 0x14 0x2 0x25>;
+			clock-names = "can_clk", "pclk";
+			reg = <0xe0009000 0x1000>;
+			interrupts = <0x0 0x33 0x4>;
+			interrupt-parent = <0x1>;
+			tx-fifo-depth = <0x40>;
+			rx-fifo-depth = <0x40>;
+		};
+
+		gpio@e000a000 {
+			compatible = "xlnx,zynq-gpio-1.0";
+			#gpio-cells = <0x2>;
+			clocks = <0x2 0x2a>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <0x2>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x14 0x4>;
+			reg = <0xe000a000 0x1000>;
+			linux,phandle = <0x6>;
+			phandle = <0x6>;
+		};
+
+		i2c@e0004000 {
+			compatible = "cdns,i2c-r1p10";
+			status = "disabled";
+			clocks = <0x2 0x26>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x19 0x4>;
+			reg = <0xe0004000 0x1000>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+		};
+
+		i2c@e0005000 {
+			compatible = "cdns,i2c-r1p10";
+			status = "disabled";
+			clocks = <0x2 0x27>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x30 0x4>;
+			reg = <0xe0005000 0x1000>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+		};
+
+		interrupt-controller@f8f01000 {
+			compatible = "arm,cortex-a9-gic";
+			#interrupt-cells = <0x3>;
+			interrupt-controller;
+			reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
+			linux,phandle = <0x1>;
+			phandle = <0x1>;
+		};
+
+		cache-controller@f8f02000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xf8f02000 0x1000>;
+			interrupts = <0x0 0x2 0x4>;
+			arm,data-latency = <0x3 0x2 0x2>;
+			arm,tag-latency = <0x2 0x2 0x2>;
+			cache-unified;
+			cache-level = <0x2>;
+		};
+
+		memory-controller@f8006000 {
+			compatible = "xlnx,zynq-ddrc-a05";
+			reg = <0xf8006000 0x1000>;
+		};
+
+		ocmc@f800c000 {
+			compatible = "xlnx,zynq-ocmc-1.0";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x3 0x4>;
+			reg = <0xf800c000 0x1000>;
+		};
+
+		serial@e0000000 {
+			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
+			status = "disabled";
+			clocks = <0x2 0x17 0x2 0x28>;
+			clock-names = "uart_clk", "pclk";
+			reg = <0xe0000000 0x1000>;
+			interrupts = <0x0 0x1b 0x4>;
+		};
+
+		serial@e0001000 {
+			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
+			status = "okay";
+			clocks = <0x2 0x18 0x2 0x29>;
+			clock-names = "uart_clk", "pclk";
+			reg = <0xe0001000 0x1000>;
+			interrupts = <0x0 0x32 0x4>;
+		};
+
+		spi@e0006000 {
+			compatible = "xlnx,zynq-spi-r1p6";
+			reg = <0xe0006000 0x1000>;
+			status = "okay";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x1a 0x4>;
+			clocks = <0x2 0x19 0x2 0x22>;
+			clock-names = "ref_clk", "pclk";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+
+			ad9361-phy@0 {
+				#address-cells = <0x1>;
+				#size-cells = <0x0>;
+				#clock-cells = <0x1>;
+				compatible = "adi,ad9361";
+				reg = <0x0>;
+				spi-cpha;
+				spi-max-frequency = <0x989680>;
+				clocks = <0x5 0x0>;
+				clock-names = "ad9364_ext_refclk";
+				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
+				adi,digital-interface-tune-skip-mode = <0x0>;
+				adi,pp-tx-swap-enable;
+				adi,pp-rx-swap-enable;
+				adi,rx-frame-pulse-mode-enable;
+				adi,lvds-mode-enable;
+				adi,lvds-bias-mV = <0x96>;
+				adi,lvds-rx-onchip-termination-enable;
+				adi,rx-data-delay = <0x4>;
+				adi,tx-fb-clock-delay = <0x7>;
+				adi,xo-disable-use-ext-refclk-enable;
+				adi,2rx-2tx-mode-enable;
+				adi,frequency-division-duplex-mode-enable;
+				adi,rx-rf-port-input-select = <0x0>;
+				adi,tx-rf-port-input-select = <0x0>;
+				adi,tx-attenuation-mdB = <0x2710>;
+				adi,tx-lo-powerdown-managed-enable;
+				adi,rf-rx-bandwidth-hz = <0x112a880>;
+				adi,rf-tx-bandwidth-hz = <0x112a880>;
+				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
+				adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
+				adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
+				adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
+				adi,gc-rx1-mode = <0x2>;
+				adi,gc-rx2-mode = <0x2>;
+				adi,gc-adc-ovr-sample-size = <0x4>;
+				adi,gc-adc-small-overload-thresh = <0x2f>;
+				adi,gc-adc-large-overload-thresh = <0x3a>;
+				adi,gc-lmt-overload-high-thresh = <0x320>;
+				adi,gc-lmt-overload-low-thresh = <0x2c0>;
+				adi,gc-dec-pow-measurement-duration = <0x2000>;
+				adi,gc-low-power-thresh = <0x18>;
+				adi,mgc-inc-gain-step = <0x2>;
+				adi,mgc-dec-gain-step = <0x2>;
+				adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
+				adi,agc-attack-delay-extra-margin-us = <0x1>;
+				adi,agc-outer-thresh-high = <0x5>;
+				adi,agc-outer-thresh-high-dec-steps = <0x2>;
+				adi,agc-inner-thresh-high = <0xa>;
+				adi,agc-inner-thresh-high-dec-steps = <0x1>;
+				adi,agc-inner-thresh-low = <0xc>;
+				adi,agc-inner-thresh-low-inc-steps = <0x1>;
+				adi,agc-outer-thresh-low = <0x12>;
+				adi,agc-outer-thresh-low-inc-steps = <0x2>;
+				adi,agc-adc-small-overload-exceed-counter = <0xa>;
+				adi,agc-adc-large-overload-exceed-counter = <0xa>;
+				adi,agc-adc-large-overload-inc-steps = <0x2>;
+				adi,agc-lmt-overload-large-exceed-counter = <0xa>;
+				adi,agc-lmt-overload-small-exceed-counter = <0xa>;
+				adi,agc-lmt-overload-large-inc-steps = <0x2>;
+				adi,agc-gain-update-interval-us = <0x3e8>;
+				adi,fagc-dec-pow-measurement-duration = <0x40>;
+				adi,fagc-lp-thresh-increment-steps = <0x1>;
+				adi,fagc-lp-thresh-increment-time = <0x5>;
+				adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
+				adi,fagc-final-overrange-count = <0x3>;
+				adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
+				adi,fagc-lmt-final-settling-steps = <0x1>;
+				adi,fagc-lock-level = <0xa>;
+				adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
+				adi,fagc-lock-level-lmt-gain-increase-enable;
+				adi,fagc-lpf-final-settling-steps = <0x1>;
+				adi,fagc-optimized-gain-offset = <0x5>;
+				adi,fagc-power-measurement-duration-in-state5 = <0x40>;
+				adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
+				adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
+				adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
+				adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
+				adi,fagc-rst-gla-large-adc-overload-enable;
+				adi,fagc-rst-gla-large-lmt-overload-enable;
+				adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
+				adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
+				adi,fagc-state-wait-time-ns = <0x104>;
+				adi,fagc-use-last-lock-level-for-set-gain-enable;
+				adi,rssi-restart-mode = <0x3>;
+				adi,rssi-delay = <0x1>;
+				adi,rssi-wait = <0x1>;
+				adi,rssi-duration = <0x3e8>;
+				adi,ctrl-outs-index = <0x0>;
+				adi,ctrl-outs-enable-mask = <0xff>;
+				adi,temp-sense-measurement-interval-ms = <0x3e8>;
+				adi,temp-sense-offset-signed = <0xce>;
+				adi,temp-sense-periodic-measurement-enable;
+				adi,aux-dac-manual-mode-enable;
+				adi,aux-dac1-default-value-mV = <0x0>;
+				adi,aux-dac1-rx-delay-us = <0x0>;
+				adi,aux-dac1-tx-delay-us = <0x0>;
+				adi,aux-dac2-default-value-mV = <0x0>;
+				adi,aux-dac2-rx-delay-us = <0x0>;
+				adi,aux-dac2-tx-delay-us = <0x0>;
+				en_agc-gpios = <0x6 0x62 0x0>;
+				sync-gpios = <0x6 0x63 0x0>;
+				reset-gpios = <0x6 0x64 0x0>;
+				enable-gpios = <0x6 0x65 0x0>;
+				txnrx-gpios = <0x6 0x66 0x0>;
+				linux,phandle = <0xb>;
+				phandle = <0xb>;
+			};
+		};
+
+		spi@e0007000 {
+			compatible = "xlnx,zynq-spi-r1p6";
+			reg = <0xe0007000 0x1000>;
+			status = "disabled";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x31 0x4>;
+			clocks = <0x2 0x1a 0x2 0x23>;
+			clock-names = "ref_clk", "pclk";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+		};
+
+		spi@e000d000 {
+			clock-names = "ref_clk", "pclk";
+			clocks = <0x2 0xa 0x2 0x2b>;
+			compatible = "xlnx,zynq-qspi-1.0";
+			status = "okay";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x13 0x4>;
+			reg = <0xe000d000 0x1000>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			is-dual = <0x0>;
+			num-cs = <0x1>;
+
+			ps7-qspi@0 {
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+				spi-tx-bus-width = <0x1>;
+				spi-rx-bus-width = <0x4>;
+				compatible = "n25q256a", "jedec,spi-nor";
+				reg = <0x0>;
+				spi-max-frequency = <0x2faf080>;
+
+				partition@qspi-fsbl-uboot {
+					label = "qspi-fsbl-uboot";
+					reg = <0x0 0xe0000>;
+				};
+
+				partition@qspi-uboot-env {
+					label = "qspi-uboot-env";
+					reg = <0xe0000 0x20000>;
+				};
+
+				partition@qspi-linux {
+					label = "qspi-linux";
+					reg = <0x100000 0x500000>;
+				};
+
+				partition@qspi-device-tree {
+					label = "qspi-device-tree";
+					reg = <0x600000 0x20000>;
+				};
+
+				partition@qspi-rootfs {
+					label = "qspi-rootfs";
+					reg = <0x620000 0xce0000>;
+				};
+
+				partition@qspi-bitstream {
+					label = "qspi-bitstream";
+					reg = <0x1300000 0xd00000>;
+				};
+			};
+		};
+
+		memory-controller@e000e000 {
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			status = "disabled";
+			clock-names = "memclk", "aclk";
+			clocks = <0x2 0xb 0x2 0x2c>;
+			compatible = "arm,pl353-smc-r2p1";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x12 0x4>;
+			ranges;
+			reg = <0xe000e000 0x1000>;
+
+			flash@e1000000 {
+				status = "disabled";
+				compatible = "arm,pl353-nand-r2p1";
+				reg = <0xe1000000 0x1000000>;
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+			};
+
+			flash@e2000000 {
+				status = "disabled";
+				compatible = "cfi-flash";
+				reg = <0xe2000000 0x2000000>;
+				#address-cells = <0x1>;
+				#size-cells = <0x1>;
+			};
+		};
+
+		ethernet@e000b000 {
+			compatible = "cdns,zynq-gem", "cdns,gem";
+			reg = <0xe000b000 0x1000>;
+			status = "okay";
+			interrupts = <0x0 0x16 0x4>;
+			clocks = <0x2 0x1e 0x2 0x1e 0x2 0xd>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			phy-handle = <0x7>;
+			phy-mode = "rgmii-id";
+
+			phy@0 {
+				device_type = "ethernet-phy";
+				reg = <0x0>;
+				marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0x0>;
+				linux,phandle = <0x7>;
+				phandle = <0x7>;
+			};
+		};
+
+ 
+		ethernet@e000c000 {
+			compatible = "cdns,zynq-gem", "cdns,gem";
+			reg = <0xe000c000 0x1000>;
+			status = "okay";
+			interrupts = <0x0 0x2d 0x4>;
+			clocks = <0x2 0x1f 0x2 0x1f 0x2 0xe>;
+			clock-names = "pclk", "hclk", "tx_clk";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+			phy-mode = "gmii";
+			phy-handle = <&phy1>;
+
+			phy1: phy@0{
+				reg = <0>; 
+			};	
+		};
+ 
+ 
+		mmc@e0100000 {
+			compatible = "arasan,sdhci-8.9a";
+			status = "okay";
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <0x2 0x15 0x2 0x20>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x18 0x4>;
+			reg = <0xe0100000 0x1000>;
+			disable-wp;
+		};
+
+		mmc@e0101000 {
+			compatible = "arasan,sdhci-8.9a";
+			status = "disabled";
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <0x2 0x16 0x2 0x21>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x2f 0x4>;
+			reg = <0xe0101000 0x1000>;
+		};
+
+		slcr@f8000000 {
+			u-boot,dm-pre-reloc;
+			#address-cells = <0x1>;
+			#size-cells = <0x1>;
+			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
+			reg = <0xf8000000 0x1000>;
+			ranges;
+			linux,phandle = <0x8>;
+			phandle = <0x8>;
+
+			clkc@100 {
+				u-boot,dm-pre-reloc;
+				#clock-cells = <0x1>;
+				compatible = "xlnx,ps7-clkc";
+				fclk-enable = <0xf>;
+				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
+				reg = <0x100 0x100>;
+				ps-clk-frequency = <0x1fca055>;
+				linux,phandle = <0x2>;
+				phandle = <0x2>;
+			};
+
+			rstc@200 {
+				compatible = "xlnx,zynq-reset";
+				reg = <0x200 0x48>;
+				#reset-cells = <0x1>;
+				syscon = <0x8>;
+			};
+
+			pinctrl@700 {
+				compatible = "xlnx,pinctrl-zynq";
+				reg = <0x700 0x200>;
+				syscon = <0x8>;
+			};
+		};
+
+		dmac@f8003000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0xf8003000 0x1000>;
+			interrupt-parent = <0x1>;
+			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
+			interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
+			#dma-cells = <0x1>;
+			#dma-channels = <0x8>;
+			#dma-requests = <0x4>;
+			clocks = <0x2 0x1b>;
+			clock-names = "apb_pclk";
+		};
+
+		devcfg@f8007000 {
+			compatible = "xlnx,zynq-devcfg-1.0";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x8 0x4>;
+			reg = <0xf8007000 0x100>;
+			clocks = <0x2 0xc 0x2 0xf 0x2 0x10 0x2 0x11 0x2 0x12>;
+			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
+			syscon = <0x8>;
+			linux,phandle = <0x4>;
+			phandle = <0x4>;
+		};
+
+		efuse@f800d000 {
+			compatible = "xlnx,zynq-efuse";
+			reg = <0xf800d000 0x20>;
+		};
+
+		timer@f8f00200 {
+			compatible = "arm,cortex-a9-global-timer";
+			reg = <0xf8f00200 0x20>;
+			interrupts = <0x1 0xb 0x301>;
+			interrupt-parent = <0x1>;
+			clocks = <0x2 0x4>;
+		};
+
+		timer@f8001000 {
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
+			compatible = "cdns,ttc";
+			clocks = <0x2 0x6>;
+			reg = <0xf8001000 0x1000>;
+		};
+
+		timer@f8002000 {
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
+			compatible = "cdns,ttc";
+			clocks = <0x2 0x6>;
+			reg = <0xf8002000 0x1000>;
+		};
+
+		timer@f8f00600 {
+			interrupt-parent = <0x1>;
+			interrupts = <0x1 0xd 0x301>;
+			compatible = "arm,cortex-a9-twd-timer";
+			reg = <0xf8f00600 0x20>;
+			clocks = <0x2 0x4>;
+		};
+
+		usb@e0002000 {
+			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
+			status = "okay";
+			clocks = <0x2 0x1c>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x15 0x4>;
+			reg = <0xe0002000 0x1000>;
+			phy_type = "ulpi";
+			dr_mode = "host";
+			xlnx,phy-reset-gpio = <0x6 0x7 0x0>;
+		};
+
+		usb@e0003000 {
+			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
+			status = "disabled";
+			clocks = <0x2 0x1d>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x2c 0x4>;
+			reg = <0xe0003000 0x1000>;
+			phy_type = "ulpi";
+		};
+
+		watchdog@f8005000 {
+			clocks = <0x2 0x2d>;
+			compatible = "cdns,wdt-r1p2";
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x9 0x1>;
+			reg = <0xf8005000 0x1000>;
+			timeout-sec = <0xa>;
+		};
+	};
+
+	aliases {
+		ethernet0 = "/amba/ethernet@e000b000";
+		serial0 = "/amba/serial@e0001000";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	chosen {
+		linux,stdout-path = "/amba@0/uart@E0001000";
+	};
+
+	clocks {
+
+		clock@0 {
+			#clock-cells = <0x0>;
+			compatible = "adjustable-clock";
+			clock-frequency = <0x2625a00>;
+			clock-accuracy = <0x30d40>;
+			clock-output-names = "ad9364_ext_refclk";
+			linux,phandle = <0x5>;
+			phandle = <0x5>;
+		};
+
+		clock@1 {
+			#clock-cells = <0x0>;
+			compatible = "fixed-clock";
+			clock-frequency = <0x16e3600>;
+			clock-output-names = "24MHz";
+			linux,phandle = <0x9>;
+			phandle = <0x9>;
+		};
+	};
+
+	usb-ulpi-gpio-gate@0 {
+		compatible = "gpio-gate-clock";
+		clocks = <0x9>;
+		#clock-cells = <0x0>;
+		enable-gpios = <0x6 0x9 0x1>;
+	};
+
+	fpga-axi@0 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		ranges;
+
+		i2c@41600000 {
+			compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
+			reg = <0x41600000 0x10000>;
+			interrupt-parent = <0x1>;
+			interrupts = <0x0 0x3a 0x4>;
+			clocks = <0x2 0xf>;
+			clock-names = "pclk";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+
+			ad7291@20 {
+				compatible = "adi,ad7291";
+				reg = <0x20>;
+			};
+
+			ad7291-bob@2C {
+				compatible = "adi,ad7291";
+				reg = <0x2c>;
+			};
+
+			eeprom@50 {
+				compatible = "at24,24c32";
+				reg = <0x50>;
+			};
+		};
+
+		// dma@7c400000 {
+		// 	compatible = "adi,axi-dmac-1.00.a";
+		// 	reg = <0x7c400000 0x10000>;
+		// 	#dma-cells = <0x1>;
+		// 	interrupts = <0x0 0x39 0x0>;
+		// 	clocks = <0x2 0x10>;
+		// 	linux,phandle = <0xa>;
+		// 	phandle = <0xa>;
+
+		// 	adi,channels {
+		// 		#size-cells = <0x0>;
+		// 		#address-cells = <0x1>;
+
+		// 		dma-channel@0 {
+		// 			reg = <0x0>;
+		// 			adi,source-bus-width = <0x40>;
+		// 			adi,source-bus-type = <0x2>;
+		// 			adi,destination-bus-width = <0x40>;
+		// 			adi,destination-bus-type = <0x0>;
+		// 		};
+		// 	};
+		// };
+
+		// dma@7c420000 {
+		// 	compatible = "adi,axi-dmac-1.00.a";
+		// 	reg = <0x7c420000 0x10000>;
+		// 	#dma-cells = <0x1>;
+		// 	interrupts = <0x0 0x38 0x0>;
+		// 	clocks = <0x2 0x10>;
+		// 	linux,phandle = <0xc>;
+		// 	phandle = <0xc>;
+
+		// 	adi,channels {
+		// 		#size-cells = <0x0>;
+		// 		#address-cells = <0x1>;
+
+		// 		dma-channel@0 {
+		// 			reg = <0x0>;
+		// 			adi,source-bus-width = <0x40>;
+		// 			adi,source-bus-type = <0x0>;
+		// 			adi,destination-bus-width = <0x40>;
+		// 			adi,destination-bus-type = <0x2>;
+		// 		};
+		// 	};
+		// };
+
+		sdr: sdr {
+			compatible ="sdr,sdr";
+			dmas = <&rx_dma 1
+					&tx_dma 0>;
+			dma-names = "rx_dma_s2mm", "tx_dma_mm2s";
+			interrupt-names = "not_valid_anymore", "rx_pkt_intr", "tx_itrpt";
+			interrupt-parent = <1>;
+			interrupts = <0 29 1 0 30 1 0 33 1 0 34 1>;
+		} ;
+
+		axidmatest_1: axidmatest@1 {
+			compatible ="xlnx,axi-dma-test-1.00.a";
+			dmas = <&rx_dma 0
+				&rx_dma 1>;
+			dma-names = "axidma0", "axidma1";
+		} ;
+
+		tx_dma: dma@80400000 {
+			#dma-cells = <1>;
+			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
+			clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
+			compatible = "xlnx,axi-dma-1.00.a";
+			interrupt-names = "mm2s_introut", "s2mm_introut";
+			interrupt-parent = <1>;
+			interrupts = <0 35 4 0 36 4>;
+			reg = <0x80400000 0x10000>;
+			xlnx,addrwidth = <0x20>;
+			xlnx,include-sg ;
+			xlnx,sg-length-width = <0xe>;
+			dma-channel@80400000 {
+				compatible = "xlnx,axi-dma-mm2s-channel";
+				dma-channels = <0x1>;
+				interrupts = <0 35 4>;
+				xlnx,datawidth = <0x40>;
+				xlnx,device-id = <0x0>;
+			};
+			dma-channel@80400030 {
+				compatible = "xlnx,axi-dma-s2mm-channel";
+				dma-channels = <0x1>;
+				interrupts = <0 36 4>;
+				xlnx,datawidth = <0x40>;
+				xlnx,device-id = <0x0>;
+			};
+		};
+		
+		rx_dma: dma@80410000 {
+			#dma-cells = <1>;
+			clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
+			clocks = <0x2 0x11>, <0x2 0x11>, <0x2 0x11>, <0x2 0x11>;
+			compatible = "xlnx,axi-dma-1.00.a";
+			//dma-coherent ;
+			interrupt-names = "mm2s_introut", "s2mm_introut";
+			interrupt-parent = <1>;
+			interrupts = <0 31 4 0 32 4>;
+			reg = <0x80410000 0x10000>;
+			xlnx,addrwidth = <0x20>;
+			xlnx,include-sg ;
+			xlnx,sg-length-width = <0xe>;
+			dma-channel@80410000 {
+				compatible = "xlnx,axi-dma-mm2s-channel";
+				dma-channels = <0x1>;
+				interrupts = <0 31 4>;
+				xlnx,datawidth = <0x40>;
+				xlnx,device-id = <0x1>;
+			};
+			dma-channel@80410030 {
+				compatible = "xlnx,axi-dma-s2mm-channel";
+				dma-channels = <0x1>;
+				interrupts = <0 32 4>;
+				xlnx,datawidth = <0x40>;
+				xlnx,device-id = <0x1>;
+			};
+		};
+
+		tx_intf_0: tx_intf@83c00000 {
+			clock-names = "s00_axi_aclk", "s00_axis_aclk";//, "s01_axis_aclk", "m00_axis_aclk";
+			clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>, <0x2 0x11>;
+			compatible = "sdr,tx_intf";
+			interrupt-names = "tx_itrpt";
+			interrupt-parent = <1>;
+			interrupts = <0 34 1>;
+			reg = <0x83c00000 0x10000>;
+			xlnx,s00-axi-addr-width = <0x7>;
+			xlnx,s00-axi-data-width = <0x20>;
+		};
+
+		rx_intf_0: rx_intf@83c20000 {
+			clock-names = "s00_axi_aclk", "m00_axis_aclk";//, "s00_axis_aclk";
+			clocks = <0x2 0x11>, <0x2 0x11>;//, <0x2 0x11>;
+			compatible = "sdr,rx_intf";
+			interrupt-names = "not_valid_anymore", "rx_pkt_intr";
+			interrupt-parent = <1>;
+			interrupts = <0 29 1 0 30 1>;
+			reg = <0x83c20000 0x10000>;
+			xlnx,s00-axi-addr-width = <0x7>;
+			xlnx,s00-axi-data-width = <0x20>;
+		};
+
+		openofdm_tx_0: openofdm_tx@83c10000 {
+			clock-names = "clk";
+			clocks = <0x2 0x11>;
+			compatible = "sdr,openofdm_tx";
+			reg = <0x83c10000 0x10000>;
+		};
+
+		openofdm_rx_0: openofdm_rx@83c30000 {
+			clock-names = "clk";
+			clocks = <0x2 0x11>;
+			compatible = "sdr,openofdm_rx";
+			reg = <0x83c30000 0x10000>;
+		};
+
+		xpu_0: xpu@83c40000 {
+			clock-names = "s00_axi_aclk";
+			clocks = <0x2 0x11>;
+			compatible = "sdr,xpu";
+			reg = <0x83c40000 0x10000>;
+		};
+
+		side_ch_0: side_ch@83c50000 {
+			clock-names = "s00_axi_aclk";
+			clocks = <0x2 0x11>;
+			compatible = "sdr,side_ch";
+			reg = <0x83c50000 0x10000>;
+			dmas = <&rx_dma 0
+					&tx_dma 1>;
+			dma-names = "rx_dma_mm2s", "tx_dma_s2mm";
+		};
+
+		cf-ad9361-lpc@79020000 {
+			compatible = "adi,axi-ad9361-6.00.a";
+			reg = <0x79020000 0x6000>;
+			// dmas = <0xa 0x0>;
+			// dma-names = "rx";
+			spibus-connected = <0xb>;
+		};
+
+		cf-ad9361-dds-core-lpc@79024000 {
+			compatible = "adi,axi-ad9361-dds-6.00.a";
+			reg = <0x79024000 0x1000>;
+			clocks = <0xb 0xd>;
+			clock-names = "sampl_clk";
+			// dmas = <0xc 0x0>;
+			// dma-names = "tx";
+		};
+
+		mwipcore@43c00000 {
+			compatible = "mathworks,mwipcore-axi4lite-v1.00";
+			reg = <0x43c00000 0xffff>;
+		};
+
+		/*axi-sysid-0@45000000 {
+			compatible = "adi,axi-sysid-1.00.a";
+			reg = <0x45000000 0x10000>;
+		};*/
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0 {
+			label = "led0:green";
+			gpios = <0x6 0xF 0>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+//	gpio_keys {
+//		compatible = "gpio-keys";
+//		#address-cells = <0x1>;
+//		#size-cells = <0x0>;
+//		autorepeat;
+//
+//		sw1 {
+//			label = "SW1";
+//			linux,input-type = <0x5>;
+//			linux,code = <0x3>;
+//			gpios = <0x6 0xE 0x0>;
+//		};
+//	};
+};

kernel_boot/boards/sdrpi/notes.md

@@ -0,0 +1,15 @@
+# sdrpi for openwifi
+
+## Introduction
+[SDRPi](https://github.com/hexsdr/) is a smart and powerful SDR platform according Raspberry Pi size,which is based on [xilinx zynq7020](https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html) and [adi ad936x](https://www.analog.com/en/products/ad9361.html). 
+
+
+
+Hareware feature is : ZYNQ 7Z020CLG400 ,1GB DDR3 memory fo PS, 1G Ethernet RJ45 for PS,1G Ethernet RJ45 for PL, USB OTG(act as USB host or USB SLAVE ), dual USB uarts for PS and PL,on board USB to JTAG debuger,TF card , bootable QSPI FLASH and also external 27 IO pins from PL bank in 3.3v vatage with enable this board connect to other boards or modules. AD9361 RF design is based FMCOMMS3 with RF amplifier additionally.It also has a Ublox m8t GPS module and 40MHZ VCXO.
+
+
+
+
+It could be used as a traditional SDR device such as PlutoSDR or FMCOMMS2/3/4 with Xilinx evaluation board, and it also be used as hardware platform to support openwifi.
+
+

kernel_boot/build_boot_bin.sh

@@ -1,60 +1,38 @@
 #!/bin/bash
-
-# Author: Xianjun Jiao
-# SPDX-FileCopyrightText: 2019 UGent
-# SPDX-License-Identifier: AGPL-3.0-or-later
-# https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynq_2014r2
-
-if [ "$#" -ne 2 ]; then
-    echo "You must enter the \$OPENWIFI_HW_DIR \$BOARD_NAME as argument"
-    echo "BOARD_NAME Like: antsdr adrv9364z7020 adrv9361z7035 zc706_fmcs2 zed_fmcs2 zc702_fmcs2 zcu102_fmcs2 zcu102_9371"
-    exit 1
-fi
-
-OPENWIFI_HW_DIR=$1
-BOARD_NAME=$2
-
-if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then
-    echo "\$BOARD_NAME is not correct. Please check!"
-    exit 1
-else
-    echo "\$BOARD_NAME is found!"
-fi
-
 set -ex
 
-HDF_FILE=$OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf
-UBOOT_FILE=./boards/$BOARD_NAME/u-boot.elf
-BUILD_DIR=./boards/$BOARD_NAME/build_boot_bin
-OUTPUT_DIR=./boards/$BOARD_NAME/output_boot_bin
+HDF_FILE=$1
+UBOOT_FILE=$2
+BUILD_DIR=build_boot_bin
+OUTPUT_DIR=output_boot_bin
 
-# usage () {
-# 	echo usage: $0 system_top.hdf u-boot.elf [output-archive]
-# 	exit 1
-# }
+usage () {
+	echo "usage: $0 system_top.<hdf/xsa> u-boot.elf [output-archive]"
+	exit 1
+}
 
-# depends () {
-# 	echo Xilinx $1 must be installed and in your PATH
-# 	echo try: source /opt/Xilinx/Vivado/201x.x/settings64.sh
-# 	exit 1
-# }
+depends () {
+	echo Xilinx $1 must be installed and in your PATH
+	echo try: source /opt/Xilinx/Vivado/201x.x/settings64.sh
+	exit 1
+}
 
 ### Check command line parameters
-echo $HDF_FILE | grep -q ".hdf" || usage
-echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" || usage
+echo $HDF_FILE | grep -q ".hdf\|.xsa" || usage
+echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" -e "u-boot"|| usage
 
 if [ ! -f $HDF_FILE ]; then
-    echo $HDF_FILE: File not found!
-    usage
+	echo $HDF_FILE: File not found!
+	usage
 fi
 
 if [ ! -f $UBOOT_FILE ]; then
-    echo $UBOOT_FILE: File not found!
-    usage
+	echo $UBOOT_FILE: File not found!
+	usage
 fi
 
-### Check for required Xilinx tools
-command -v xsdk >/dev/null 2>&1 || depends xsdk
+### Check for required Xilinx tools (xcst is equivalent with 'xsdk -batch')
+command -v xsct >/dev/null 2>&1 || depends xsct
 command -v bootgen >/dev/null 2>&1 || depends bootgen
 
 rm -Rf $BUILD_DIR $OUTPUT_DIR
@@ -65,14 +43,26 @@ cp $HDF_FILE $BUILD_DIR/
 cp $UBOOT_FILE $OUTPUT_DIR/u-boot.elf
 cp $HDF_FILE $OUTPUT_DIR/
 
-### Create create_fsbl_project.tcl file used by xsdk to create the fsbl
+### Create create_fsbl_project.tcl file used by xsct to create the fsbl.
 echo "hsi open_hw_design `basename $HDF_FILE`" > $BUILD_DIR/create_fsbl_project.tcl
 echo 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl
-echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl
-echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl
-echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl
-echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl
-echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl
+### The fsbl creating flow is different starting with 2019.2 Xilinx version
+if [[ "$HDF_FILE" =~ ".hdf" ]];then
+	echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl
+	echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl
+	echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl
+	echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl
+	echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl
+
+	FSBL_PATH="$BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf"
+	SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw_0/system_top.bit"
+else
+	echo 'platform create -name hw0 -hw system_top.xsa -os standalone -out ./build/sdk -proc $cpu_name' >> $BUILD_DIR/create_fsbl_project.tcl
+	echo 'platform generate' >> $BUILD_DIR/create_fsbl_project.tcl
+
+	FSBL_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/fsbl.elf"
+	SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw0/hw/system_top.bit"
+fi
 
 ### Create zynq.bif file used by bootgen
 echo 'the_ROM_image:' > $OUTPUT_DIR/zynq.bif
@@ -85,12 +75,12 @@ echo '}' >> $OUTPUT_DIR/zynq.bif
 ### Build fsbl.elf
 (
 	cd $BUILD_DIR
-	xsdk -batch -source create_fsbl_project.tcl
+	xsct create_fsbl_project.tcl
 )
 
 ### Copy fsbl and system_top.bit into the output folder
-cp $BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf $OUTPUT_DIR/fsbl.elf
-cp $BUILD_DIR/build/sdk/hw_0/system_top.bit $OUTPUT_DIR/system_top.bit
+cp $FSBL_PATH $OUTPUT_DIR/fsbl.elf
+cp $SYSTEM_TOP_BIT_PATH $OUTPUT_DIR/system_top.bit
 
 ### Build BOOT.BIN
 (
@@ -98,12 +88,7 @@ cp $BUILD_DIR/build/sdk/hw_0/system_top.bit $OUTPUT_DIR/system_top.bit
 	bootgen -arch zynq -image zynq.bif -o BOOT.BIN -w
 )
 
-### clean up BUILD_DIR and copy ILA definition together with .bit into OUTPUT_DIR
-(
-	rm $BUILD_DIR -rf
-)
-
-# ### Optionally tar.gz the entire output folder with the name given in argument 3
-# if [ ${#3} -ne 0 ]; then
-# 	tar czvf $3.tar.gz $OUTPUT_DIR
-# fi
+### Optionally tar.gz the entire output folder with the name given in argument 3
+if [ ${#3} -ne 0 ]; then
+	tar czvf $3.tar.gz $OUTPUT_DIR
+fi

kernel_boot/build_zynqmp_boot_bin.sh

@@ -1,10 +1,4 @@
 #!/bin/bash
-
-# Author: Xianjun Jiao
-# SPDX-FileCopyrightText: 2019 UGent
-# SPDX-License-Identifier: AGPL-3.0-or-later
-# https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynqmp
-
 set -ex
 
 HDF_FILE=$1
@@ -14,7 +8,7 @@ BUILD_DIR=build_boot_bin
 OUTPUT_DIR=output_boot_bin
 
 usage () {
-	echo "usage: $0 system_top.hdf u-boot.elf  (download | bl31.elf | <path-to-arm-trusted-firmware-source>) [output-archive]"
+	echo "usage: $0 system_top.<hdf/xsa> u-boot.elf  (download | bl31.elf | <path-to-arm-trusted-firmware-source>) [output-archive]"
 	exit 1
 }
 
@@ -25,12 +19,14 @@ depends () {
 }
 
 ### Check command line parameters
-echo $HDF_FILE | grep -q ".hdf" || usage
-echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" || usage
+echo $HDF_FILE | grep -q ".hdf\|.xsa" || usage
+echo $UBOOT_FILE | grep -q -e ".elf" -e "uboot" -e "u-boot" || usage
 
 if [ ! -f $HDF_FILE ]; then
-    echo $HDF_FILE: File not found!
-    usage
+	echo $HDF_FILE: File not found!
+	usage
+else
+	if [[ "$HDF_FILE" =~ ".hdf" ]]; then TOOL="xsdk";else TOOL="vitis";fi
 fi
 
 if [ ! -f $UBOOT_FILE ]; then
@@ -38,10 +34,10 @@ if [ ! -f $UBOOT_FILE ]; then
     usage
 fi
 
-### Check for required Xilinx tools
-command -v xsdk >/dev/null 2>&1 || depends xsdk
+### Check for required Xilinx tools (starting with 2019.2 there is no hsi anymore)
+command -v xsct >/dev/null 2>&1 || depends xsct
 command -v bootgen >/dev/null 2>&1 || depends bootgen
-command -v hsi >/dev/null 2>&1 || depends hsi
+if [[ "$HDF_FILE" =~ ".hdf" ]];then (command -v hsi >/dev/null 2>&1 || depends hsi);fi
 
 rm -Rf $BUILD_DIR $OUTPUT_DIR
 mkdir -p $OUTPUT_DIR
@@ -51,13 +47,22 @@ mkdir -p $BUILD_DIR
 # 2018.1 use df4a7e97d57494c7d79de51b1e0e450d982cea98
 # 2018.2 use 93a69a5a3bc318027da4af5911124537f4907642
 # 2018.3 use 08560c36ea5b6f48b962cb4bd9a79b35bb3d95ce
+# 2019.3 use 713dace94b259845fd8eede11061fbd8f039011e
+# 2020.1 use bf72e4d494f3be10665b94c0e88766eb2096ef71
+# 2021.2 use 799131a3b063f6f24f87baa74e46906c076aebcd
 
-hsi_ver=$(hsi -version | head -1 | cut -d' ' -f2)
-if [ -z "$hsi_ver" ] ; then
+tool_version=$($TOOL -version | sed -n '3p' | cut -d' ' -f 3)
+if [ -z "$tool_version" ] ; then
 	echo "Could not determine Vivado version"
 	exit 1
 fi
-atf_version=xilinx-$hsi_ver
+atf_version=xilinx-$tool_version
+
+if [[ "$atf_version" == "xilinx-v2021.1" ]];then atf_version="xlnx_rebase_v2.4_2021.1";fi
+if [[ "$atf_version" == "xilinx-v2021.1.1" ]];then atf_version="xlnx_rebase_v2.4_2021.1_update1";fi
+if [[ "$atf_version" == "xilinx-v2021.2" ]];then atf_version="xlnx-v2021.2";fi
+
+if [[ "$4" == "uart1" ]];then console="cadence1";else console="cadence0";fi
 
 ### Check if ATF_FILE is .elf or path to arm-trusted-firmware
 if [ "$ATF_FILE" != "" ] && [ -d $ATF_FILE ]; then
@@ -66,7 +71,7 @@ if [ "$ATF_FILE" != "" ] && [ -d $ATF_FILE ]; then
 	cd $ATF_FILE
 	make distclean
 	git checkout $atf_version
-	make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1
+	make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_CONSOLE=$console
 )
 	cp $ATF_FILE/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf
 elif [ "$ATF_FILE" == "download" ]; then
@@ -76,7 +81,7 @@ elif [ "$ATF_FILE" == "download" ]; then
 	git clone https://github.com/Xilinx/arm-trusted-firmware.git
 	cd arm-trusted-firmware
 	git checkout $atf_version
-	make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1
+	make CROSS_COMPILE=aarch64-linux-gnu- PLAT=zynqmp RESET_TO_BL31=1 ZYNQMP_CONSOLE=$console
 )
 	cp $BUILD_DIR/arm-trusted-firmware/build/zynqmp/release/bl31/bl31.elf $OUTPUT_DIR/bl31.elf
 else
@@ -88,45 +93,52 @@ else
 	cp $ATF_FILE $OUTPUT_DIR/bl31.elf
 fi
 
-cp $HDF_FILE $BUILD_DIR/
-cp $UBOOT_FILE $OUTPUT_DIR/u-boot.elf
-cp $HDF_FILE $OUTPUT_DIR/
+cp "$HDF_FILE" "$BUILD_DIR/"
+cp "$UBOOT_FILE" "$OUTPUT_DIR/u-boot.elf"
+cp "$HDF_FILE" "$OUTPUT_DIR/"
 
-# get the tools version (e.g., v2018.3)
-tool_version=$(hsi -version)
-tool_version=${tool_version#hsi\ }
-tool_version=${tool_version%\ (64-bit)*}
-
-# Work-arownd for MPSoC ZCU102 and ZCU106 Evaluation Kits - DDR4 SODIMM change
+# Work-around for MPSoC ZCU102 and ZCU106 Evaluation Kits - DDR4 SODIMM change
 # (https://www.xilinx.com/support/answers/71961.html)
 if [ $tool_version == "v2018.3" ];then
 (
-#	wget https://www.xilinx.com/Attachment/72113-files.zip -P $BUILD_DIR
-	cp -P 72113-files.zip $BUILD_DIR
+	wget https://www.xilinx.com/Attachment/72113-files.zip -P $BUILD_DIR
 	unzip $BUILD_DIR/72113-files.zip -d  $BUILD_DIR
 )
 fi
 
-### Create create_fsbl_project.tcl file used by xsdk to create the fsbl
+### Create create_fsbl_project.tcl file used by xsct to create the fsbl.
 echo "hsi open_hw_design `basename $HDF_FILE`" > $BUILD_DIR/create_fsbl_project.tcl
 echo 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]' >> $BUILD_DIR/create_fsbl_project.tcl
-echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl
-echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl
-echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq MP FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl
-echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl
-if [ $tool_version == "v2018.3" ];then
-(
-	echo "file copy -force xfsbl_ddr_init.c ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
-	echo "file copy -force xfsbl_hooks.c    ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
-	echo "file copy -force xfsbl_hooks.h    ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
-)
-fi
-echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl
+### The fsbl creating flow is different starting with 2019.2 Xilinx version
+if [[ "$HDF_FILE" =~ ".hdf" ]];then
+        echo 'sdk setws ./build/sdk' >> $BUILD_DIR/create_fsbl_project.tcl
+        echo "sdk createhw -name hw_0 -hwspec `basename $HDF_FILE`" >> $BUILD_DIR/create_fsbl_project.tcl
+        echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq MP FSBL}' >> $BUILD_DIR/create_fsbl_project.tcl
+        echo 'configapp -app fsbl build-config release' >> $BUILD_DIR/create_fsbl_project.tcl
+	if [ $tool_version == "v2018.3" ];then
+		echo "file copy -force xfsbl_ddr_init.c ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
+		echo "file copy -force xfsbl_hooks.c    ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
+		echo "file copy -force xfsbl_hooks.h    ./build/sdk/fsbl/src" >> $BUILD_DIR/create_fsbl_project.tcl
+	fi
+	echo 'sdk projects -build -type all' >> $BUILD_DIR/create_fsbl_project.tcl
 
-### Create create_pmufw_project.tcl
-echo "set hwdsgn [open_hw_design `basename $HDF_FILE`]" > $BUILD_DIR/create_pmufw_project.tcl
-echo 'generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -sw pmufw -dir pmufw' >> $BUILD_DIR/create_pmufw_project.tcl
-echo 'quit' >> $BUILD_DIR/create_pmufw_project.tcl
+	### Create create_pmufw_project.tcl
+	echo "set hwdsgn [open_hw_design `basename $HDF_FILE`]" > $BUILD_DIR/create_pmufw_project.tcl
+	echo 'generate_app -hw $hwdsgn -os standalone -proc psu_pmu_0 -app zynqmp_pmufw -compile -sw pmufw -dir pmufw' >> $BUILD_DIR/create_pmufw_project.tcl
+	echo 'quit' >> $BUILD_DIR/create_pmufw_project.tcl
+
+        FSBL_PATH="$BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf"
+        SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw_0/system_top.bit"
+	PMUFW_PATH="$BUILD_DIR/pmufw/executable.elf"
+else
+	# Flow got changed starting with 2019.2 version (when Vitis replaced SDK) and pmufw is generated automatically with fsbl
+        echo 'platform create -name hw0 -hw system_top.xsa -os standalone -out ./build/sdk -proc $cpu_name' >> $BUILD_DIR/create_fsbl_project.tcl
+        echo 'platform generate' >> $BUILD_DIR/create_fsbl_project.tcl
+
+        FSBL_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/fsbl.elf"
+        SYSTEM_TOP_BIT_PATH="$BUILD_DIR/build/sdk/hw0/hw/system_top.bit"
+	PMUFW_PATH="$BUILD_DIR/build/sdk/hw0/export/hw0/sw/hw0/boot/pmufw.elf"
+fi
 
 ### Create zynq.bif file used by bootgen
 echo "the_ROM_image:" > $OUTPUT_DIR/zynq.bif
@@ -138,22 +150,22 @@ echo "[destination_cpu=a53-0,exception_level=el-3,trustzone] bl31.elf" >> $OUTPU
 echo "[destination_cpu=a53-0, exception_level=el-2] u-boot.elf" >> $OUTPUT_DIR/zynq.bif
 echo "}" >> $OUTPUT_DIR/zynq.bif
 
-
 ### Build fsbl.elf & pmufw.elf
 (
 	cd $BUILD_DIR
-	xsdk -batch -source create_fsbl_project.tcl
-	hsi -source create_pmufw_project.tcl
-	### There was a bug in some vivado version where they build would fail -> check CC_FLAGS
-	grep "CC_FLAGS :=" pmufw/Makefile | grep -e "-Os" || sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile
-	cd pmufw
-	make
+	xsct create_fsbl_project.tcl
+	if [[ "$HDF_FILE" =~ ".hdf" ]];then
+		hsi -source create_pmufw_project.tcl
+		### There was a bug in some vivado version where they build would fail -> check CC_FLAGS
+		grep "CC_FLAGS :=" pmufw/Makefile | grep -e "-Os" || sed -i '/-mxl-soft-mul/ s/$/ -Os -flto -ffat-lto-objects/' pmufw/Makefile
+		cd pmufw
+		make
+	fi
 )
-
 ### Copy fsbl and system_top.bit into the output folder
-cp $BUILD_DIR/build/sdk/fsbl/Release/fsbl.elf $OUTPUT_DIR/fsbl.elf
-cp $BUILD_DIR/build/sdk/hw_0/system_top.bit $OUTPUT_DIR/system_top.bit
-cp $BUILD_DIR/pmufw/executable.elf $OUTPUT_DIR/pmufw.elf
+cp "$FSBL_PATH" "$OUTPUT_DIR/fsbl.elf"
+cp "$SYSTEM_TOP_BIT_PATH" "$OUTPUT_DIR/system_top.bit"
+cp "$PMUFW_PATH" "$OUTPUT_DIR/pmufw.elf"
 
 ### Build BOOT.BIN
 (
@@ -161,7 +173,11 @@ cp $BUILD_DIR/pmufw/executable.elf $OUTPUT_DIR/pmufw.elf
 	bootgen -arch zynqmp -image zynq.bif -o BOOT.BIN -w
 )
 
-### Optionally tar.gz the entire output folder with the name given in argument 3
-if [ ${#4} -ne 0 ]; then
-	tar czvf $4.tar.gz $OUTPUT_DIR
+### Optionally tar.gz the entire output folder with the name given in argument 4/5
+if [[ ( $4 == "uart"* && ${#5} -ne 0 ) ]]; then
+	tar czvf $5.tar.gz $OUTPUT_DIR
+fi
+
+if [[ ( ${#4} -ne 0 && $4 != "uart"* && ${#5} -eq 0 ) ]]; then
+        tar czvf $4.tar.gz $OUTPUT_DIR
 fi

kernel_boot/kernel_patch_readme.md

@@ -0,0 +1,6 @@
+axi_hdmi_crtc.patch to avoid axi hdmi compiling error after enable Xilinx axi dma.
+
+ad9361.patch to expose some APIs for openwifi driver.
+
+ad9361_conv.patch to avoid 61.44Msps lvds interface self timing calibration for some low-end/bad hardware (sometimes difficult).
+

user_space/arbitrary_iq_gen/single_carrier_gen.m

@@ -1,4 +1,6 @@
-% xianjun.jiao@imec.be
+% Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com)
+% SPDX-FileCopyrightText: 2023 UGent
+% SPDX-License-Identifier: AGPL-3.0-or-later
 
 function single_carrier_gen(carrier_freq, num_iq)
 if exist('carrier_freq', 'var')==0 || isempty(carrier_freq)

user_space/boot_bin_gen.sh

@@ -5,18 +5,18 @@
 # SPDX-License-Identifier: AGPL-3.0-or-later
 
 if [ "$#" -ne 3 ]; then
-    echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME"
+    echo "You must enter exactly 3 arguments: \$XILINX_DIR \$BOARD_NAME DIR_TO_system_top.xsa"
     exit 1
 fi
 
-OPENWIFI_HW_DIR=$1
-XILINX_DIR=$2
-BOARD_NAME=$3
+XILINX_DIR=$1
+BOARD_NAME=$2
+XSA_FILE=$3
 
 OPENWIFI_DIR=$(pwd)/../
 
 echo OPENWIFI_DIR $OPENWIFI_DIR
-echo OPENWIFI_HW_DIR $OPENWIFI_HW_DIR
+echo XSA_FILE $XSA_FILE
 
 if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
     echo "\$OPENWIFI_DIR is found!"
@@ -25,24 +25,24 @@ else
     exit 1
 fi
 
-if [ -d "$XILINX_DIR/SDK" ]; then
+if [ -d "$XILINX_DIR/Vitis" ]; then
     echo "\$XILINX_DIR is found!"
 else
     echo "\$XILINX_DIR is not correct. Please check!"
     exit 1
 fi
 
-if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then
-    echo "\$BOARD_NAME is not correct. Please check!"
-    exit 1
-else
-    echo "\$BOARD_NAME is found!"
-fi
+# if [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ]; then
+#     echo "\$BOARD_NAME is not correct. Please check!"
+#     exit 1
+# else
+#     echo "\$BOARD_NAME is found!"
+# fi
 
-if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then
-    echo "\$OPENWIFI_HW_DIR is found!"
+if [ -f "$XSA_FILE" ]; then
+    echo "\$XSA_FILE is found!"
 else
-    echo "\$OPENWIFI_HW_DIR is not correct. Please check!"
+    echo "\$XSA_FILE is not found. Please check!"
     exit 1
 fi
 
@@ -50,11 +50,32 @@ home_dir=$(pwd)
 
 set -ex
 
-# check if user entered the right path to SDK
-source $XILINX_DIR/SDK/2018.3/settings64.sh
+source $XILINX_DIR/Vitis/2021.1/settings64.sh
 
 cd $OPENWIFI_DIR/kernel_boot
 
-./build_boot_bin.sh $OPENWIFI_HW_DIR $BOARD_NAME
+if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then
+  ./build_zynqmp_boot_bin.sh $XSA_FILE boards/$BOARD_NAME/u-boot_xilinx_zynqmp_zcu102_revA.elf boards/$BOARD_NAME/bl31.elf
+  ARCH="zynqmp"
+  ARCH_BIT=64
+elif [ "$BOARD_NAME" == "antsdr" ] || [ "$BOARD_NAME" == "antsdr_e200" ] || [ "$BOARD_NAME" == "e310v2" ] || [ "$BOARD_NAME" == "sdrpi" ] || [ "$BOARD_NAME" == "neptunesdr" ] || [ "$BOARD_NAME" == "zc706_fmcs2" ] || [ "$BOARD_NAME" == "zc702_fmcs2" ] || [ "$BOARD_NAME" == "zed_fmcs2" ] || [ "$BOARD_NAME" == "adrv9361z7035" ] || [ "$BOARD_NAME" == "adrv9364z7020" ]; then
+  ./build_boot_bin.sh $XSA_FILE boards/$BOARD_NAME/u-boot.elf
+  ARCH="zynq"
+  ARCH_BIT=32
+else
+  echo "\$BOARD_NAME is not correct. Please check!"
+  cd $home_dir
+  exit 1
+fi
+
+rm -rf build_boot_bin
+rm -rf boards/$BOARD_NAME/output_boot_bin
+mv output_boot_bin boards/$BOARD_NAME/
 
 cd $home_dir
+
+# generate system_top.bit.bin for FPGA dynamic loading
+unzip -o $XSA_FILE
+rm -rf ./system_top.bit.bin
+bootgen -image system_top.bif -arch $ARCH -process_bitstream bin -w
+ls ./system_top.bit.bin -al

user_space/boot_bin_gen_zynqmp.sh

@@ -1,64 +0,0 @@
-#!/bin/bash
-
-# Author: Xianjun Jiao
-# SPDX-FileCopyrightText: 2019 UGent
-# SPDX-License-Identifier: AGPL-3.0-or-later
-
-if [ "$#" -ne 3 ]; then
-    echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_DIR \$XILINX_DIR \$BOARD_NAME"
-    exit 1
-fi
-
-OPENWIFI_HW_DIR=$1
-XILINX_DIR=$2
-BOARD_NAME=$3
-
-OPENWIFI_DIR=$(pwd)/../
-
-echo OPENWIFI_DIR $OPENWIFI_DIR
-echo OPENWIFI_HW_DIR $OPENWIFI_HW_DIR
-
-if [ -f "$OPENWIFI_DIR/LICENSE" ]; then
-    echo "\$OPENWIFI_DIR is found!"
-else
-    echo "\$OPENWIFI_DIR is not correct. Please check!"
-    exit 1
-fi
-
-if [ -d "$XILINX_DIR/SDK" ]; then
-    echo "\$XILINX_DIR is found!"
-else
-    echo "\$XILINX_DIR is not correct. Please check!"
-    exit 1
-fi
-
-if [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then
-    echo "\$BOARD_NAME is not correct. Please check!"
-    exit 1
-else
-    echo "\$BOARD_NAME is found!"
-fi
-
-if [ -d "$OPENWIFI_HW_DIR/boards/$BOARD_NAME" ]; then
-    echo "\$OPENWIFI_HW_DIR is found!"
-else
-    echo "\$OPENWIFI_HW_DIR is not correct. Please check!"
-    exit 1
-fi
-
-home_dir=$(pwd)
-
-set -ex
-
-# check if user entered the right path to SDK
-source $XILINX_DIR/SDK/2018.3/settings64.sh
-
-cd $OPENWIFI_DIR/kernel_boot
-
-./build_zynqmp_boot_bin.sh $OPENWIFI_HW_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf boards/$BOARD_NAME/u-boot-zcu.elf boards/$BOARD_NAME/bl31.elf
-
-rm -rf build_boot_bin
-rm -rf boards/$BOARD_NAME/output_boot_bin
-mv output_boot_bin boards/$BOARD_NAME/
-
-cd $home_dir

user_space/dhcpd.conf

@@ -13,7 +13,7 @@
 ddns-update-style none;
 
 # option definitions common to all supported networks...
-option domain-name "orca-project.eu";
+# option domain-name "orca-project.eu";
 #option domain-name-servers ns1.example.org, ns2.example.org;
 
 default-lease-time 600;

user_space/drv_and_fpga_package_gen.sh

@@ -0,0 +1,107 @@
+  
+#!/bin/bash
+
+# Author: Xianjun Jiao
+# SPDX-FileCopyrightText: 2022 UGent
+# SPDX-License-Identifier: AGPL-3.0-or-later
+
+if [ "$#" -ne 3 ]; then
+    echo "You have input $# arguments."
+    echo "You must enter exactly 3 arguments: \$OPENWIFI_HW_IMG_DIR \$XILINX_DIR \$BOARD_NAME"
+    exit 1
+fi
+
+OPENWIFI_HW_IMG_DIR=$1
+XILINX_DIR=$2
+BOARD_NAME=$3
+
+if [ -d "$XILINX_DIR/Vitis" ]; then
+    echo "\$XILINX_DIR is found!"
+else
+    echo "\$XILINX_DIR is not correct. Please check!"
+    exit 1
+fi
+
+if [ "$BOARD_NAME" != "neptunesdr" ] && [ "$BOARD_NAME" != "antsdr" ] && [ "$BOARD_NAME" != "antsdr_e200" ] && [ "$BOARD_NAME" != "e310v2" ]  && [ "$BOARD_NAME" != "sdrpi" ] && [ "$BOARD_NAME" != "zc706_fmcs2" ] && [ "$BOARD_NAME" != "zc702_fmcs2" ] && [ "$BOARD_NAME" != "zed_fmcs2" ] && [ "$BOARD_NAME" != "adrv9361z7035" ] && [ "$BOARD_NAME" != "adrv9364z7020" ] && [ "$BOARD_NAME" != "zcu102_fmcs2" ] && [ "$BOARD_NAME" != "zcu102_9371" ]; then
+    echo "\$BOARD_NAME is not correct. Please check!"
+    exit 1
+else
+    echo "\$BOARD_NAME is found!"
+fi
+
+if [ -d "$OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME" ]; then
+    echo "\$OPENWIFI_HW_IMG_DIR is found!"
+else
+    echo "\$OPENWIFI_HW_IMG_DIR is not correct. Please check!"
+    exit 1
+fi
+
+# uncompress the system.hdf and system_top.bit for use
+mkdir -p hdf_and_bit
+rm hdf_and_bit/* -rf
+unzip $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top.xsa -d ./hdf_and_bit
+# cp ./hdf_and_bit/$BOARD_NAME/sdk/system_top_hw_platform_0/system.hdf $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf
+# cp ./hdf_and_bit/system_top.bit $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/ -rf
+
+# BIT_FILENAME=$OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/system_top_hw_platform_0/system_top.bit
+BIT_FILENAME=./hdf_and_bit/system_top.bit
+
+if [ -f "$BIT_FILENAME" ]; then
+    echo "\$BIT_FILENAME is found!"
+else
+    echo "\$BIT_FILENAME does NOT exist. Please check!"
+    exit 1
+fi
+
+if [ "$BOARD_NAME" == "zcu102_fmcs2" ] || [ "$BOARD_NAME" == "zcu102_9371" ]; then
+    ARCH="zynqmp"
+    ARCH_BIT=64
+else
+    ARCH="zynq"
+    ARCH_BIT=32
+fi
+
+# FINAL_BIT_FILENAME=$BOARD_NAME\_system_top_reload.bit.bin
+
+source $XILINX_DIR/Vitis/2021.1/settings64.sh
+
+set -x
+
+cp $BIT_FILENAME ./
+bootgen -image system_top.bif -arch $ARCH -process_bitstream bin -w
+
+# cp system_top_reload.bit.bin ./$FINAL_BIT_FILENAME
+
+cd ../driver
+make clean
+./make_all.sh $XILINX_DIR $ARCH_BIT
+cd ../user_space
+mkdir -p drv_and_fpga
+rm -rf drv_and_fpga/*
+cp system_top.bit.bin ../driver/side_ch/side_ch.ko ../driver/tx_intf/tx_intf.ko ../driver/rx_intf/rx_intf.ko ../driver/openofdm_tx/openofdm_tx.ko ../driver/openofdm_rx/openofdm_rx.ko  ../driver/xpu/xpu.ko ../driver/sdr.ko ./drv_and_fpga -f
+cp $OPENWIFI_HW_IMG_DIR/boards/$BOARD_NAME/sdk/git_info.txt ./drv_and_fpga -f
+tar -cvf ./drv_and_fpga/driver.tar $(git ls-files ../driver/)
+
+# dir_save=$(pwd)
+
+# cd $OPENWIFI_HW_DIR/ip/
+# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-root.tar $(git ls-files ./ | grep -v -E "/|openofdm_rx")
+# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-xpu.tar $(git ls-files ./xpu)
+# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-tx_intf.tar $(git ls-files ./tx_intf)
+# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-rx_intf.tar $(git ls-files ./rx_intf)
+# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-openofdm_tx.tar $(git ls-files ./openofdm_tx)
+# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-ip-side_ch.tar $(git ls-files ./side_ch)
+
+# cd ../boards
+# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-root.tar $(git ls-files ./ | grep -v "/")
+# cd ./$BOARD_NAME
+# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-root.tar $(git ls-files ./ | grep -v "/")
+# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-src.tar $(git ls-files ./src)
+# tar -cvf $dir_save/drv_and_fpga/openwifi-hw-boards-$BOARD_NAME-ip_repo.tar ip_repo
+
+# cd $dir_save
+# # tar -cvf drv_and_fpga.tar system_top.bit.bin tx_intf.ko rx_intf.ko openofdm_tx.ko openofdm_rx.ko xpu.ko sdr.ko git_info.txt
+
+tar -zcvf drv_and_fpga.tar.gz drv_and_fpga
+
+set +x

user_space/eifs_by_last_rx_fail_disable.sh

@@ -0,0 +1,21 @@
+#!/bin/bash
+
+home_dir=$(pwd)
+
+if test -d "/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr"; then
+  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr
+else 
+  cd /sys/devices/soc0/fpga-axi\@0/fpga-axi\@0\:sdr
+fi
+
+set -x
+#set
+if [[ -n $1 ]]; then
+  echo "4$1" > csma_cfg0
+fi
+
+# show
+cat csma_cfg0
+set +x
+
+cd $home_dir

user_space/eifs_by_last_tx_fail_disable.sh

@@ -0,0 +1,21 @@
+#!/bin/bash
+
+home_dir=$(pwd)
+
+if test -d "/sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr"; then
+  cd /sys/devices/platform/fpga-axi@0/fpga-axi@0:sdr
+else 
+  cd /sys/devices/soc0/fpga-axi\@0/fpga-axi\@0\:sdr
+fi
+
+set -x
+#set
+if [[ -n $1 ]]; then
+  echo "5$1" > csma_cfg0
+fi
+
+# show
+cat csma_cfg0
+set +x
+
+cd $home_dir

user_space/fast_reg_log/fast_reg_log.c

@@ -0,0 +1,60 @@
+// Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com)
+// SPDX-FileCopyrightText: 2023 UGent
+// SPDX-License-Identifier: AGPL-3.0-or-later
+
+// Use this example together with fast_reg_log_analyzer.m (notter release)
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <stdint.h>
+
+int main()
+{
+  unsigned int bram_size = 0x10000; // 64KB, aligned with openwifi hw .bd and devicetree
+  off_t bram_pbase = 0x83c40000;    // physical base address, aligned with openwifi hw .bd and devicetree (this example: xpu @ 32bit boards)
+  uint32_t *bram32_vptr;
+  int fd, i, j;
+  uint32_t tsf_reg[524288*2];
+  FILE *fp;
+  // Map the BRAM physical address into user space getting a virtual address for it
+  if ((fd = open("/dev/mem", O_RDONLY | O_SYNC)) != -1) {
+    bram32_vptr = (uint32_t *)mmap(NULL, bram_size, PROT_READ, MAP_SHARED, fd, bram_pbase);
+    
+    fp = fopen ("fast_reg_log.bin", "wb");
+    if (fp == NULL) {
+      printf("fopen fast_reg_log.bin failed! %d\n", (int)fp);
+      close(fd);
+      return(0);
+    }
+
+    for (j=0; j<10; j++) {
+      for (i=0; i<(524288*2); i=i+2) {
+        tsf_reg[i+0] = (*(bram32_vptr+57)); // read xpu register 57: rssi trx agc cca status
+        tsf_reg[i+1] = (*(bram32_vptr+58)); // read xpu register 58: low 32bit of tsf
+      }
+
+      // for (i=0; i<1024; i++) {
+      //   printf("%d %x\n", tsf[i], reg[i]);
+      // }
+      // memcpy(buf, bram64_vptr, bram_size);
+
+      fwrite(tsf_reg, sizeof(uint32_t), 524288*2, fp);
+    }
+
+    fclose(fp);
+    // printf("%016llx\n", buf[65532]);
+    // printf("%016llx\n", buf[65533]);
+    // printf("%016llx\n", buf[65534]);
+    // printf("%016llx\n", buf[65535]);
+    // //for(i=0; i<32; i++) {
+    // //    printf("0x%02x\n", buf[i]);
+    // //}
+
+    close(fd);
+  }
+  return(0);
+}

user_space/fast_reg_log/fast_reg_log_analyzer.m

@@ -0,0 +1,71 @@
+% Author: Xianjun Jiao (xianjun.jiao@imec.be; putaoshu@msn.com)
+% SPDX-FileCopyrightText: 2023 UGent
+% SPDX-License-Identifier: AGPL-3.0-or-later
+
+function fast_reg_log_analyzer(filename_bin, start_idx, end_idx)
+close all;
+
+% if exist('start_idx', 'var')==0 || isempty(start_idx)
+%   start_idx = 1;
+% end
+% 
+% if exist('end_idx', 'var')==0 || isempty(end_idx)
+%   end_idx = 65536;
+% end
+
+filename_csv = [filename_bin(1:(end-3)) 'csv'];
+disp(['Human readable fast reg log will be in ' filename_csv]);
+
+fid = fopen(filename_bin);
+if fid == -1
+    disp('fopen failed!');
+    return;
+end
+
+a = fread(fid, inf, 'uint32');
+fclose(fid);
+% a = bitand(uint32(a), uint32(268435455));
+% plot(a(1:2:end)); hold on;
+% plot(a(2:2:end));
+% legend('1', '2');
+
+a = uint32(a);
+tsf = a(2:2:end);
+% plot(tsf);
+state = a(1:2:end);
+
+% find out overflow idx
+overflow_idx = find(diff([0; double(tsf)])<0, 1, 'first');
+% overflow_idx
+if ~isempty(overflow_idx)
+    tsf(overflow_idx:end) = tsf(overflow_idx:end) + (2^32);
+    disp(num2str(overflow_idx));
+end
+
+rssi_correction = 145;
+rssi_half_db = double(bitand(bitshift(state, 0), uint32((2^11)-1)));
+agc_lock = 1 - double(bitand(bitshift(state, -11), uint32(1)));
+demod_is_ongoing = double(bitand(bitshift(state, -12), uint32(1)));
+tx_is_ongoing = double(bitand(bitshift(state, -13), uint32(1)));
+ch_idle = 1 - double(bitand(bitshift(state, -14), uint32(1)));
+iq_rssi_half_db = double(bitand(bitshift(state, -16), uint32((2^9)-1)));
+agc_gain = double(bitand(bitshift(state, -25), uint32((2^7)-1)));
+
+rssi_dbm = (rssi_half_db./2) - rssi_correction;
+
+figure;
+subplot(2,1,1);
+plot(tsf, -rssi_dbm, 'r+-'); hold on;
+plot(tsf, iq_rssi_half_db, 'bo-');
+plot(tsf, agc_gain, 'ks-');
+legend('rssi dbm', 'iq rssi half db', 'agc gain');
+subplot(2,1,2);
+plot(tsf, agc_lock+0); hold on;
+plot(tsf, demod_is_ongoing+2);
+plot(tsf, tx_is_ongoing+4);
+plot(tsf, ch_idle+6);
+
+legend('agc lock', 'demod is ongoing', 'tx is ongoing', 'ch idle');
+
+a=table(tsf, rssi_half_db, rssi_dbm, iq_rssi_half_db, agc_gain, agc_lock, demod_is_ongoing, tx_is_ongoing, ch_idle);
+writetable(a, filename_csv);

user_space/fosdem-11ag.sh

@@ -4,23 +4,25 @@
 # SPDX-FileCopyrightText: 2019 UGent
 # SPDX-License-Identifier: AGPL-3.0-or-later
 
-test_mode=$1
-if [ -z $test_mode ]
-then
-  test_mode=0
-fi
-echo test_mode $test_mode
+# test_mode=$1
+# if [ -z $test_mode ]
+# then
+#   test_mode=0
+# fi
+# echo test_mode $test_mode
 
 killall hostapd
 killall webfsd
 
 cd ~/openwifi
-service network-manager stop
-./wgd.sh $test_mode
+# service network-manager stop
+# ./wgd.sh $test_mode
 ifconfig sdr0 192.168.13.1
-route add default gw 192.168.10.1
+rm  /var/run/dhcpd.pid
+sleep 1
 service isc-dhcp-server restart
 hostapd hostapd-openwifi-11ag.conf &
 sleep 5
 cd webserver
 webfsd -F -p 80 -f index.html &
+route add default gw 192.168.10.1

user_space/fosdem.sh

@@ -4,23 +4,26 @@
 # SPDX-FileCopyrightText: 2019 UGent
 # SPDX-License-Identifier: AGPL-3.0-or-later
 
-test_mode=$1
-if [ -z $test_mode ]
-then
-  test_mode=0
-fi
-echo test_mode $test_mode
+# test_mode=$1
+# if [ -z $test_mode ]
+# then
+#   test_mode=0
+# fi
+# echo test_mode $test_mode
 
 killall hostapd
 killall webfsd
 
 cd ~/openwifi
-service network-manager stop
-./wgd.sh $test_mode
+# service network-manager stop
+# ./wgd.sh $test_mode
 ifconfig sdr0 192.168.13.1
-route add default gw 192.168.10.1
+rm  /var/run/dhcpd.pid
+sleep 1
 service isc-dhcp-server restart
 hostapd hostapd-openwifi.conf &
 sleep 5
 cd webserver
 webfsd -F -p 80 -f index.html &
+route add default gw 192.168.10.1
+

user_space/hostapd-openwifi-11ag.conf

@@ -3,7 +3,7 @@ driver=nl80211
 country_code=BE
 ssid=openwifi
 hw_mode=a
-channel=44
+channel=36
 supported_rates=60 90 120 180 240 360 480 540
 basic_rates=60 90 120 180
 #ieee80211n=1
@@ -11,6 +11,9 @@ basic_rates=60 90 120 180
 #require_ht=1
 #ieee80211d=1
 #ieee80211h=1
-#wpa=2
-#wpa_passphrase=myrabbit
+#wpa=1
+#wpa_passphrase=openwifi
 #wpa_key_mgmt=WPA-PSK
+#wpa_pairwise=TKIP CCMP
+#wpa_ptk_rekey=600
+

user_space/hostapd-openwifi.conf

@@ -3,7 +3,7 @@ driver=nl80211
 country_code=BE
 ssid=openwifi
 hw_mode=a
-channel=44
+channel=36
 supported_rates=60 90 120 180 240 360 480 540
 basic_rates=60 90 120 180
 ieee80211n=1
@@ -11,6 +11,9 @@ ieee80211n=1
 require_ht=1
 #ieee80211d=1
 #ieee80211h=1
-#wpa=2
-#wpa_passphrase=myrabbit
+#wpa=1
+#wpa_passphrase=openwifi
 #wpa_key_mgmt=WPA-PSK
+#wpa_pairwise=TKIP CCMP
+#wpa_ptk_rekey=600
+

user_space/inject_80211/Makefile

@@ -2,11 +2,12 @@
 all: inject_80211 analyze_80211
 
 inject_80211: inject_80211.c
-	gcc  -Wall -Werror inject_80211.c -o inject_80211 -lpcap
+#	gcc  -Wall -Werror inject_80211.c -o inject_80211 -lpcap
+	gcc  -Wall inject_80211.c -o inject_80211 -lpcap
 
 analyze_80211: analyze_80211.c
-	gcc  -Wall -Werror radiotap.c analyze_80211.c -o analyze_80211 -lpcap
-
+# gcc  -Wall -Werror radiotap.c analyze_80211.c -o analyze_80211 -lpcap
+	gcc  -Wall radiotap.c analyze_80211.c -o analyze_80211 -lpcap
 
 clean:
 	rm -f inject_80211 analyze_80211

user_space/inject_80211/analyze_80211.c

@@ -75,7 +75,7 @@ int main(int argc, char **argv)
 		if (packet_size < 0)
 			continue;
 
-		if (ieee80211_radiotap_iterator_init(&rti, (struct ieee80211_radiotap_header *)packet, packet_size) < 0)
+		if (ieee80211_radiotap_iterator_init(&rti, (struct ieee80211_radiotap_header *)packet, packet_size, NULL) < 0)
 			continue;
 
 		while ((n = ieee80211_radiotap_iterator_next(&rti)) == 0)

user_space/inject_80211/ieee80211_radiotap.h

@@ -1,196 +1,55 @@
 /*
- * Copyright (c) 2003, 2004 David Young.  All rights reserved.
+ * Copyright (c) 2017		Intel Deutschland GmbH
+ * Copyright (c) 2018-2019	Intel Corporation
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of David Young may not be used to endorse or promote
- *    products derived from this software without specific prior
- *    written permission.
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
  *
- * THIS SOFTWARE IS PROVIDED BY DAVID YOUNG ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
- * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL DAVID
- * YOUNG BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
+#ifndef __RADIOTAP_H
+#define __RADIOTAP_H
 
-/*
- * Modifications to fit into the linux IEEE 802.11 stack,
- * Mike Kershaw (dragorn@kismetwireless.net)
- */
-
-#ifndef IEEE80211RADIOTAP_H
-#define IEEE80211RADIOTAP_H
-
-#include <linux/if_ether.h>
 #include <linux/kernel.h>
+// #include <asm/unaligned.h>
 
-/* Base version of the radiotap packet header data */
-#define PKTHDR_RADIOTAP_VERSION		0
-
-/* A generic radio capture format is desirable. There is one for
- * Linux, but it is neither rigidly defined (there were not even
- * units given for some fields) nor easily extensible.
- *
- * I suggest the following extensible radio capture format. It is
- * based on a bitmap indicating which fields are present.
- *
- * I am trying to describe precisely what the application programmer
- * should expect in the following, and for that reason I tell the
- * units and origin of each measurement (where it applies), or else I
- * use sufficiently weaselly language ("is a monotonically nondecreasing
- * function of...") that I cannot set false expectations for lawyerly
- * readers.
- */
-
-/*
- * The radio capture header precedes the 802.11 header.
- * All data in the header is little endian on all platforms.
+/**
+ * struct ieee82011_radiotap_header - base radiotap header
  */
 struct ieee80211_radiotap_header {
-	u8 it_version;		/* Version 0. Only increases
-				 * for drastic changes,
-				 * introduction of compatible
-				 * new fields does not count.
-				 */
-	u8 it_pad;
-	__le16 it_len;		/* length of the whole
-				 * header in bytes, including
-				 * it_version, it_pad,
-				 * it_len, and data fields.
-				 */
-	__le32 it_present;	/* A bitmap telling which
-				 * fields are present. Set bit 31
-				 * (0x80000000) to extend the
-				 * bitmap by another 32 bits.
-				 * Additional extensions are made
-				 * by setting bit 31.
-				 */
-} __packed;
+	/**
+	 * @it_version: radiotap version, always 0
+	 */
+	uint8_t it_version;
 
-/* Name                                 Data type    Units
- * ----                                 ---------    -----
- *
- * IEEE80211_RADIOTAP_TSFT              __le64       microseconds
- *
- *      Value in microseconds of the MAC's 64-bit 802.11 Time
- *      Synchronization Function timer when the first bit of the
- *      MPDU arrived at the MAC. For received frames, only.
- *
- * IEEE80211_RADIOTAP_CHANNEL           2 x __le16   MHz, bitmap
- *
- *      Tx/Rx frequency in MHz, followed by flags (see below).
- *
- * IEEE80211_RADIOTAP_FHSS              __le16       see below
- *
- *      For frequency-hopping radios, the hop set (first byte)
- *      and pattern (second byte).
- *
- * IEEE80211_RADIOTAP_RATE              u8           500kb/s
- *
- *      Tx/Rx data rate
- *
- * IEEE80211_RADIOTAP_DBM_ANTSIGNAL     s8           decibels from
- *                                                   one milliwatt (dBm)
- *
- *      RF signal power at the antenna, decibel difference from
- *      one milliwatt.
- *
- * IEEE80211_RADIOTAP_DBM_ANTNOISE      s8           decibels from
- *                                                   one milliwatt (dBm)
- *
- *      RF noise power at the antenna, decibel difference from one
- *      milliwatt.
- *
- * IEEE80211_RADIOTAP_DB_ANTSIGNAL      u8           decibel (dB)
- *
- *      RF signal power at the antenna, decibel difference from an
- *      arbitrary, fixed reference.
- *
- * IEEE80211_RADIOTAP_DB_ANTNOISE       u8           decibel (dB)
- *
- *      RF noise power at the antenna, decibel difference from an
- *      arbitrary, fixed reference point.
- *
- * IEEE80211_RADIOTAP_LOCK_QUALITY      __le16       unitless
- *
- *      Quality of Barker code lock. Unitless. Monotonically
- *      nondecreasing with "better" lock strength. Called "Signal
- *      Quality" in datasheets.  (Is there a standard way to measure
- *      this?)
- *
- * IEEE80211_RADIOTAP_TX_ATTENUATION    __le16       unitless
- *
- *      Transmit power expressed as unitless distance from max
- *      power set at factory calibration.  0 is max power.
- *      Monotonically nondecreasing with lower power levels.
- *
- * IEEE80211_RADIOTAP_DB_TX_ATTENUATION __le16       decibels (dB)
- *
- *      Transmit power expressed as decibel distance from max power
- *      set at factory calibration.  0 is max power.  Monotonically
- *      nondecreasing with lower power levels.
- *
- * IEEE80211_RADIOTAP_DBM_TX_POWER      s8           decibels from
- *                                                   one milliwatt (dBm)
- *
- *      Transmit power expressed as dBm (decibels from a 1 milliwatt
- *      reference). This is the absolute power level measured at
- *      the antenna port.
- *
- * IEEE80211_RADIOTAP_FLAGS             u8           bitmap
- *
- *      Properties of transmitted and received frames. See flags
- *      defined below.
- *
- * IEEE80211_RADIOTAP_ANTENNA           u8           antenna index
- *
- *      Unitless indication of the Rx/Tx antenna for this packet.
- *      The first antenna is antenna 0.
- *
- * IEEE80211_RADIOTAP_RX_FLAGS          __le16       bitmap
- *
- *     Properties of received frames. See flags defined below.
- *
- * IEEE80211_RADIOTAP_TX_FLAGS          __le16       bitmap
- *
- *     Properties of transmitted frames. See flags defined below.
- *
- * IEEE80211_RADIOTAP_RTS_RETRIES       u8           data
- *
- *     Number of rts retries a transmitted frame used.
- *
- * IEEE80211_RADIOTAP_DATA_RETRIES      u8           data
- *
- *     Number of unicast retries a transmitted frame used.
- *
- * IEEE80211_RADIOTAP_MCS	u8, u8, u8		unitless
- *
- *     Contains a bitmap of known fields/flags, the flags, and
- *     the MCS index.
- *
- * IEEE80211_RADIOTAP_AMPDU_STATUS	u32, u16, u8, u8	unitless
- *
- *	Contains the AMPDU information for the subframe.
- *
- * IEEE80211_RADIOTAP_VHT	u16, u8, u8, u8[4], u8, u8, u16
- *
- *	Contains VHT information about this frame.
- */
-enum ieee80211_radiotap_type {
+	/**
+	 * @it_pad: padding (or alignment)
+	 */
+	uint8_t it_pad;
+
+	/**
+	 * @it_len: overall radiotap header length
+	 */
+	__le16 it_len;
+
+	/**
+	 * @it_present: (first) present word
+	 */
+	__le32 it_present;
+} __attribute__((packed));
+
+/* version is always 0 */
+#define PKTHDR_RADIOTAP_VERSION	0
+
+/* see the radiotap website for the descriptions */
+enum ieee80211_radiotap_presence {
 	IEEE80211_RADIOTAP_TSFT = 0,
 	IEEE80211_RADIOTAP_FLAGS = 1,
 	IEEE80211_RADIOTAP_RATE = 2,
@@ -209,10 +68,15 @@ enum ieee80211_radiotap_type {
 	IEEE80211_RADIOTAP_TX_FLAGS = 15,
 	IEEE80211_RADIOTAP_RTS_RETRIES = 16,
 	IEEE80211_RADIOTAP_DATA_RETRIES = 17,
-
+	/* 18 is XChannel, but it's not defined yet */
 	IEEE80211_RADIOTAP_MCS = 19,
 	IEEE80211_RADIOTAP_AMPDU_STATUS = 20,
 	IEEE80211_RADIOTAP_VHT = 21,
+	IEEE80211_RADIOTAP_TIMESTAMP = 22,
+	IEEE80211_RADIOTAP_HE = 23,
+	IEEE80211_RADIOTAP_HE_MU = 24,
+	IEEE80211_RADIOTAP_ZERO_LEN_PSDU = 26,
+	IEEE80211_RADIOTAP_LSIG = 27,
 
 	/* valid in every it_present bitmap, even vendor namespaces */
 	IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE = 29,
@@ -220,88 +84,284 @@ enum ieee80211_radiotap_type {
 	IEEE80211_RADIOTAP_EXT = 31
 };
 
-/* Channel flags. */
-#define	IEEE80211_CHAN_TURBO	0x0010	/* Turbo channel */
-#define	IEEE80211_CHAN_CCK	0x0020	/* CCK channel */
-#define	IEEE80211_CHAN_OFDM	0x0040	/* OFDM channel */
-#define	IEEE80211_CHAN_2GHZ	0x0080	/* 2 GHz spectrum channel. */
-#define	IEEE80211_CHAN_5GHZ	0x0100	/* 5 GHz spectrum channel */
-#define	IEEE80211_CHAN_PASSIVE	0x0200	/* Only passive scan allowed */
-#define	IEEE80211_CHAN_DYN	0x0400	/* Dynamic CCK-OFDM channel */
-#define	IEEE80211_CHAN_GFSK	0x0800	/* GFSK channel (FHSS PHY) */
+/* for IEEE80211_RADIOTAP_FLAGS */
+enum ieee80211_radiotap_flags {
+	IEEE80211_RADIOTAP_F_CFP = 0x01,
+	IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
+	IEEE80211_RADIOTAP_F_WEP = 0x04,
+	IEEE80211_RADIOTAP_F_FRAG = 0x08,
+	IEEE80211_RADIOTAP_F_FCS = 0x10,
+	IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
+	IEEE80211_RADIOTAP_F_BADFCS = 0x40,
+};
 
-/* For IEEE80211_RADIOTAP_FLAGS */
-#define	IEEE80211_RADIOTAP_F_CFP	0x01	/* sent/received
-						 * during CFP
-						 */
-#define	IEEE80211_RADIOTAP_F_SHORTPRE	0x02	/* sent/received
-						 * with short
-						 * preamble
-						 */
-#define	IEEE80211_RADIOTAP_F_WEP	0x04	/* sent/received
-						 * with WEP encryption
-						 */
-#define	IEEE80211_RADIOTAP_F_FRAG	0x08	/* sent/received
-						 * with fragmentation
-						 */
-#define	IEEE80211_RADIOTAP_F_FCS	0x10	/* frame includes FCS */
-#define	IEEE80211_RADIOTAP_F_DATAPAD	0x20	/* frame has padding between
-						 * 802.11 header and payload
-						 * (to 32-bit boundary)
-						 */
-#define IEEE80211_RADIOTAP_F_BADFCS	0x40	/* bad FCS */
+/* for IEEE80211_RADIOTAP_CHANNEL */
+enum ieee80211_radiotap_channel_flags {
+	IEEE80211_CHAN_CCK = 0x0020,
+	IEEE80211_CHAN_OFDM = 0x0040,
+	IEEE80211_CHAN_2GHZ = 0x0080,
+	IEEE80211_CHAN_5GHZ = 0x0100,
+	IEEE80211_CHAN_DYN = 0x0400,
+	IEEE80211_CHAN_HALF = 0x4000,
+	IEEE80211_CHAN_QUARTER = 0x8000,
+};
 
-/* For IEEE80211_RADIOTAP_RX_FLAGS */
-#define IEEE80211_RADIOTAP_F_RX_BADPLCP	0x0002	/* frame has bad PLCP */
+/* for IEEE80211_RADIOTAP_RX_FLAGS */
+enum ieee80211_radiotap_rx_flags {
+	IEEE80211_RADIOTAP_F_RX_BADPLCP = 0x0002,
+};
 
-/* For IEEE80211_RADIOTAP_TX_FLAGS */
-#define IEEE80211_RADIOTAP_F_TX_FAIL	0x0001	/* failed due to excessive
-						 * retries */
-#define IEEE80211_RADIOTAP_F_TX_CTS	0x0002	/* used cts 'protection' */
-#define IEEE80211_RADIOTAP_F_TX_RTS	0x0004	/* used rts/cts handshake */
-#define IEEE80211_RADIOTAP_F_TX_NOACK	0x0008	/* don't expect an ack */
+/* for IEEE80211_RADIOTAP_TX_FLAGS */
+enum ieee80211_radiotap_tx_flags {
+	IEEE80211_RADIOTAP_F_TX_FAIL = 0x0001,
+	IEEE80211_RADIOTAP_F_TX_CTS = 0x0002,
+	IEEE80211_RADIOTAP_F_TX_RTS = 0x0004,
+	IEEE80211_RADIOTAP_F_TX_NOACK = 0x0008,
+	IEEE80211_RADIOTAP_F_TX_NOSEQNO = 0x0010,
+};
 
+/* for IEEE80211_RADIOTAP_MCS "have" flags */
+enum ieee80211_radiotap_mcs_have {
+	IEEE80211_RADIOTAP_MCS_HAVE_BW = 0x01,
+	IEEE80211_RADIOTAP_MCS_HAVE_MCS = 0x02,
+	IEEE80211_RADIOTAP_MCS_HAVE_GI = 0x04,
+	IEEE80211_RADIOTAP_MCS_HAVE_FMT = 0x08,
+	IEEE80211_RADIOTAP_MCS_HAVE_FEC = 0x10,
+	IEEE80211_RADIOTAP_MCS_HAVE_STBC = 0x20,
+};
 
-/* For IEEE80211_RADIOTAP_MCS */
-#define IEEE80211_RADIOTAP_MCS_HAVE_BW		0x01
-#define IEEE80211_RADIOTAP_MCS_HAVE_MCS		0x02
-#define IEEE80211_RADIOTAP_MCS_HAVE_GI		0x04
-#define IEEE80211_RADIOTAP_MCS_HAVE_FMT		0x08
-#define IEEE80211_RADIOTAP_MCS_HAVE_FEC		0x10
+enum ieee80211_radiotap_mcs_flags {
+	IEEE80211_RADIOTAP_MCS_BW_MASK = 0x03,
+	IEEE80211_RADIOTAP_MCS_BW_20 = 0,
+	IEEE80211_RADIOTAP_MCS_BW_40 = 1,
+	IEEE80211_RADIOTAP_MCS_BW_20L = 2,
+	IEEE80211_RADIOTAP_MCS_BW_20U = 3,
 
-#define IEEE80211_RADIOTAP_MCS_BW_MASK		0x03
-#define		IEEE80211_RADIOTAP_MCS_BW_20	0
-#define		IEEE80211_RADIOTAP_MCS_BW_40	1
-#define		IEEE80211_RADIOTAP_MCS_BW_20L	2
-#define		IEEE80211_RADIOTAP_MCS_BW_20U	3
-#define IEEE80211_RADIOTAP_MCS_SGI		0x04
-#define IEEE80211_RADIOTAP_MCS_FMT_GF		0x08
-#define IEEE80211_RADIOTAP_MCS_FEC_LDPC		0x10
+	IEEE80211_RADIOTAP_MCS_SGI = 0x04,
+	IEEE80211_RADIOTAP_MCS_FMT_GF = 0x08,
+	IEEE80211_RADIOTAP_MCS_FEC_LDPC = 0x10,
+	IEEE80211_RADIOTAP_MCS_STBC_MASK = 0x60,
+	IEEE80211_RADIOTAP_MCS_STBC_1 = 1,
+	IEEE80211_RADIOTAP_MCS_STBC_2 = 2,
+	IEEE80211_RADIOTAP_MCS_STBC_3 = 3,
+	IEEE80211_RADIOTAP_MCS_STBC_SHIFT = 5,
+};
 
-/* For IEEE80211_RADIOTAP_AMPDU_STATUS */
-#define IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN		0x0001
-#define IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN		0x0002
-#define IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN		0x0004
-#define IEEE80211_RADIOTAP_AMPDU_IS_LAST		0x0008
-#define IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR		0x0010
-#define IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN	0x0020
+/* for IEEE80211_RADIOTAP_AMPDU_STATUS */
+enum ieee80211_radiotap_ampdu_flags {
+	IEEE80211_RADIOTAP_AMPDU_REPORT_ZEROLEN = 0x0001,
+	IEEE80211_RADIOTAP_AMPDU_IS_ZEROLEN = 0x0002,
+	IEEE80211_RADIOTAP_AMPDU_LAST_KNOWN = 0x0004,
+	IEEE80211_RADIOTAP_AMPDU_IS_LAST = 0x0008,
+	IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_ERR = 0x0010,
+	IEEE80211_RADIOTAP_AMPDU_DELIM_CRC_KNOWN = 0x0020,
+	IEEE80211_RADIOTAP_AMPDU_EOF = 0x0040,
+	IEEE80211_RADIOTAP_AMPDU_EOF_KNOWN = 0x0080,
+};
 
-/* For IEEE80211_RADIOTAP_VHT */
-#define IEEE80211_RADIOTAP_VHT_KNOWN_STBC			0x0001
-#define IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA			0x0002
-#define IEEE80211_RADIOTAP_VHT_KNOWN_GI				0x0004
-#define IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS		0x0008
-#define IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM	0x0010
-#define IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED			0x0020
-#define IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH			0x0040
-#define IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID			0x0080
-#define IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID		0x0100
+/* for IEEE80211_RADIOTAP_VHT */
+enum ieee80211_radiotap_vht_known {
+	IEEE80211_RADIOTAP_VHT_KNOWN_STBC = 0x0001,
+	IEEE80211_RADIOTAP_VHT_KNOWN_TXOP_PS_NA = 0x0002,
+	IEEE80211_RADIOTAP_VHT_KNOWN_GI = 0x0004,
+	IEEE80211_RADIOTAP_VHT_KNOWN_SGI_NSYM_DIS = 0x0008,
+	IEEE80211_RADIOTAP_VHT_KNOWN_LDPC_EXTRA_OFDM_SYM = 0x0010,
+	IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED = 0x0020,
+	IEEE80211_RADIOTAP_VHT_KNOWN_BANDWIDTH = 0x0040,
+	IEEE80211_RADIOTAP_VHT_KNOWN_GROUP_ID = 0x0080,
+	IEEE80211_RADIOTAP_VHT_KNOWN_PARTIAL_AID = 0x0100,
+};
 
-#define IEEE80211_RADIOTAP_VHT_FLAG_STBC			0x01
-#define IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA			0x02
-#define IEEE80211_RADIOTAP_VHT_FLAG_SGI				0x04
-#define IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9		0x08
-#define IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM		0x10
-#define IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED			0x20
+enum ieee80211_radiotap_vht_flags {
+	IEEE80211_RADIOTAP_VHT_FLAG_STBC = 0x01,
+	IEEE80211_RADIOTAP_VHT_FLAG_TXOP_PS_NA = 0x02,
+	IEEE80211_RADIOTAP_VHT_FLAG_SGI = 0x04,
+	IEEE80211_RADIOTAP_VHT_FLAG_SGI_NSYM_M10_9 = 0x08,
+	IEEE80211_RADIOTAP_VHT_FLAG_LDPC_EXTRA_OFDM_SYM = 0x10,
+	IEEE80211_RADIOTAP_VHT_FLAG_BEAMFORMED = 0x20,
+};
 
-#endif				/* IEEE80211_RADIOTAP_H */
+enum ieee80211_radiotap_vht_coding {
+	IEEE80211_RADIOTAP_CODING_LDPC_USER0 = 0x01,
+	IEEE80211_RADIOTAP_CODING_LDPC_USER1 = 0x02,
+	IEEE80211_RADIOTAP_CODING_LDPC_USER2 = 0x04,
+	IEEE80211_RADIOTAP_CODING_LDPC_USER3 = 0x08,
+};
+
+/* for IEEE80211_RADIOTAP_TIMESTAMP */
+enum ieee80211_radiotap_timestamp_unit_spos {
+	IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MASK = 0x000F,
+	IEEE80211_RADIOTAP_TIMESTAMP_UNIT_MS = 0x0000,
+	IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US = 0x0001,
+	IEEE80211_RADIOTAP_TIMESTAMP_UNIT_NS = 0x0003,
+	IEEE80211_RADIOTAP_TIMESTAMP_SPOS_MASK = 0x00F0,
+	IEEE80211_RADIOTAP_TIMESTAMP_SPOS_BEGIN_MDPU = 0x0000,
+	IEEE80211_RADIOTAP_TIMESTAMP_SPOS_PLCP_SIG_ACQ = 0x0010,
+	IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_PPDU = 0x0020,
+	IEEE80211_RADIOTAP_TIMESTAMP_SPOS_EO_MPDU = 0x0030,
+	IEEE80211_RADIOTAP_TIMESTAMP_SPOS_UNKNOWN = 0x00F0,
+};
+
+enum ieee80211_radiotap_timestamp_flags {
+	IEEE80211_RADIOTAP_TIMESTAMP_FLAG_64BIT = 0x00,
+	IEEE80211_RADIOTAP_TIMESTAMP_FLAG_32BIT = 0x01,
+	IEEE80211_RADIOTAP_TIMESTAMP_FLAG_ACCURACY = 0x02,
+};
+
+struct ieee80211_radiotap_he {
+	__le16 data1, data2, data3, data4, data5, data6;
+};
+
+enum ieee80211_radiotap_he_bits {
+	IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK		= 3,
+	IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU		= 0,
+	IEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU	= 1,
+	IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU		= 2,
+	IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG		= 3,
+
+	IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN	= 0x0004,
+	IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN	= 0x0008,
+	IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN		= 0x0010,
+	IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN	= 0x0020,
+	IEEE80211_RADIOTAP_HE_DATA1_DATA_DCM_KNOWN	= 0x0040,
+	IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN	= 0x0080,
+	IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN	= 0x0100,
+	IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN		= 0x0200,
+	IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN	= 0x0400,
+	IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN	= 0x0800,
+	IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN	= 0x1000,
+	IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN	= 0x2000,
+	IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN	= 0x4000,
+	IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN	= 0x8000,
+
+	IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_KNOWN	= 0x0001,
+	IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN		= 0x0002,
+	IEEE80211_RADIOTAP_HE_DATA2_NUM_LTF_SYMS_KNOWN	= 0x0004,
+	IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN	= 0x0008,
+	IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN		= 0x0010,
+	IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN	= 0x0020,
+	IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN		= 0x0040,
+	IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN	= 0x0080,
+	IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET		= 0x3f00,
+	IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET_KNOWN	= 0x4000,
+	IEEE80211_RADIOTAP_HE_DATA2_PRISEC_80_SEC	= 0x8000,
+
+	IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR		= 0x003f,
+	IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE		= 0x0040,
+	IEEE80211_RADIOTAP_HE_DATA3_UL_DL		= 0x0080,
+	IEEE80211_RADIOTAP_HE_DATA3_DATA_MCS		= 0x0f00,
+	IEEE80211_RADIOTAP_HE_DATA3_DATA_DCM		= 0x1000,
+	IEEE80211_RADIOTAP_HE_DATA3_CODING		= 0x2000,
+	IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG	= 0x4000,
+	IEEE80211_RADIOTAP_HE_DATA3_STBC		= 0x8000,
+
+	IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE	= 0x000f,
+	IEEE80211_RADIOTAP_HE_DATA4_MU_STA_ID		= 0x7ff0,
+	IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1	= 0x000f,
+	IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2	= 0x00f0,
+	IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3	= 0x0f00,
+	IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4	= 0xf000,
+
+	IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC	= 0x000f,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_20MHZ	= 0,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_40MHZ	= 1,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_80MHZ	= 2,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_160MHZ	= 3,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_26T	= 4,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_52T	= 5,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_106T	= 6,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_242T	= 7,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_484T	= 8,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_996T	= 9,
+		IEEE80211_RADIOTAP_HE_DATA5_DATA_BW_RU_ALLOC_2x996T	= 10,
+
+	IEEE80211_RADIOTAP_HE_DATA5_GI			= 0x0030,
+		IEEE80211_RADIOTAP_HE_DATA5_GI_0_8			= 0,
+		IEEE80211_RADIOTAP_HE_DATA5_GI_1_6			= 1,
+		IEEE80211_RADIOTAP_HE_DATA5_GI_3_2			= 2,
+
+	IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE		= 0x00c0,
+		IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_UNKNOWN		= 0,
+		IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_1X			= 1,
+		IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_2X			= 2,
+		IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE_4X			= 3,
+	IEEE80211_RADIOTAP_HE_DATA5_NUM_LTF_SYMS	= 0x0700,
+	IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD		= 0x3000,
+	IEEE80211_RADIOTAP_HE_DATA5_TXBF		= 0x4000,
+	IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG		= 0x8000,
+
+	IEEE80211_RADIOTAP_HE_DATA6_NSTS		= 0x000f,
+	IEEE80211_RADIOTAP_HE_DATA6_DOPPLER		= 0x0010,
+	IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_KNOWN	= 0x0020,
+	IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW		= 0x00c0,
+		IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_20MHZ	= 0,
+		IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_40MHZ	= 1,
+		IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_80MHZ	= 2,
+		IEEE80211_RADIOTAP_HE_DATA6_TB_PPDU_BW_160MHZ	= 3,
+	IEEE80211_RADIOTAP_HE_DATA6_TXOP		= 0x7f00,
+	IEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY	= 0x8000,
+};
+
+struct ieee80211_radiotap_he_mu {
+	__le16 flags1, flags2;
+	u8 ru_ch1[4];
+	u8 ru_ch2[4];
+};
+
+enum ieee80211_radiotap_he_mu_bits {
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS		= 0x000f,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN		= 0x0010,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM		= 0x0020,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN		= 0x0040,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_CTR_26T_RU_KNOWN	= 0x0080,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN		= 0x0100,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_RU_KNOWN		= 0x0200,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU_KNOWN	= 0x1000,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU		= 0x2000,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN	= 0x4000,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN	= 0x8000,
+
+	IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW	= 0x0003,
+		IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_20MHZ	= 0x0000,
+		IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_40MHZ	= 0x0001,
+		IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_80MHZ	= 0x0002,
+		IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_160MHZ	= 0x0003,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN	= 0x0004,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP		= 0x0008,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS	= 0x00f0,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW	= 0x0300,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN= 0x0400,
+	IEEE80211_RADIOTAP_HE_MU_FLAGS2_CH2_CTR_26T_RU		= 0x0800,
+};
+
+enum ieee80211_radiotap_lsig_data1 {
+	IEEE80211_RADIOTAP_LSIG_DATA1_RATE_KNOWN		= 0x0001,
+	IEEE80211_RADIOTAP_LSIG_DATA1_LENGTH_KNOWN		= 0x0002,
+};
+
+enum ieee80211_radiotap_lsig_data2 {
+	IEEE80211_RADIOTAP_LSIG_DATA2_RATE			= 0x000f,
+	IEEE80211_RADIOTAP_LSIG_DATA2_LENGTH			= 0xfff0,
+};
+
+struct ieee80211_radiotap_lsig {
+	__le16 data1, data2;
+};
+
+enum ieee80211_radiotap_zero_len_psdu_type {
+	IEEE80211_RADIOTAP_ZERO_LEN_PSDU_SOUNDING		= 0,
+	IEEE80211_RADIOTAP_ZERO_LEN_PSDU_NOT_CAPTURED		= 1,
+	IEEE80211_RADIOTAP_ZERO_LEN_PSDU_VENDOR			= 0xff,
+};
+
+// /**
+//  * ieee80211_get_radiotap_len - get radiotap header length
+//  */
+// static inline u16 ieee80211_get_radiotap_len(const char *data)
+// {
+// 	struct ieee80211_radiotap_header *hdr = (void *)data;
+
+// 	return get_unaligned_le16(&hdr->it_len);
+// }
+
+#endif /* __RADIOTAP_H */

user_space/inject_80211/inject_80211.c

@@ -22,7 +22,7 @@
 // 2007-03-15 fixes to getopt_long code by Matteo Croce rootkit85@yahoo.it
 
 #include "inject_80211.h"
-#include "radiotap.h"
+#include "ieee80211_radiotap.h"
 
 #define BUF_SIZE_MAX   (1536)
 #define BUF_SIZE_TOTAL (BUF_SIZE_MAX+1) // +1 in case the sprintf insert the last 0
@@ -63,7 +63,7 @@ static const u8 u8aRadiotapHeader[] =
 /* IEEE80211 header */
 static u8 ieee_hdr_data[] =
 {
-	0x08, 0x02, 0x00, 0x00,             // FC 0x0801. 0--subtype; 8--type&version; 02--toDS0 fromDS1 (data packet from DS to STA)
+	0x08, 0x02, 0x00, 0x00,             // FC 0x0802. 0--subtype; 8--type&version; 02--toDS0 fromDS1 (data packet from DS to STA)
 	0x66, 0x55, 0x44, 0x33, 0x22, 0x11, // BSSID/MAC of AP
 	0x66, 0x55, 0x44, 0x33, 0x22, 0x22, // Source address (STA)
 	0x66, 0x55, 0x44, 0x33, 0x22, 0x33, // Destination address (another STA under the same AP)
@@ -142,7 +142,7 @@ void usage(void)
 	    "-h   this menu\n\n"
 
 	    "Example:\n"
-	    "  iw dev wlan0 interface add mon0 type monitor && ifconfig mon0 up\n"
+	    "  iw dev sdr0 interface add mon0 type monitor && ifconfig mon0 up\n"
 	    "  inject_80211 mon0\n"
 	    "\n");
 	exit(1);
@@ -186,6 +186,7 @@ int main(int argc, char *argv[])
 
 			case 'h':
 				usage();
+        break;
 
 			case 'm':
 				hw_mode = optarg[0];
@@ -270,6 +271,7 @@ int main(int argc, char *argv[])
 		ieee_hdr_data[0]  = ( ieee_hdr_data[0]|(sub_type<<4) );
 		ieee_hdr_data[9]  = addr1;
 		ieee_hdr_data[15] = addr2;
+		ieee_hdr_data[21] = addr1;
 		ieee_hdr_len = sizeof(ieee_hdr_data);
 		ieee_hdr = ieee_hdr_data;
 	}
@@ -278,6 +280,7 @@ int main(int argc, char *argv[])
 		ieee_hdr_mgmt[0]  = ( ieee_hdr_mgmt[0]|(sub_type<<4) );
 		ieee_hdr_mgmt[9]  = addr1;
 		ieee_hdr_mgmt[15] = addr2;
+		ieee_hdr_mgmt[21] = addr1;
 		ieee_hdr_len = sizeof(ieee_hdr_mgmt);
 		ieee_hdr = ieee_hdr_mgmt;
 	}

user_space/inject_80211/inject_80211.h

@@ -12,6 +12,7 @@
 #include <pcap.h>
 #include <errno.h>
 
+typedef unsigned long long int u64;
 typedef unsigned int u32;
 typedef unsigned short u16;
 typedef unsigned char u8;