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Update addr2 read-back register

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Thijs Havinga 2023-09-12 12:13:50 +02:00 committed by Xianjun Jiao
parent 3696c5e269
commit f6dab9cd3b
2 changed files with 2 additions and 2 deletions
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2
doc/README.md
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@ -220,9 +220,9 @@ reg_idx|meaning|comment
29|BSSID address high 16bit for BSSID filtering|auto set by xpu_api->XPU_REG_BSSID_FILTER_HIGH_write in openwifi_bss_info_changed of sdr.c
30|MAC address low 32bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c
31|MAC address high 16bit|auto set by XPU_REG_MAC_ADDR_write in sdr.c
37|addr2 of rx packet read back|bit31-0 are from bit47-16 of addr2 field in the received packet
58|TSF runtime value low 32bit|read only
59|TSF runtime value high 32bit|read only
62|addr2 of rx packet read back|bit31-0 are from bit47-16 of addr2 field in the received packet
63|git revision when build the FPGA|returned register value means git revision in hex format
## Rx packet flow and filtering config

2
doc/app_notes/perf_counter.md
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@ -61,4 +61,4 @@ register idx|meaning |note
Note: addr2 (source/sender's MAC address) target setting uses only 32bit. For address 6c:fd:b9:4c:b1:c1, you set b94cb1c1
Note: read register 37 of xpu for some addr2 captured by the receiver
Note: read register 62 of xpu for some addr2 captured by the receiver