Merge pull request #195 from open-sdr/master

Sync master
2025-06-01 23:21:00 +00:00 · 2022-08-02 10:57:33 +02:00 · 2022-08-02 10:57:33 +02:00 · f3b2e60927
commit f3b2e60927
parent f3d767acbb c6dd9e71e5
9 changed files with 55 additions and 48 deletions
--- a/README.md
+++ b/README.md
@ -49,13 +49,13 @@ Openwifi code has dual licenses. [AGPLv3](https://github.com/open-sdr/openwifi/b

 board_name|board combination|status|SD card img|Vivado license
 -------|-------|----|----|-----
-zc706_fmcs2|[Xilinx ZC706 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|Need
-zed_fmcs2|[Xilinx zed board](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|**NO** need
-adrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/adrv9364-z7020.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|**NO** need
-adrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|Need
-zc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|**NO** need
-antsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-32bit.img.xz)|**NO** need
-zcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[64bit img](https://users.ugent.be/~xjiao/openwifi-1.3.0-wilsele-64bit.img.xz)|Need
+zc706_fmcs2|[Xilinx ZC706 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-32bit.img.xz)|Need
+zed_fmcs2|[Xilinx zed board](https://www.xilinx.com/products/boards-and-kits/1-8dyf-11.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-32bit.img.xz)|**NO** need
+adrv9364z7020|[ADRV9364-Z7020 + ADRV1CRR-BOB](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/adrv9364-z7020.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-32bit.img.xz)|**NO** need
+adrv9361z7035|[ADRV9361-Z7035 + ADRV1CRR-BOB/FMC](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/ADRV9361-Z7035.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-32bit.img.xz)|Need
+zc702_fmcs2|[Xilinx ZC702 board](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-32bit.img.xz)|**NO** need
+antsdr|[MicroPhase](https://github.com/MicroPhase/) enhanced ADALM-PLUTO [Notes](kernel_boot/boards/antsdr/notes.md)|Done|[32bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-32bit.img.xz)|**NO** need
+zcu102_fmcs2|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [FMCOMMS2/3/4](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad-fmcomms2.html)|Done|[64bit img](https://users.ugent.be/~xjiao/openwifi-1.3.1-wilsele-64bit.img.xz)|Need
 zcu102_9371|[Xilinx ZCU102 board](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + [ADRV9371](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adrv9371.html)|Future|Future|Need

 - board_name is used to identify FPGA design in openwifi-hw/boards/
@ -244,6 +244,12 @@ Since the pre-built SD card image might not have the latest bug-fixes/updates, i
  **ethX** is the PC NIC name connecting the board ethernet. **NICY** is the PC NIC name connecting internet (WiFi or another ethernet).
  
  If you want, uncommenting "net.ipv4.ip_forward=1" in /etc/sysctl.conf to make IP forwarding persistent on PC.
+- Test the connectivity. Run on board (in the ssh session):
+  ```
+  route add default gw 192.168.10.1
+  ping IP_YOU_KNOW_ON_YOUR_NETWORK
+  ```
+  If there is issue with the connectivity (ping can not reach the target), it needs to be solved before going to the next step.
 - Run **one time** script on board to complete post installation/config (After this, password becomes **openwifi**)
  ```
  cd ~/openwifi && ./post_config.sh
--- a/doc/app_notes/drv_fpga_dynamic_loading.md
+++ b/doc/app_notes/drv_fpga_dynamic_loading.md
@ -10,6 +10,8 @@ The purpose of this feature is to help you easily reload driver and FPGA built f
 - [[Suggested practice to generate driver FPGA variants](#Suggested-practice-to-generate-driver-FPGA-variants)]
 - [[Detailed full usage info](#Detailed-full-usage-info)]

+Note: Make sure you have compiled driver before. Check [Update Driver](../../README.md#update-driver).
+
 ## Reload driver only
 This is the original way. To let **wgd.sh** only loads the driver without touching FPGA, please ensure FPGA image file **system_top.bit.bin** is **NOT** 
 present in the directory. If wgd.sh can not find the FPGA image, it will skip reloading it.
--- a/doc/app_notes/packet-iq-self-loopback-test.md
+++ b/doc/app_notes/packet-iq-self-loopback-test.md
@ -19,24 +19,31 @@ want to understand openwifi side channel (for IQ and CSI) deeper.
 - Put the Tx and Rx antenna as close as possible.
 - Connect a computer to the SDR board via Ethernet cable. The computer should have static IP 192.168.10.1. Open a terminal on the computer, and then in the terminal:
  ```
+  # ssh into the SDR board, password: openwifi
  ssh root@192.168.10.122
-  (password: openwifi)
  cd openwifi
+  # Bring up the openwifi NIC sdr0
  ./wgd.sh
-  (Bring up the openwifi NIC sdr0)
+
+  # Setup monitor mode in WiFi channel 44. You should find a channel as clean as possible in your location. Note that some channels don't work, so stick to 44 or 48 for now.
  ./monitor_ch.sh sdr0 44
-  (Setup monitor mode in WiFi channel 44. You should find a channel as clean as possible in your location)
+
+  # Turn off CCA by setting a very high threshold that make the CSMA engine always think the channel is idle (no incoming signal is higher than this threshold)
+  ./sdrctl dev sdr0 set reg xpu 8 1000
+  
+  # Load side channel kernel module with buffer lenght of 8187 (replace this with 4095 when using low end FPGA board)
  insmod side_ch.ko iq_len_init=8187
-  ./side_ch_ctl wh11d0
-  (Set 0 to register 11. It means the pre trigger length is 0, so we only capture IQ after trigger condition is met)
+  
+  # Set 100 to register 11. It means the pre trigger length is 100, so we mainly capture IQ after trigger condition is met
+  ./side_ch_ctl wh11d100
+  # Set 16 to register 8 -- set trigger condition to phy_tx_started signal from openofdm tx core
  ./side_ch_ctl wh8d16
-  (Set 16 to register 8 -- set trigger condition to phy_tx_started signal from openofdm tx core)
+  # Unmute the baseband self-receiving to receive openwifi own TX signal/packet -- important for self loopback!
  ./sdrctl dev sdr0 set reg xpu 1 1
-  (Unmute the baseband self-receiving to receive openwifi own TX signal/packet -- important for self loopback!)
+  # Set the loopback mode to over-the-air
  ./side_ch_ctl wh5h0
-  (Set the loopback mode to over-the-air)
+  # Relay the FPGA IQ capture to the host computer that will show the captured IQ later on)
  ./side_ch_ctl g0
-  (Relay the FPGA IQ capture to the host computer that will show the captured IQ later on)
  ```
  You should see on outputs like:
  ```
@ -50,11 +57,16 @@ want to understand openwifi side channel (for IQ and CSI) deeper.
  ```
  cd openwifi/inject_80211/
  make
-  (Build our example packet injection program)
+  # Build our example packet injection program
  ./inject_80211 -m n -r 5 -n 1 sdr0
-  (Inject one packet to openwifi sdr0 NIC)
+  # Inject one packet to openwifi sdr0 NIC
  ```
  Normally in the previous ssh session, the count becomes 1. It means one packet (of IQ sample) is sent and captured via loopback over the air.
+  
+  If 1 is not seen, you can try to put the receiver into reset state, so it won't block the system in case it runs into dead state
+  ```
+  ./sdrctl dev sdr0 set reg rx 0 1
+  ```

 - On your computer (NOT ssh onboard!), run:
  ```
@ -80,7 +92,10 @@ to do further offline analysis, or feed the IQ sample to the openwifi receiver s
  ```
  tcpdump -i sdr0
  ```
-  Run the packet injection "./inject_80211 -m n -r 5 -n 1 sdr0" in another session, you should see the packet information printed by tcpdump from self over-the-air loopback.
+  Run the packet injection "./inject_80211 -m n -r 5 -n 1 sdr0" in another session, you should see the packet information printed by tcpdump from self over-the-air loopback. In case you put the receiver into reset state in the previous IQ loopback, you should put the receiver back to normal for packet loopback (otherwise the receiver won't decode the IQ signal back to packet):
+  ```
+  ./sdrctl dev sdr0 set reg rx 0 0
+  ```
  
 - You can also see the openwifi printk message of Rx packet (self Tx looped back) while the packet comes to the openwifi Rx interrupt.
  A new ssh session to the board should be opened to do this before running the packet injection:
@ -88,7 +103,7 @@ to do further offline analysis, or feed the IQ sample to the openwifi receiver s
  cd openwifi
  ./sdrctl dev sdr0 set reg drv_rx 7 7
  ./sdrctl dev sdr0 set reg drv_tx 7 7
-  (Turn on the openwifi Tx/Rx printk logging)
+  # Turn on the openwifi Tx/Rx printk logging
  ```
  Stop the "./side_ch_ctl g0" in the very first ssh session. Run the packet injection, then check the printk message:
  ```
--- a/doc/publications.md
+++ b/doc/publications.md
@ -27,5 +27,7 @@ Other openwifi related publications:
 - [Luca Baldesi, et al. ChARM: NextG Spectrum Sharing Through Data-Driven Real-Time O-RAN Dynamic Control. INFOCOM 2022](https://ece.northeastern.edu/wineslab/papers/BaldesiInfocom22.pdf)
 - [Zelin Yun, et al. RT-WiFi on Software-Defined Radio: Design and Implementation. accepted RTAS2022 paper and demo](https://arxiv.org/abs/2203.10390)
 - [Thijs Havinga, et al. WIP: Achieving Self-Interference-Free Operation on SDR Platform with Critical TDD Turnaround Time. accepted WoWMoM2022 paper](https://arxiv.org/abs/2204.07354)
+- [Pablo Avila-Campos, et al. Impactless Beacon-Based Wireless TSN Association Procedure. 2022 IEEE 18th International Conference on Factory Communication Systems (WFCS)](https://ieeexplore.ieee.org/abstract/document/9779186)
+- [Yingshuo Xi, Baiming Zhang. High-Throughput Open Source Viterbi Decoder for OpenWiFi. 2022 KU Leuven master thesis](https://github.com/BaimingZhang26213/viterbi_decoder)

 **Openwifi was born in ORCA project (EU's Horizon2020 programme under agreement number 732174).**
--- a/doc/videos.md
+++ b/doc/videos.md
@ -5,7 +5,7 @@
 - FOSDEM2021 presentation [[Flash back](https://twitter.com/jxjputaoshu/status/1358462741703491584?s=20)], [[link for CHN user](https://www.zhihu.com/zvideo/1340748826311974912)]; [[Presentation](https://video.fosdem.org/2021/D.radio/fsr_openwifi_opensource_wifi_chip.webm)], [[link for CHN user](https://www.zhihu.com/zvideo/1345036055104360448)]
 - FSF Libreplanet 2021 presentation [[Official](https://media.libreplanet.org/u/libreplanet/m/openwifi-project-the-dawn-of-the-free-libre-wifi-chip/)], [[LinuxReviews](https://linuxreviews.org/Openwifi_project:_The_dawn_of_the_free/libre_WiFi_chip)], [[link for CHN user](https://www.zhihu.com/zvideo/1373649688906883072)]
 - Openwifi industrial real-time high reliable low latency applications (EU Horizon 2020 SHOP4CF project) [[Youtube](https://youtu.be/p7zkkdMvPNc)], [[link for CHN user](https://www.zhihu.com/zvideo/1378413483944538113)]
- CSI fuzzer [[Youtube](https://youtu.be/aOPYwT77Qdw)], [[link for CHN user](https://www.zhihu.com/zvideo/1378409348163506177)]
+- CSI fuzzer [[Youtube](https://youtu.be/aOPYwT77Qdw)], [[link for CHN user](https://www.zhihu.com/zvideo/1378409348163506177)], and ACM WiSec interview [[Youtube](https://youtu.be/ZOCV78aTaQg)], [[link for CHN user](https://www.bilibili.com/video/BV1Mo4y1C76t?share_source=copy_web)]
 - NGI zero, nlnet online session on future of European open hardware [[Session](https://nlnet.nl/news/2021/20210507-NGI-Zero-workshop-open-hardware.html)], [[Original record](https://archive.org/details/ngiforum-open-hardware-workshop-ngizero)], [[Youtube](https://youtu.be/m9Tw5VuHAfk)], [[link for CHN user](https://www.zhihu.com/zvideo/1379302398096285696)]
 - High Precision Time Synchronization on Wi-Fi based Multi-Hop Network [[Youtube](https://youtu.be/m5ryRArbdC8)], [[link for CHN user](https://www.zhihu.com/zvideo/1418222775224492032)]
 - FOSDEM2022 presentation [[Presentation](https://video.fosdem.org/2022/D.radio/radio_openwifi.webm)], [[link for CHN user](https://www.bilibili.com/video/BV12b4y1j7YK?share_source=copy_web)]
--- a/user_space/drv_and_fpga_package_gen.sh
+++ b/user_space/drv_and_fpga_package_gen.sh
@ -71,6 +71,7 @@ bootgen -image system_top.bif -arch $ARCH -process_bitstream bin -w
 # cp system_top_reload.bit.bin ./$FINAL_BIT_FILENAME

 cd ../driver
+make clean
 ./make_all.sh $XILINX_DIR $ARCH_BIT
 cd ../user_space
 mkdir -p drv_and_fpga
--- a/user_space/load_fpga_img.sh
+++ b/user_space/load_fpga_img.sh
@ -33,10 +33,12 @@ rmmod xpu

 sleep 1

-echo 0 > /sys/class/fpga_manager/fpga0/flags
-mkdir -p /lib/firmware
-cp $fpga_img_filename /lib/firmware/
-echo $fpga_img_filename_core > /sys/class/fpga_manager/fpga0/firmware
+if [ -f "$fpga_img_filename" ]; then
+  echo 0 > /sys/class/fpga_manager/fpga0/flags
+  mkdir -p /lib/firmware
+  cp $fpga_img_filename /lib/firmware/ -rf
+  echo $fpga_img_filename_core > /sys/class/fpga_manager/fpga0/firmware
+fi

 # insmod ad9361_drv.ko
 # sleep 1
--- a/user_space/rf_init_11n.sh
+++ b/user_space/rf_init_11n.sh
@ -58,23 +58,14 @@ fi
 set +x

 echo 25215513 >  in_voltage_rf_bandwidth
-sync
 echo 25215414 >  out_voltage_rf_bandwidth
-sync
 echo 40000000 >  in_voltage_sampling_frequency
-sync
 echo 40000000 >  out_voltage_sampling_frequency
-sync
-sleep 1

 echo 1000000000 >  out_altvoltage0_RX_LO_frequency
-sync
 echo 1000000000 >  out_altvoltage1_TX_LO_frequency
-sync

 cat $home_dir/$fir_filename > filter_fir_config
-sync
-sleep 0.5
 echo 1 > in_voltage_filter_fir_en
 echo $tx_fir_enable > out_voltage_filter_fir_en
 cat filter_fir_config
@ -87,7 +78,6 @@ cat in_voltage0_gain_control_mode
 echo fast_attack > in_voltage0_gain_control_mode
 #echo manual > in_voltage0_gain_control_mode
 cat in_voltage0_gain_control_mode
-sync

 echo "rx1 agc fast_attack"
 #echo "rx1 agc manual"
@ -95,8 +85,6 @@ cat in_voltage1_gain_control_mode
 echo fast_attack > in_voltage1_gain_control_mode
 #echo manual > in_voltage1_gain_control_mode
 cat in_voltage1_gain_control_mode
-sync
-sleep 1

 cat in_voltage_sampling_frequency
 cat in_voltage_rf_bandwidth
@ -112,25 +100,21 @@ echo "rx0 gain to 70" # this set gain is gpio gain - 5dB (test with agc and read
 cat in_voltage0_hardwaregain
 echo 70 > in_voltage0_hardwaregain
 cat in_voltage0_hardwaregain
-sync

 echo "rx1 gain to 70"
 cat in_voltage1_hardwaregain
 echo 70 > in_voltage1_hardwaregain
 cat in_voltage1_hardwaregain
-sync

 echo "tx0 gain -89dB"
 cat out_voltage0_hardwaregain
 echo -89 > out_voltage0_hardwaregain
 cat out_voltage0_hardwaregain
-sync

 echo "tx1 gain 0dB"
 cat out_voltage1_hardwaregain
 echo 0 > out_voltage1_hardwaregain
 cat out_voltage1_hardwaregain
-sync
 # #  --------not needed maybe-------- # #

 cd $home_dir
--- a/user_space/wgd.sh
+++ b/user_space/wgd.sh
@ -63,7 +63,6 @@ insert_check_module () {
 }

 print_usage
-sync

 TARGET_DIR=./
 DOWNLOAD_FLAG=0
@ -107,8 +106,6 @@ echo TARGET_DIR $TARGET_DIR
 echo DOWNLOAD_FLAG $DOWNLOAD_FLAG
 echo test_mode $test_mode

-sync
-
 #if ((($test_mode & 0x2) != 0)); then
  tx_offset_tuning_enable=0
 #else
@ -141,6 +138,7 @@ if [ -f "$TARGET_DIR/system_top.bit.bin" ]; then
  ./load_fpga_img.sh $TARGET_DIR/system_top.bit.bin
 else
  echo $TARGET_DIR/system_top.bit.bin not found. Skip reloading FPGA.
+  ./load_fpga_img.sh fjdo349ujtrueugjhj
 fi

 ./rf_init_11n.sh
@ -163,10 +161,7 @@ do
  fi
 done

-if ps -p $(</tmp/check_calib_inf.pid) > /dev/null
-then
-   kill $(</tmp/check_calib_inf.pid)
-fi
+[ -e /tmp/check_calib_inf.pid ] && kill -0 $(</tmp/check_calib_inf.pid)
 ./check_calib_inf.sh

 echo the end