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https://github.com/open-sdr/openwifi.git
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Remove unnecessary code in xpu.c
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1fa7cac08e
commit
ec5a505373
@ -150,14 +150,6 @@ static inline u32 XPU_REG_FORCE_IDLE_MISC_read(void){
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return reg_read(XPU_REG_FORCE_IDLE_MISC_ADDR);
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}
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static inline u32 XPU_REG_TRX_STATUS_read(void){
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return reg_read(XPU_REG_TRX_STATUS_ADDR);
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}
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static inline u32 XPU_REG_TX_RESULT_read(void){
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return reg_read(XPU_REG_TX_RESULT_ADDR);
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}
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static inline u32 XPU_REG_TSF_RUNTIME_VAL_LOW_read(void){
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return reg_read(XPU_REG_TSF_RUNTIME_VAL_LOW_ADDR);
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}
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@ -180,34 +172,6 @@ static inline void XPU_REG_TSF_LOAD_VAL_write(u32 high_value, u32 low_value){
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XPU_REG_TSF_LOAD_VAL_HIGH_write(high_value&(~0x80000000)); // msb low
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}
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static inline u32 XPU_REG_FC_DI_read(void){
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return reg_read(XPU_REG_FC_DI_ADDR);
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}
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static inline u32 XPU_REG_ADDR1_LOW_read(void){
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return reg_read(XPU_REG_ADDR1_LOW_ADDR);
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}
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static inline u32 XPU_REG_ADDR1_HIGH_read(void){
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return reg_read(XPU_REG_ADDR1_HIGH_ADDR);
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}
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static inline u32 XPU_REG_ADDR2_LOW_read(void){
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return reg_read(XPU_REG_ADDR2_LOW_ADDR);
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}
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static inline u32 XPU_REG_ADDR2_HIGH_read(void){
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return reg_read(XPU_REG_ADDR2_HIGH_ADDR);
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}
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// static inline void XPU_REG_LBT_TH_write(u32 value, u32 en_flag) {
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// if (en_flag) {
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// reg_write(XPU_REG_LBT_TH_ADDR, value&0x7FFFFFFF);
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// } else {
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// reg_write(XPU_REG_LBT_TH_ADDR, value|0x80000000);
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// }
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// }
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static inline void XPU_REG_LBT_TH_write(u32 value) {
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reg_write(XPU_REG_LBT_TH_ADDR, value);
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}
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@ -539,21 +503,12 @@ static int dev_probe(struct platform_device *pdev)
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xpu_api->XPU_REG_FORCE_IDLE_MISC_write=XPU_REG_FORCE_IDLE_MISC_write;
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xpu_api->XPU_REG_FORCE_IDLE_MISC_read=XPU_REG_FORCE_IDLE_MISC_read;
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xpu_api->XPU_REG_TRX_STATUS_read=XPU_REG_TRX_STATUS_read;
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xpu_api->XPU_REG_TX_RESULT_read=XPU_REG_TX_RESULT_read;
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xpu_api->XPU_REG_TSF_RUNTIME_VAL_LOW_read=XPU_REG_TSF_RUNTIME_VAL_LOW_read;
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xpu_api->XPU_REG_TSF_RUNTIME_VAL_HIGH_read=XPU_REG_TSF_RUNTIME_VAL_HIGH_read;
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xpu_api->XPU_REG_TSF_LOAD_VAL_LOW_write=XPU_REG_TSF_LOAD_VAL_LOW_write;
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xpu_api->XPU_REG_TSF_LOAD_VAL_HIGH_write=XPU_REG_TSF_LOAD_VAL_HIGH_write;
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xpu_api->XPU_REG_TSF_LOAD_VAL_write=XPU_REG_TSF_LOAD_VAL_write;
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xpu_api->XPU_REG_FC_DI_read=XPU_REG_FC_DI_read;
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xpu_api->XPU_REG_ADDR1_LOW_read=XPU_REG_ADDR1_LOW_read;
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xpu_api->XPU_REG_ADDR1_HIGH_read=XPU_REG_ADDR1_HIGH_read;
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xpu_api->XPU_REG_ADDR2_LOW_read=XPU_REG_ADDR2_LOW_read;
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xpu_api->XPU_REG_ADDR2_HIGH_read=XPU_REG_ADDR2_HIGH_read;
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xpu_api->XPU_REG_LBT_TH_write=XPU_REG_LBT_TH_write;
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xpu_api->XPU_REG_LBT_TH_read=XPU_REG_LBT_TH_read;
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