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Add driver support for euqalizer monitor:
When the equalizer out is too small (48 out of 52/56) for SIGNAL decoding, watchdoc will reset the receiver
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@ -241,6 +241,7 @@ enum openofdm_rx_mode {
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#define OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT 64
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#define OPENOFDM_RX_MIN_PLATEAU_INIT 100
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#define OPENOFDM_RX_FFT_WIN_SHIFT_INIT 1
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#define OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH 48
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#define OPENWIFI_MAX_SIGNAL_LEN_TH 1700 //Packet longer than this threshold will result in receiver early termination. It goes to openofdm_rx/xpu/rx_intf
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@ -97,7 +97,7 @@ static inline u32 hw_init(enum openofdm_rx_mode mode){
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openofdm_rx_api->OPENOFDM_RX_REG_POWER_THRES_write((OPENOFDM_RX_DC_RUNNING_SUM_TH_INIT<<16)|OPENOFDM_RX_POWER_THRES_INIT); // turn on signal watchdog by default
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openofdm_rx_api->OPENOFDM_RX_REG_MIN_PLATEAU_write(OPENOFDM_RX_MIN_PLATEAU_INIT);
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openofdm_rx_api->OPENOFDM_RX_REG_SOFT_DECODING_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|(OPENWIFI_MIN_SIGNAL_LEN_TH<<12)|1); //bit1 enable soft decoding; bit15~12 min pkt length threshold; bit31~16 max pkt length threshold
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openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write(OPENOFDM_RX_FFT_WIN_SHIFT_INIT);
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openofdm_rx_api->OPENOFDM_RX_REG_FFT_WIN_SHIFT_write((OPENOFDM_RX_SMALL_EQ_OUT_COUNTER_TH<<4)|OPENOFDM_RX_FFT_WIN_SHIFT_INIT);
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//rst
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for (i=0;i<8;i++)
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