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Though the SIFS definition in 2.4GHz is 10us, the actual gap is still 16us:

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1. Confirmed by CMW270 in OFDM mode (10us is for 11b where viterbi decoder is not needed)
2. See Signal Extension in 18.3.2.4 ERP-OFDM PPDU format of 802.11-2020
This commit is contained in:
Xianjun Jiao 2023-01-17 13:21:58 +01:00
parent 26825b8b77
commit d4c3d8108e
3 changed files with 10 additions and 6 deletions
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4
driver/sdr.c
View File

@ -1094,7 +1094,8 @@ static void openwifi_tx(struct ieee80211_hw *dev,
if (use_ht_aggr && rate_hw_value==0)
rate_hw_value = 1;
sifs = (priv->actual_rx_lo<2500?10:16);
// sifs = (priv->actual_rx_lo<2500?10:16);
sifs = 16; // for ofdm, sifs is always 16
if (use_ht_rate) {
// printk("%s openwifi_tx: rate_hw_value %d aggr %d sifs %d\n", sdr_compatible_str, rate_hw_value, use_ht_aggr, sifs);
@ -2437,7 +2438,6 @@ static int openwifi_dev_probe(struct platform_device *pdev)
* is mapped on the highst tx ring IDX.
*/
dev->queues = MAX_NUM_HW_QUEUE;
//dev->queues = 1;
ieee80211_hw_set(dev, SIGNAL_DBM);

2
driver/tx_intf/tx_intf.c
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@ -311,7 +311,7 @@ static inline u32 hw_init(enum tx_intf_mode mode, u32 tx_config, u32 num_dma_sym
if (mode!=TX_INTF_AXIS_LOOP_BACK) {
tx_intf_api->TX_INTF_REG_MULTI_RST_write(0);
tx_intf_api->TX_INTF_REG_CSI_FUZZER_write(0);
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(10*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed
tx_intf_api->TX_INTF_REG_CTS_TOSELF_WAIT_SIFS_TOP_write( ((16*10)<<16)|(16*10) );//high 16bit 5GHz; low 16 bit 2.4GHz. counter speed 10MHz is assumed
tx_intf_api->TX_INTF_REG_TX_CONFIG_write(tx_config);
tx_intf_api->TX_INTF_REG_NUM_DMA_SYMBOL_TO_PS_write(num_dma_symbol_to_ps);

10
driver/xpu/xpu.c
View File

@ -433,10 +433,14 @@ static inline u32 hw_init(enum xpu_mode mode){
// xpu_api->XPU_REG_CSMA_CFG_write(268435459); // Linux will do config for each queue via openwifi_conf_tx
// xpu_api->XPU_REG_CSMA_CFG_write(0xe0000000); // Linux will do config for each queue via openwifi_conf_tx
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+23)<<16)|(0+23) );
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
// // ------- assume 2.4 and 5GHz have the same SIFS (6us signal extension) --------
xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+25)<<16)|((16+25)<<0) );
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
// // ------- assume 2.4 and 5GHz have different SIFS --------
// xpu_api->XPU_REG_SEND_ACK_WAIT_TOP_write( ((16+23)<<16)|(0+23) );
// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP0_write( (1<<31) | (((45+2+2)*10 + 15)<<16) | 10 );//2.4GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
// xpu_api->XPU_REG_RECV_ACK_COUNT_TOP1_write( (1<<31) | (((51+2+2)*10 + 15)<<16) | 10 );//5GHz. extra 300 clocks are needed when rx core fall into fake ht detection phase (rx mcs 6M)
xpu_api->XPU_REG_DIFS_ADVANCE_write((OPENWIFI_MAX_SIGNAL_LEN_TH<<16)|2); //us. bit31~16 max pkt length threshold