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Necessary kernel driver patches and kernel_patch_readme.md
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68
kernel_boot/ad9361.patch
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68
kernel_boot/ad9361.patch
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diff --git a/drivers/iio/adc/ad9361.c b/drivers/iio/adc/ad9361.c
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index b21e2129e27c..b53d7b7ab20d 100644
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--- a/drivers/iio/adc/ad9361.c
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+++ b/drivers/iio/adc/ad9361.c
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@@ -1234,7 +1234,7 @@ static int ad9361_load_mixer_gm_subtable(struct ad9361_rf_phy *phy)
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return 0;
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}
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-static int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
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+int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
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bool tx1, bool tx2, bool immed)
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{
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u8 buf[2];
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@@ -1266,8 +1266,8 @@ static int ad9361_set_tx_atten(struct ad9361_rf_phy *phy, u32 atten_mdb,
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return ret;
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}
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-
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-static int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)
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+EXPORT_SYMBOL(ad9361_set_tx_atten);
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+int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)
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{
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u8 buf[2];
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int ret = 0;
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@@ -1285,7 +1285,7 @@ static int ad9361_get_tx_atten(struct ad9361_rf_phy *phy, u32 tx_num)
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return code;
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}
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-
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+EXPORT_SYMBOL(ad9361_get_tx_atten);
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int ad9361_tx_mute(struct ad9361_rf_phy *phy, u32 state)
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{
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struct ad9361_rf_phy_state *st = phy->state;
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@@ -3744,7 +3744,7 @@ static int ad9361_get_auxadc(struct ad9361_rf_phy *phy)
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// Setup Control Outs
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//************************************************************
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-static int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
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+int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
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struct ctrl_outs_control *ctrl)
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{
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struct spi_device *spi = phy->spi;
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@@ -3754,6 +3754,7 @@ static int ad9361_ctrl_outs_setup(struct ad9361_rf_phy *phy,
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ad9361_spi_write(spi, REG_CTRL_OUTPUT_POINTER, ctrl->index); // Ctrl Out index
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return ad9361_spi_write(spi, REG_CTRL_OUTPUT_ENABLE, ctrl->en_mask); // Ctrl Out [7:0] output enable
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}
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+EXPORT_SYMBOL(ad9361_ctrl_outs_setup);
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//************************************************************
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// Setup GPO
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//************************************************************
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@@ -5235,7 +5236,7 @@ static int ad9361_setup(struct ad9361_rf_phy *phy)
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}
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-static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)
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+int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)
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{
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struct ad9361_rf_phy_state *st = phy->state;
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int ret;
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@@ -5268,7 +5269,7 @@ static int ad9361_do_calib_run(struct ad9361_rf_phy *phy, u32 cal, int arg)
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return ret;
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}
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-
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+EXPORT_SYMBOL(ad9361_do_calib_run);
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static int ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,
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u32 rf_rx_bw, u32 rf_tx_bw)
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{
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14
kernel_boot/ad9361_conv.patch
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14
kernel_boot/ad9361_conv.patch
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@ -0,0 +1,14 @@
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diff --git a/drivers/iio/adc/ad9361_conv.c b/drivers/iio/adc/ad9361_conv.c
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index 1902e7d07501..ef421dbd5e70 100644
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--- a/drivers/iio/adc/ad9361_conv.c
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+++ b/drivers/iio/adc/ad9361_conv.c
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@@ -449,7 +449,8 @@ static int ad9361_dig_tune_delay(struct ad9361_rf_phy *phy,
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unsigned long max_freq,
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enum dig_tune_flags flags, bool tx)
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{
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- static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};
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+ // static const unsigned int rates[3] = {25000000U, 40000000U, 61440000U};
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+ static const unsigned int rates[3] = {25000000U, 40000000U, 40000000U};
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struct axiadc_converter *conv = spi_get_drvdata(phy->spi);
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unsigned int s0, s1, c0, c1;
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unsigned int i, j, r;
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13
kernel_boot/axi_hdmi_crtc.patch
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13
kernel_boot/axi_hdmi_crtc.patch
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@ -0,0 +1,13 @@
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diff --git a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c
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index f24669f623d6..70c5769019fa 100644
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--- a/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c
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+++ b/drivers/gpu/drm/adi_axi_hdmi/axi_hdmi_crtc.c
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@@ -54,7 +54,7 @@ static struct dma_async_tx_descriptor *axi_hdmi_vdma_prep_interleaved_desc(
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memset(&vdma_config, 0, sizeof(vdma_config));
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vdma_config.park = 1;
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vdma_config.coalesc = 0xff;
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- xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config);
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+ // xilinx_vdma_channel_set_config(axi_hdmi_crtc->dma, &vdma_config);
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}
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#endif
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6
kernel_boot/kernel_patch_readme.md
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6
kernel_boot/kernel_patch_readme.md
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axi_hdmi_crtc.patch to avoid axi hdmi compiling error after enable Xilinx axi dma.
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ad9361.patch to expose some APIs for openwifi driver.
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ad9361_conv.patch to avoid 61.44Msps lvds interface self timing calibration for some low-end/bad hardware (sometimes difficult).
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