ExternalVendorCode/openwifi
1
0
Fork 0
mirror of https://github.com/open-sdr/openwifi.git synced 2024-12-19 21:58:13 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Update detailed HLS paper link

Browse Source
This commit is contained in:
Thijs Havinga 2023-05-24 09:17:15 +02:00 committed by GitHub
parent 63a8161d18
commit c11f6dddf9
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
doc/app_notes/hls.md
View File

@ -6,7 +6,7 @@ SPDX-License-Identifier: AGPL-3.0-or-later
FCCM2023 Poster: [Thijs Havinga, et al. Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thijs-FCCM2023-poster.jpg)
[Longer/detailed info about the poster](https://github.com/open-sdr/openwifi-hw-img/raw/master/doc_repo/Thijs-FCCM2023.pdf)
[Longer/detailed info about the poster](https://arxiv.org/abs/2305.13351)
In order to speed up or ease FPGA development, it is possible to use High-Level Synthesis (HLS) for creating core baseband processing modules of openwifi. We have already programmed the receiver modules channel estimation and equalization in C++ and converted to Verilog using Vitis HLS. In order to use openwifi with these HLS modules, follow the [build instructions](#build-instructions).
In order to modify these modules within Vitis HLS, follow [the instructions below](#modify-the-code-using-vitis-hls).