Xianjun Jiao
f59c9418a7
Add DEBUG but not enabled
2023-01-09 15:49:23 +01:00
Xianjun Jiao
ad5a5206d3
Remove floating connections
2023-01-09 15:48:23 +01:00
thavinga
95e93cadfd
LVPE correction before estimation
...
- Add state in equalizer and rename others
- Add new dumper files in testbench to check with MATLAB
2023-01-09 15:45:05 +01:00
thavinga
b0df85040f
Add FFT window shift register
2023-01-09 15:40:42 +01:00
Xianjun Jiao
1b0354f85d
Avoid phy_len_calculation out of the watchdog reset scope to have stable value before the next long_preamble_detected
2023-01-09 15:33:57 +01:00
Xianjun Jiao
e83599a85e
Enable threshold scale for receiver and disable power trigger for watchdog by default
2023-01-09 15:32:48 +01:00
Xianjun Jiao
1043429762
signal watchdog only work while rssi above threshold:
...
power_trigger valid
2023-01-09 15:31:52 +01:00
Xianjun Jiao
54bdff7348
Make minimum pkt length configurable for signal_watchdog
2023-01-09 15:30:20 +01:00
Xianjun Jiao
75979e165a
Add fake random +/-1 input while input are 0s:
...
to avoid receiver reset during self-rx-muting (packet sending)
2023-01-09 15:29:33 +01:00
Xianjun Jiao
73475306b7
Add phy len indication for decoding latency prediciton:
...
Add n_ofdm_sym, n_bit_in_last_sym and phy_len_valid to openofdm_rx ip
2023-01-09 15:28:25 +01:00
Xianjun Jiao
4359e4f96d
Add phy len log into dot11_tb
2023-01-09 15:25:29 +01:00
Xianjun Jiao
8ce830c262
Shrink the bits of num_bits_to_decode and deinter_out_count:
...
and adapt the verilog/ofdm_decoder.v accordingly
2023-01-09 15:24:42 +01:00
thavinga
efa844bf0c
Adapt CPE/LVPE calculation
2023-01-09 15:20:16 +01:00
Xianjun Jiao
27392f217f
Adapt the test bench to align with ...
2023-01-09 14:51:55 +01:00
Xianjun Jiao
e978f30de6
Resolve the cpe/lvpe overflow issue
2023-01-09 14:51:06 +01:00
Xianjun Jiao
f455472288
Feed data to ofdm decoder earlier in case a data is missed (arrive too early for ofdm decoder)
2023-01-09 14:50:22 +01:00
Xianjun Jiao
71c9b42d78
Reset internally equalizer after it is disabled to prepare for next round enable
2023-01-09 14:49:31 +01:00
Xianjun Jiao
8e59685c65
Let sync short restart earlier before the end of current packet decoding, so that the next packet can come earlier (smaller inter packet gap is achieved)
2023-01-09 14:48:34 +01:00
Xianjun Jiao
e65ee43101
Make some basic block simpler and its delay more deterministic
2023-01-09 14:47:34 +01:00
Xianjun Jiao
a1e1e0090b
Add threshold_scale and enable it by default:
...
sync short works at low SNR and the receiver sensitivity is better
2023-01-09 14:43:34 +01:00
Xianjun Jiao
6a8818fe5f
extend the status_code to more formated style
2023-01-09 14:40:46 +01:00
Wei Liu
2747d431f9
fix viterbi decoder logging issue
2023-01-05 16:47:07 +01:00
Wei Liu
fe93170efc
log all header bits, also when error occors
2023-01-05 16:45:43 +01:00
Wei Liu
c9f3d280a3
clean up log file, prolong simulation at the end by 300 sp
2023-01-05 16:38:51 +01:00
Xianjun Jiao
707cb99a90
Remove the huge logging thing in dot11_tb.v
2022-07-15 12:10:03 +02:00
Xianjun Jiao
064bbe4250
Auto stop the simulation at the end of iq sample file
2022-05-16 09:53:07 +02:00
Xianjun Jiao
f6fd0a2a85
Minor cleaning
2022-05-16 09:52:24 +02:00
Xianjun Jiao
7622d7aaa0
Disable signal watch dog for normal simulation in the tb
2022-05-16 09:51:30 +02:00
Xianjun Jiao
55f77bb16b
Connect pkt_len from dot11 to signal watch dog in the tb
2022-05-16 09:51:01 +02:00
thavinga
cb6b566d5f
Move all signal logging to dot11_tb.v
2022-05-16 09:33:19 +02:00
Xianjun Jiao
1659c01ac7
Add conditional compiling framework
2022-05-13 13:24:41 +02:00
Xianjun Jiao
a7b95b492c
Workaround to supress the error message when the 1st time run simulation
2022-05-13 13:21:19 +02:00
Xianjun Jiao
4168aa8c7a
Add slv_reg1[4] for option of disabling all smoothing
2022-03-29 12:50:31 +02:00
Xianjun Jiao
39911461ef
Fix the issue of adrv9364z7020: demod_is_ongoing always high. dot11 stuck at state 3
...
Seems new viter decoder IP core does not need this complicated CE signal vit_ce in ofdm_decoder.v
Setting the vit-ce to always 1 fixed the issue
2022-03-23 14:26:41 +01:00
Xianjun Jiao
44c8846072
Add more test vectors into testing_inputs/simulated
2022-03-16 15:07:48 +01:00
Xianjun Jiao
f08c76ca3d
Add signal_watchdog module to prevent fake demod in early phase:
...
1. If strong DC or low frequency sing wave like signal (suspect it is generated by ad9361 during some self-calibration like operation), put the receiver into reset
2. If the signal/header is valid, but the packet length is abnormal (signal_len<14 || signal_len>max_signal_len_th), reset the receiver
2022-03-15 16:03:40 +01:00
Xianjun Jiao
e77f1ba70b
Add git rev tracking to reg 31
2022-03-15 15:57:57 +01:00
Xianjun Jiao
954bae4e77
Add a test vector fake-demod-0.txt that could cause fake demodulation
2022-03-15 15:53:36 +01:00
Xianjun Jiao
40b3e59958
remove unnecessary atan_lut files
2022-03-15 15:52:05 +01:00
Xianjun Jiao
566e82f43e
Add more clock cases into dot11_tb.v
2022-01-28 12:17:16 +01:00
Xianjun Jiao
030cdb34ca
Add force ht smoothing option:
...
> 1. Leave the module always enabled, so the slv_reg1 is free
> 2. Use the slv_reg1 to force ht smoothing
> 3. By default, the smoothing option of the receiver is still controlled by the received ht packet
2022-01-28 12:15:49 +01:00
mmehari
23e61e6a29
Avoid equalizer module processing HT_STF symbol
2022-01-04 22:45:47 +01:00
mmehari
0c75a8e8f2
bug fix: remaining packet length calculation
2022-01-04 22:44:31 +01:00
mmehari
8730912d6f
feature update: sampling frequency offset (SFO) compensation
2022-01-04 22:26:57 +01:00
mmehari
b40c221e67
Advance phase correction value by guard interval size
2022-01-04 22:25:38 +01:00
mmehari
85b1adbec7
bug fix: increase phase calculation delay by 1 CLK
2022-01-04 22:22:00 +01:00
mmehari
e257d3373b
storage update: A-MPDU decoding
2022-01-04 22:20:44 +01:00
mmehari
af855d8c10
Save channel gain information of HT-LTF
2022-01-04 22:19:40 +01:00
mmehari
48aade0190
provide demod_soft_bits and demod_soft_bits_pos signals out
2022-01-04 22:18:23 +01:00
mmehari
84039d7368
Don't catagorize IQ modulation as Q-BPSK or BPSK when I and Q components have the same magnitude
2022-01-04 22:17:12 +01:00
