98 Commits

Author	SHA1	Message	Date
mmehari	d2d5494f57	LTF cross-correlation window update: 16->32 complex samples	2022-01-04 22:16:18 +01:00
mmehari	36c738fe98	phase estimation update: quadrant quantization from 256 slices -> 512 slices	2022-01-04 22:15:16 +01:00
mmehari	53679a107f	integer division rounding fix during phase offset calculation	2022-01-04 22:12:45 +01:00
mmehari	82d2d456e5	keep significant bits while performing division during phase calculation	2022-01-04 22:11:50 +01:00
mmehari	d9649eb614	phase register size reduction: 32bit -> 16bit	2022-01-04 22:10:36 +01:00
mmehari	f3e95eaa92	long preamble detection method update: cross-correlation inter-peak gap distance -> 1st peak detection	2022-01-04 22:07:54 +01:00
mmehari	aaa8ef3ce5	HT/non_HT detection requires at most 9 clocks	2022-01-04 22:05:38 +01:00
mmehari	8bc2d7f0a4	channel smoothing update based on HT-SIG field	2022-01-04 22:03:03 +01:00
mmehari	171ef8b27a	A-MPDU decoding support	2022-01-04 22:01:58 +01:00
mmehari	1a9246fd24	Provide ht_aggregation signal out	2022-01-04 22:00:55 +01:00
mmehari	f83d179cbe	Provide ht_sgi signal out	2020-11-06 13:20:15 +01:00
Xianjun Jiao	d331e66a31	add necessary port as trigger for iq capture feature in openwifi	2020-10-19 09:22:54 +02:00
Xianjun Jiao	8714c30857	output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux	2020-10-08 10:06:03 +02:00
Xianjun Jiao	539133f453	make the code more testbench friendly	2020-09-02 21:59:37 +02:00
Xianjun Jiao	2b3a043e8c	turn on soft_decoding in dot11_tb.v	2020-09-02 17:15:11 +02:00
Xianjun Jiao	bf043af712	change the latency of divider from automatic 60 clocks to the original 36 clock	2020-09-02 16:49:59 +02:00
mmehari	b86951097c	802.11n rx performance fix when used different clock rates (i.e. 100MHz vs 200MHz)	2020-08-30 15:23:07 +02:00
Xianjun Jiao	d7f5806790	fix the atan_addr overflow issue (phase.v)	2020-08-29 14:48:38 +02:00
mmehari	8c59d3a8dd	channel estimation update: frequency domain averaging	2020-08-29 11:41:32 +02:00
mmehari	77e201cfa8	course CFO bug fix	2020-08-29 11:38:06 +02:00
Xianjun Jiao	6a0073ee58	remove debug	2020-06-12 10:24:59 +02:00
Xianjun Jiao	abbe9ecde9	extend support to zcu102/Zynq MPSoC ultra_scale	2020-04-27 15:46:16 +02:00
Jiao Xianjun	03b2591cef	revert to original index ... according to test: https://github.com/open-sdr/openwifi-hw/issues/8	2020-04-17 17:10:23 +02:00
Xianjun Jiao	60677384b9	change the long preamble correlator first 4 sample indexes from 1 2 3 4 to 0 1 2 3	2020-03-28 21:18:33 +01:00
mmehari	66aef6310f	xjiao update: add soft decoding register switch	2019-12-10 13:48:38 +01:00
mmehari	1f8bb83587	soft decoding support for BPSK, QPSK, 16-QAM and 64-QAM	2019-12-10 13:45:43 +01:00
Xianjun Jiao	2643844f2f	necessary bug fixes and improvements for openwifi	2019-12-10 13:31:16 +01:00
weiliu	10ff8da3d7	port dot11 to zynq	2019-12-10 14:09:31 +01:00
Jinghao Shi	079744bec1	fix dot11 port pinout	2017-04-21 13:42:09 -04:00
Jinghao Shi	b7361b2feb	fix port pinout	2017-04-21 13:41:49 -04:00
Jinghao Shi	c0ad55abb6	remve unused variable in descramble.v	2017-04-21 13:41:28 -04:00
Jinghao Shi	556794ae2e	add coregen files	2017-04-14 16:29:33 -04:00
Jinghao Shi	e5d4dc7cfc	enlarge num_sample	2017-04-14 11:01:18 -04:00
Jinghao Shi	701cbb70c9	variable name	2017-04-14 11:00:46 -04:00
Jinghao Shi	0b0723899a	rotate	2017-04-14 11:00:33 -04:00
Jinghao Shi	47577f7099	fix comment	2017-04-14 11:00:12 -04:00
Jinghao Shi	191b197d5e	fix polarity pattern	2017-04-14 11:00:01 -04:00
Jinghao Shi	297162af13	working	2017-04-07 16:51:06 -04:00
Jinghao Shi	20279b42a4	fix long preamble sample beginning index	2017-04-07 16:49:41 -04:00
Jinghao Shi	779b3651a4	remove unused verilog files	2017-04-07 11:36:51 -04:00
Jinghao Shi	8375779a03	refactor name	2017-04-07 11:36:41 -04:00
Jinghao Shi	4dd053ebf8	use delayT	2017-04-07 11:36:21 -04:00
Jinghao Shi	cf42e1b7ae	working	2017-04-03 15:48:25 -04:00
Jinghao Shi	506472dec3	add sim_out dir	2017-04-03 15:25:48 -04:00
Jinghao Shi	1ad9302fc3	readme	2017-04-03 14:31:25 -04:00
Jinghao Shi	d3ff9e7ce8	makefile	2017-04-03 14:05:07 -04:00
Jinghao Shi	bf4701fb39	makefile	2017-04-03 12:59:32 -04:00
Jinghao Shi	9edf1899bd	verilog init	2017-04-03 12:52:03 -04:00