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openofdm/verilog
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Xianjun Jiao 8714c30857 output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux
2020-10-08 10:06:03 +02:00
..
coregen
change the latency of divider from automatic 60 clocks to the original 36 clock
2020-09-02 16:49:59 +02:00
sim_out
add sim_out dir
2017-04-03 15:25:48 -04:00
usrp2
verilog init
2017-04-03 12:52:03 -04:00
Xilinx
extend support to zcu102/Zynq MPSoC ultra_scale
2020-04-27 15:46:16 +02:00
atan_lut.coe
verilog init
2017-04-03 12:52:03 -04:00
atan_lut.mif
verilog init
2017-04-03 12:52:03 -04:00
bits_to_bytes.v
verilog init
2017-04-03 12:52:03 -04:00
calc_mean.v
verilog init
2017-04-03 12:52:03 -04:00
common_defs.v
verilog init
2017-04-03 12:52:03 -04:00
common_params.v
readme
2017-04-03 14:31:25 -04:00
complex_mult.v
port dot11 to zynq
2019-12-10 14:09:31 +01:00
complex_to_mag_sq.v
verilog init
2017-04-03 12:52:03 -04:00
complex_to_mag.v
use delayT
2017-04-07 11:36:21 -04:00
crc32.v
verilog init
2017-04-03 12:52:03 -04:00
deinter_lut.coe
necessary bug fixes and improvements for openwifi
2019-12-10 13:31:16 +01:00
deinter_lut.mif
necessary bug fixes and improvements for openwifi
2019-12-10 13:31:16 +01:00
deinterleave.v
remove debug
2020-06-12 10:24:59 +02:00
delay_sample.v
verilog init
2017-04-03 12:52:03 -04:00
delayT.v
verilog init
2017-04-03 12:52:03 -04:00
demodulate.v
soft decoding support for BPSK, QPSK, 16-QAM and 64-QAM
2019-12-10 13:45:43 +01:00
descramble.v
remve unused variable in descramble.v
2017-04-21 13:41:28 -04:00
divider.v
extend support to zcu102/Zynq MPSoC ultra_scale
2020-04-27 15:46:16 +02:00
dot11_modules.list
verilog init
2017-04-03 12:52:03 -04:00
dot11_side_ch_tb.v
output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux
2020-10-08 10:06:03 +02:00
dot11_tb.v
output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux
2020-10-08 10:06:03 +02:00
dot11.v
output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux
2020-10-08 10:06:03 +02:00
equalizer.v
output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux
2020-10-08 10:06:03 +02:00
ht_sig_crc.v
verilog init
2017-04-03 12:52:03 -04:00
intf_64bit.v
port dot11 to zynq
2019-12-10 14:09:31 +01:00
last_sym_indicator.v
necessary bug fixes and improvements for openwifi
2019-12-10 13:31:16 +01:00
Makefile
makefile
2017-04-03 14:05:07 -04:00
moving_avg.v
verilog init
2017-04-03 12:52:03 -04:00
ofdm_decoder.v
remove debug
2020-06-12 10:24:59 +02:00
openofdm_rx_s_axi.v
xjiao update: add soft decoding register switch
2019-12-10 13:48:38 +01:00
openofdm_rx.v
output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux
2020-10-08 10:06:03 +02:00
phase.v
fix the atan_addr overflow issue (phase.v)
2020-08-29 14:48:38 +02:00
power_trigger.v
port dot11 to zynq
2019-12-10 14:09:31 +01:00
rand_gen_tb.v
verilog init
2017-04-03 12:52:03 -04:00
rand_gen.v
verilog init
2017-04-03 12:52:03 -04:00
rate_to_idx.v
verilog init
2017-04-03 12:52:03 -04:00
rot_lut.coe
verilog init
2017-04-03 12:52:03 -04:00
rot_lut.mif
verilog init
2017-04-03 12:52:03 -04:00
rotate.v
rotate
2017-04-14 11:00:33 -04:00
stage_mult.v
port dot11 to zynq
2019-12-10 14:09:31 +01:00
sync_long.v
output information for openwifi side channel feature: capture timestamp, frequency offset, channel state information and equalizer constellation to Linux
2020-10-08 10:06:03 +02:00
sync_short.v
make the code more testbench friendly
2020-09-02 21:59:37 +02:00
viterbi.v
verilog init
2017-04-03 12:52:03 -04:00